KR100940920B1 - Built-In Self Test device and Phase-Locked Loops including the same, Built-In Self Test scheme and Storage medium storing the same - Google Patents

Abstract

The present invention relates to a self-testing apparatus for a phase locked loop, a phase locked loop including the same, a self-built test method for a phase locked loop, and a storage medium containing the same. More specifically, by detecting the level shift between each divided signal of the frequency divider every clock and calculating the Hamming distance, the internal failure can be quickly tested with little hardware overhead using only the digital signal inside the phase locked loop. The present invention relates to a self-contained test apparatus for a phase locked loop, a phase locked loop including the same, a self-contained test method for a phase locked loop, and a storage medium containing the same.

Phase locked loop, self-contained test device, BIST, overhead, hamming distance

Description

Built-in self test device, phase-locked loop, phase-locked loop self-contained test method and a storage medium including the same (Built-In Self Test device and Phase-Locked Loops including the same, Built-In Self) Test scheme and Storage medium storing the same}

The present invention relates to a self-testing apparatus for a phase locked loop, a phase locked loop including the same, a self-built test method for a phase locked loop, and a storage medium containing the same. More specifically, by detecting the level shift between each divided signal of the frequency divider every clock and calculating the Hamming distance, the internal failure can be quickly tested with little hardware overhead using only the digital signal inside the phase locked loop. The present invention relates to a self-contained test apparatus for a phase locked loop, a phase locked loop including the same, a self-built test method for a phase locked loop, and a storage medium containing the same.

Phase locked loops are widely used in RF systems for frequency synthesis, clock generation in circuits, and clock recovery due to noise. RF systems must be equipped with a frequency source, such as a voltage controlled oscillator (VCO), which is susceptible to fluctuations in output frequency under the influence of circuitry, peripheral equipment, or temperature and weather. In this case, the phase-locking loop fixes the frequency source so as not to shake, and precisely varies the frequency source to a desired frequency. Therefore, testing and correcting whether the phase locked loop is operating normally is related to the performance and accuracy of the overall RF system.

Such a phase locked loop is a block having a mixed signal in which digital blocks such as phase detectors and frequency dividers and mixed analog blocks such as loop filters are mixed. Analog blocks are more sensitive to noise than digital blocks, so there are many things to consider when testing phase locked loops.

As a method for testing a phase locked loop, a separate tester was used. For example, there is a method using a mixed signal tester, a frequency lock test method, an analog test method, and the like. The mixed signal tester method requires complex programming, the frequency fixed test method is simple and quick to test, while the test performance is poor, and the analog test method is expensive, and the output measurement is difficult.

In order to overcome this problem, a method of testing using a digital signal of the phase locked loop itself has been studied, and a method of using a built-in self test has been actively studied. The self-contained test method integrates the tester inside the phase-locked loop, eliminating the need for additional test equipment, resulting in excellent test time and efficiency.

However, self-contained test methods that have been studied up to now show hardware overhead problems, loop breaks in phase locked loops (F. Azais, Y. Bertrand, M. Renovell, A. Ivanov, and S. Tabatabaei, "An all- digital DFT scheme for testing catastrophic faults in PLLs ", IEEE Des. Test Comput., Vol. 20, No. 1, 2003, pp. 60-67.), frequency dividers and critical internal blocks (Chun-Lung, Yiting Lai, and Shu-Wei Wang, "Built-in Self-Test for Phase-Locked Loops", IEEE Trans . on Instruments and Measurement , Vol. 54, No. 3, Jun. 2005, pp. 996-1002.), Junseok Han, Dongsup Song, Hagbae Kim, YoungYong Kim, and Sungho Kang, "An Effective Built-in Self-Test for Chargepump PLL", IEICE Trans . on Electron , Vol . -C E88, No. 8 , Aug. 2005, pp. 1731-1733.) There is a problem of low reliability of the test.

The present invention has been made to solve the above problems, and in particular, by detecting the level shift between each divided signal of the frequency divider every clock and calculating the hamming distance through it, using only the digital signal inside the phase locked loop. The purpose of the present invention is to provide a self-contained test apparatus for a phase locked loop that can quickly test internal failures with low hardware overhead, a phase locked loop including the same, a self-built test method for a phase locked loop, and a storage medium containing the same. have.

In order to achieve the above object, a built-in self test device of a phase locked loop according to the present invention is divided into an original output signal and a frequency of the original output signal of a voltage controlled oscillator of the phase locked loop. A first transition detector which receives the divided signals from the frequency divider of the phase locked loop and detects level transitions between the signals and outputs them in a digital form; A second transition detector for comparing the level transition values output from the first transition detector with the level transition values previously output in time from the first transition detector and outputting the level transitions in a digital form; And a transition count calculation unit calculating the number of transitions through the output value of the second transition detection unit, and determining whether the phase locked loop is faulty.

In addition, the first transition detection unit is a first XOR network 1 for outputting the XOR operation value between the original output signal and the 1/2 divided signal of the divided signal, the 1/2 divided signal and 1/4 divided of the divided signal A first XOR network 2 for outputting an XOR operation value between signals and a first XOR network 3 for outputting an XOR operation value between the quarter divided signal and the 1/8 divided signal among the divided signals, wherein the delay unit D latch 1 to store and output the previous output value of the first XOR network 1, D latch 2 to store and output the previous output value of the first XOR network 2, and to store the previous output value of the first XOR network 3, And a D latch 3 for outputting, wherein the second transition detection unit outputs an XOR operation value between the output value of the first XOR network 1 and the output value of the D latch 1, and the second XOR network 1 of the first XOR network 2. Output value and output of D latch 2 It is possible to include two XOR network 3 to output an XOR operation value between the two XOR network 2, and the second network 3 1 XOR of the output value and the output value of the D latch 3 to output an XOR operation value between.

Phase locked loop according to the present invention is a voltage controlled oscillator (VCO) to make an oscillation according to the change of voltage; A frequency divider which receives the output frequency output from the voltage controlled oscillator and divides it into a low frequency or synthesizes a new frequency; A phase detector detecting a phase difference between a frequency output from the frequency divider and a reference frequency output from a reference frequency oscillator; A charge pump controlling an internal charge by a phase difference detected by the phase detector; And the self-built test apparatus.

The method of building a self-test of a phase locked loop according to the present invention includes (a) receiving the original output signal of the voltage controlled oscillator of the phase locked loop and the divided signals in which the frequency of the original output signal is divided. Outputting the level transition in digital form by performing an XOR (eXclusive OR) operation between the signals; (b) outputting the level transition in digital form by performing an XOR operation between the level transition value output from step (a) and the level transition value previously output in time from step (a); And (c) calculating the number of transitions based on the output value output from the step (b), and determining whether the phase locked loop is faulty.

According to the present invention, the internal failure of the phase locked loop is tested using only the digital signal inside the phase locked loop, thereby minimizing the distortion applied to the analog block that is sensitive to noise such as a loop filter, and detecting the level shift of the divided signals. By testing, the test access is not only simple, the test time and efficiency is high, but the hardware overhead can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are assigned to the same components as much as possible, even if shown on different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related well-known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, the following will describe a preferred embodiment of the present invention, but the technical idea of the present invention is not limited thereto and may be variously modified and modified by those skilled in the art.

First, a phase locked loop to which the self-test device according to the present invention is applied will be described.

1 is a block diagram of a phase locked loop to which a self-testing apparatus according to the present invention is applied.

Referring to FIG. 1, the phase locked loop according to the present invention includes a voltage controlled oscillator 10 (VCO), a frequency divider 20, a phase detector 30, a reference frequency oscillator 40, and a potential pump 50. , Loop filter 60, and self-contained test device 100.

The voltage controlled oscillator 10 serves as a frequency source by generating an oscillation signal according to a change in voltage. The oscillation signal generated by the voltage controlled oscillator 10 is easily shaken by the influence of the circuit itself, the influence of the peripheral equipment, the temperature, and the like. Thus, a phase lock loop is constructed to fix this frequency source so as not to shake. In addition, the phase locked loop may vary the oscillation frequency of the voltage controlled oscillator 10 by adjusting the frequency division value of the frequency divider 20.

The frequency divider 20 receives an output frequency (hereinafter, “F _vco ”) output from the voltage controlled oscillator 10 and divides the frequency into a lower frequency or synthesizes a new frequency by changing the division ratio. For example, when F _vco = 800 MHz, applying a 1/100 division ratio divides at a low frequency of 8 MHz. In addition, when the division ratio is changed to 1/99, the frequency is divided into 8.08 MHz. The frequency divider 20 may operate as a binary counter by continuously connecting flip-flops or the like.

The phase detector 30 detects a phase difference between a frequency output from the frequency divider 20 and a reference frequency (hereinafter, referred to as “F _ref ”) output from the reference frequency oscillator 40. That is, F _ref at the reference frequency oscillator 40 When oscillating a reference frequency of = 8 MHz, a phase difference of 80 kHz is detected if the division ratio is 1/99 as described above. At this time, the phase detector 30 outputs a frequency corresponding to 80kHz as a digital signal in the form of a pulse.

The reference frequency oscillator 40 is preferably a temperature compensated crystal oscillator (Temperature Compensated X-tal Oscillator (TCXO)). The temperature compensated crystal oscillator can maintain the desired output frequency stably without being affected by external temperature.

The potential pump 50 adjusts the internal charge by the phase difference detected through the phase detector 30. That is, the amount of charge is adjusted according to the pulse width output from the phase detector 30. The potential pump 50 adjusts the charge according to the difference between the two signals at the reference voltage value to raise or lower the voltage.

The loop filter 60 accumulates or discharges the electric charge pushed out of the potential pump 50, and filters out noise signals including unwanted harmonic components in the output pulse of the phase detector 30. The loop filter 60 generally filters signals exceeding a desired band by using a low pass filter (LPF).

Among the elements of the phase locked loop, the phase detector and the frequency divider are devices that handle digital signals, but the loop filter is an device that handles analog signals. The fault generated in the phase locked loop affects the internal analog block, and the noise sensitive analog block affects the output frequency of the voltage controlled oscillator. Therefore, in a test using a built-in test device, it is necessary to apply as little variation as possible to sensitive analog blocks such as loop filters, and the built-in test block should not affect the performance of the phase locked loop as a whole. In addition, the test time and efficiency must be excellent and the hardware overhead must be minimized. In order to satisfy this condition, the self-contained test apparatus according to the present invention can test internal faults in a short time while minimizing hardware overhead using only digital signals inside the phase locked loop.

Hereinafter, a self-test apparatus according to a preferred embodiment of the present invention will be described.

2 is a block diagram of a built-in test device according to a preferred embodiment of the present invention. 3 is a block diagram of a self-contained test device implemented by a logic circuit element.

In the self-test apparatus 100 according to a preferred embodiment of the present invention, referring to FIG. 2, the first transition detection unit 110a, 110b, 110c, the second transition detection unit 120a, 120b, 120c, and the delay unit ( 130a, 130b, and 130c, and the transition count calculating unit 150 is included. For convenience, a self-testing device is applied to a phase-locked loop having an output frequency F _vco = 800 MHz of a voltage controlled oscillator, a reference frequency F _ref = 100 MHz of a reference frequency oscillator, and a division ratio of a frequency divider of 1/8. Will be explained.

The first transition detectors 110a, 110b, and 110c receive the original output signal F _vco and the _divided signal of the voltage controlled oscillator 10 from the frequency divider 20 to detect level transitions between the signals and output them in digital form. do. For example, the frequency divider 20 of the eighth frequency divider receives the original output signal F _vco in steps of the original output signal F _vco , the 1/2 frequency division signal F _1/2 , and the 1/4 frequency division signal F _1/4 and The 1/8 divided signal F _1/8 is outputted to the first transition detection units 110a, 110b, and 110c. Therefore, the signal output from the frequency divider 20 becomes F _vco = 800 MHz, F _1/2 = 400 MHz, F _1/4 = 200 MHz, F _1/8 = 100 MHz.

The first transition detectors 110a, 110b, and 110c receive F _vco , F _1/2 , F _1/4 , and F _1/8 from the frequency divider 20 to detect level transitions between signals for each clock. do. As the means for detecting the level transitions from these digital signals, computing elements including NAND and XOR operations, including logic circuit elements, may be used, but XOR operations are preferable to calculate a hamming distance. Do. XOR operations applied to the first transition detection units 110a, 110b, and 110c are the first XOR networks 210a, 210b, and 210c, and are illustrated in FIG. 3. While one positive level of the 1/8 divided signal is in progress, the digital signal value of each clock and each digital signal value pass through the first XOR network 210a, 210b, and 210c while the XOR operation is performed. Table 1 shows.

1/8 frequency division signal 1/4 division signal 1/2 division signal Output signal XOR One One One One 000 One One One 0 001 One One 0 One 011 One One 0 0 010 One 0 One One 110 One 0 One 0 111 One 0 0 One 101 One 0 0 0 100

The operation of Table 1 will be described with reference to the block diagrams of FIGS. 2 and 3.

X0 and X1 signals are input from the frequency divider to the first XOR network 1 210a. At this time, since XO is the level value of the original output signal, X0 = 1, and X1 is the level value of the 1/2 divided signal, so X1 = 1. In this case, when the first XOR network 1 210a performs XOR operation on the values of XO and X1, the value becomes 0. In the same manner, X2 = 1, which is a 1/2 divided signal, X3 = 1, which is a 1/4 divided signal is input to the first XOR network 2 210b, and X2 and X3 are XORed in the first XOR network 2 210b. The operation is zero. Similarly, when X4 = 1, which is a 1/4 division signal, and X5 = 1, which is a 1/8 division signal, are input to the first XOR network 3 210c, and XOR operations of X4 and X5 values are performed on the first XOR network 3 210c. It becomes zero. Thus, combining the output values of the first XOR network 210a, 210b, 210c at the first clock (first row in Table 1) of the 1/8 division signal results in "000". In this way, when the adjacent divided signals are XORed at the next clock, 000 is calculated at the first clock, 001 at the second clock, 011 at the third clock, ... on the basis of the original output signal.

The delay unit includes 130a, 130b, and 130c, and the delay units 130a and 130b store the previous output values of the first transition detectors 110a and 110b and then input the current output values to the second transition detectors 120a and 120b. , Outputs the previous stored value. Logical circuit elements such as S-R latch, D latch, and flip-flop may be used as a means for delaying input digital signals. However, D latch is preferable to perform delay more simply.

The application of the D latch to the delay units 130a, 130b, 130c is shown in FIG. The D latches 230a, 230b, and 230c include D latch 1 230a, D latch 2 230b, and D latch 3 230c. The D latch 1 230a and the D latch 2 230b delay and store the output values of the first XOR network 1 210a and the first XOR network 2 210b, respectively, and then store the output values of the second XOR network 220a at a next clock. , 220b). In the D latches 230a, 230b, and 230c, the reference frequency _Fref generated from the reference frequency oscillator of the phase locked loop serves as an input clock. The reference frequency oscillator uses a temperature compensated crystal oscillator (TCXO) as mentioned above, thereby providing a stable input clock. Since the output frequency F _vco can be distorted by the fault, it is preferable to use the reference frequency F _ref that can generate the most accurate frequency inside the phase locked loop. More specifically, 1 is input from the reference frequency oscillator to the C (Control) terminal of all the D latches 230a, 230b, and 230c, and 1 is input from the reference frequency oscillator to the D (Data) terminal. do. D latch 3 (230c) connected to the second XOR network 3 (230c) of the D latch (230a, 230b, 230c) also receives a reference frequency F _ref as input so that the hamming distance is broken due to synchronization between the distorted frequencies. Prevents undetectable situations.

When 1 is input to C (Control) terminal of D latch 230a, 230b, 230c, the value input to D (Data) terminal is delayed 1 clock based on the original output signal, and the delayed value is output to output terminal Q. do. Since the self-contained test apparatus according to the preferred embodiment of the present invention is configured to check normal operation only when the waveform of the reference frequency oscillator is positive, the C terminal of the D latch 230a, 230b, 230c is 10,000. Input is sufficient. Therefore, the D latches 230a, 230b, and 230c always delay the value input to the D terminal and output the same as it is.

The second transition detectors 120a, 120b, and 120c compare the current output values output from the first transition detectors 110a, 110b, and 110c with the current output values stored in the delay units 130a, 130b, and 130c. Output the level transition of the previous output in digital form. As a means for detecting the level transitions from these digital signals, computing elements including NAND and XOR operations, including a combination of them may be used, but like the first transition detectors 110a, 110b, and 110c, Hamming XOR operation is preferred to calculate the hamming distance. The XOR operations are applied to the second transition detection units 120a, 120b, and 120c, and the second XOR networks 220a, 220b, and 220c are illustrated in FIG. 3. The second XOR network 220a, 220b, 220c outputs an XOR operation value between an output value of the first XOR network 1 210a and an output value of the D latch 1 230a, and the second XOR network 220a, 220b, 220c. A second XOR network 2 (220b) for outputting an XOR operation value between an output value of the first XOR network 2 (210b) and an output value of the D latch 2 (230b), and an output value of the first XOR network 3 (210c) and the A second XOR network 3 (220c) for outputting the XOR operation value between the output value of the D latch 3 (230c). Table 2 shows the results of the XOR operation while passing through the first XOR networks 210a, 210b, and 210c and the adjacent values of the results while passing through the second XOR networks 220a, 220b and 220c.

First XOR Network 2nd XOR Network 000 - 001 001 011 010 010 001 110 100 111 001 101 010 100 001

Referring to Table 2, in the case of the normal waveform, when the output values of the second XOR networks 220a, 220b, and 220c are combined, only one value of 001, 010, and 100 appears.

The transition count calculator 150 calculates the number of transitions based on the output values of the second transition detectors 120a, 120b, and 120c, and determines whether the phase locked loop is broken. That is, when the second transition detectors 120a, 120b, and 120c are implemented by the XOR operator, a 3-bit digital signal is generated by combining the values of the second XOR networks 220a, 220b, and 220c in order. It is determined whether the phase locked loop is operating normally. The transition counting unit 150 combines the output values of the second XOR networks 220a, 220b, and 220c. As a result, the original output signal F _vco of the voltage-controlled oscillator is distorted except when "1" appears only once. To judge. In other words, the normal signal is regarded as output only when "1" appears only once.

It is convenient to utilize the hamming distance as a method of calculating the number of transitions in the transition number calculation unit 150. Hamming distance is defined as the number of different components when comparing two digital signal values for each component. For example, the Hamming distance of the signal values '000111000' and '110111000' is 2. If the Hamming distance is applied to the number of transitions, it is interpreted that the phase-locked loop is operating normally only when the Hamming distance between the delayed previous output and the current output is 1. In Table 2, Hamming distances between output values of the second XOR network are calculated as shown in Table 3 below.

2nd XOR Network Hamming distance - - 001 One 010 One 001 One 100 One 001 One 010 One 001 One

When the original output signal F _vco is normally output as shown in Table 3 above, the hamming distance calculated by the transition number calculation unit 150 becomes 1 in all cases. At this time, the transition count calculation unit 150 determines that the phase lock loop is operating normally. However, when the hamming distance becomes 2 as shown in clock # 2 of Table 4 below, it is determined that the phase locked loop is faulty.

Clock XOR1 XOR2 XOR3 Hamming distance Breakdown #One One 0 0 One normal #2 0 One One 2 broken # 3 0 0 One One normal

That is, the output of 1 once in the final XOR stage means that the Hamming distance is 1 because a transition occurs once in the front and rear values of the output of the D latch.

4 is a view showing the operation waveform of each step of the built-in test device according to a preferred embodiment of the present invention.

The original output signal F _vco , the reference frequency F _ref , the signal F _out input from the frequency divider to the phase detector, the output signal of the first XOR network, the output signal of the D latch, and the output signal of the second XOR network (D latch XORs the output signal and the output signal of the first XOR network).

If it is a normal waveform, only Hamming distance 1 should be detected in the second XOR network such as '001', '010', and '100'. _Referring to the normal waveform located on the left side of FIG. 4, all of them satisfy the Hamming distance 1, but the component that destroys the Hamming distance such as '000' starts to appear in the distorted waveform portion in which the waveform of F _vco is distorted. _If the waveform of F _vco is distorted, their division values, F _1/2 , F _1/4 , and F _1/8, are also distorted, so that Hamming distance 1 is broken through the first XOR network and the second XOR network. do. The failure component is finally detected by the transition count calculator 150 implemented as a combination block to analyze whether there is a defect.

Next, a self-test method according to a preferred embodiment of the present invention will be described.

5 is a flow chart of a self-contained test method according to a preferred embodiment of the present invention. In the following description, an XOR operation is used as a means for detecting a level shift and a D latch is used as a delay means.

In the self-test method according to the preferred embodiment of the present invention, referring to FIG. 5, the frequency division step S10, the first XOR network calculation step S20, the delay step S30, and the second XOR network calculation step ( S40), the transition count calculation step (S50), hamming distance determination step (S60), normal operation (S70) or failure determination step (S80) is made.

In the frequency division step S10, the frequency divider 20 of the phase locked loop receives the original output signal F _vco to generate a division signal, and the first XOR networks 110a, 110b, 110c). In the eighth _frequency division, the signals F _vco , F _1/2 , F _1/4 , and F _{1/8 are} input to the first XOR networks 110a, 110b, and 110c.

The first XOR network operation step S20 is a step of receiving the original output signal and the divided signals of each step from the frequency divider 20 and performing an XOR operation between the signals, and outputting the level transition in digital form. . At this time, each XOR operation is preferably performed every clock based on the original output signal F _vco having the largest number of clocks. In the case of 8 divisions, 8 output values of the XOR operation are given for every positive level of the 1/8 division signal. Referring to Table 1, when the original output signal F is a normal signal, the transition value between the XOR output values per clock becomes 1. That is, if the XOR output values of each clock have a transition value of 1, it can be determined that the phase locked loop is operating normally. In order to implement this process in a circuit, a delay step S30 and a second XOR network operation step S40 are performed.

The delay step S30 stores the previous output value output in the first XOR network operation step S20, and outputs the previous output value stored when the current output value is input to perform the second XOR network operation step S40. It's a step. The D latch element can be used to easily implement this process in a circuit. That is, in order to calculate a transition value between the output values of the first XOR network operation through the second XOR network operation step S40, the delay step S30 stores the previous output value for one clock interval and then inputs the current output value. If so, the previous output value is output so that a second XOR network operation can be performed.

The second XOR network operation step (S40) outputs the level transition in digital form by performing an XOR operation between the previous output value, which has been delayed by one clock through the delay step (S30), and the current output value after the first XOR network operation is completed. It's a step. Referring to Table 2, when the original output signal F is a normal signal, the XOR operation output value between the output values of the first XOR network operation, that is, the output value of the second XOR network operation, takes only one of 001, 010, and 100 values. . In other words, the number of " 1 " is always one in the output value of the second network operation. That is, if the number of "1" is one in the output value of the second XOR network operation per clock, it can be determined that the phase-locked loop is operating normally.

The transition count calculation step (S50) is a step of calculating the number of transitions using the output value output from the second XOR network calculation step (S40), and determines whether or not the phase locked loop failure. Counting the number of " 1 " in the output value of the second XOR network operation results in the number of transitions. The number of "1s" in the output value of the second XOR network operation also coincides with the Hamming distance (see Table 3). If the Hamming distance is 1 through the step S60 of determining whether the Hamming distance is 1, it is determined that the phase locked loop is operating normally (S70). If the Hamming distance is not 1, it is determined that the phase locked loop is faulty. (S80). Referring to Table 4, when the Hamming distance is 1 as in Clocks # 1 and # 3, it is normal operation. If the Hamming distance is not 1 as in Clock # 2, the number of transitions is not 1, so it can be determined that it is out of normal operation.

Meanwhile, the present invention can be embodied as computer readable codes on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored.

Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disks, optical data storage devices, and the like, which may be implemented in the form of a carrier wave (for example, transmission over the Internet). Include. The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. In addition, functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers in the art to which the present invention belongs.

The failure detection rate of the self-testing apparatus of the phase locked loop according to the preferred embodiment of the present invention was measured by experiment.

The phase-locked loop used in this experiment uses a frequency divider with a frequency division ratio of output frequency F = 800MHz and 1/8 of the voltage controlled oscillator, so that the frequency oscillator has a reference frequency F = 100MHz. In the failure model used in the experiment, the short of the transistor is modeled using 1Ω and the transistor open is 10MΩ.

Experiments include drain open (DO), source open (SO), gate open (GO), gate-source short (GSS), gate-drain short (GDS) and drain-source short (DSS) for a total of 1077 failure types. Table 5 shows the fault detection rate measured according to the fault type.

Fault type Fault detection rate (%) DO 100 SO 98.8 GO 81.7 GSS 100 GDS 100 DSS 98.3 Average 96.5

Referring to Table 5, the self-contained test apparatus according to the preferred embodiment of the present invention showed an average failure detection rate of 96.5% for six failure models.

Table 6 compares the self-contained test apparatus according to the preferred embodiment of the present invention with the conventional methods mentioned in the background of the present specification.

Comparative Example 1 Comparative Example 2 Comparative Example 3 Example Test scheme function test Breakdown test Breakdown test Breakdown test Loop type Broken Broken Not broken Not broken Overhead height lowness lowness Lowest Test access complication simple simple simple Test time Slow speed speed speed Fault Cover Rate - good good good

* Comparative Example 1: S. Sunter and A. Roy, "BIST for phase-locked loops in digital applications", in Proc . Int . Test Conf . , Sep. 1999, pp. 532-540.

* Comparative Example 2: Seongwon Kim and Mani Soma, "An All-Digital Built-in Selt-Test for High-Speed Phase-Locked Loops", IEEE Trans . on Circuits and Systems , Vol. 48, No. 2, Feb. 2001, pp. 141-150.

Comparative Example 3: Chun-Lung, Yiting Lai, and Shu-Wei Wang, "Built-in Self-Test for Phase-Locked Loops", IEEE Trans . on Instruments and Measurement , Vol. 54, No. 3, Jun. 2005, pp. 996-1002.

Referring to Table 6, it can be seen that the self-contained test apparatus according to the preferred embodiment of the present invention shows the best results in terms of overall characteristics including loop shape, overhead, test accessibility, and the like.

The above description is merely illustrative of the technical idea of the present invention, and various modifications, changes, and substitutions may be made by those skilled in the art without departing from the essential characteristics of the present invention. will be. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are not intended to limit the technical spirit of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by the embodiments and the accompanying drawings. . The scope of protection of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

Since phase locked loops have various important applications such as frequency synthesis, clock generation in a circuit, and clock recovery due to noise in an RF system, the present invention is applicable to all devices using such phase locked loops. Combined with the software that automatically generates the structure, it can be supplied as a module to CAD-related fields. In particular, the algorithm can be inserted into an existing tool rather than a single item.

1 is a block diagram of a phase locked loop to which a self-testing apparatus according to the present invention is applied.

2 is a block diagram of a built-in test device according to a preferred embodiment of the present invention.

3 is a block diagram of a self-contained test device implemented by a logic circuit element.

4 is a view showing the operation waveform of each step of the built-in test device according to a preferred embodiment of the present invention.

5 is a flow chart of a self-contained test method according to a preferred embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10-voltage controlled oscillator 20-frequency divider

30-Phase Detector 40-Reference Oscillator

50-potential pump 60-loop filter

100-built-in test device

110a, 110b, 110c-first transition detector

120a, 120b, 120c-second transition detector

130a, 130b, 130c-delay

150-Transition Count Calculator

210a, 210b, 210c-first XOR network

220a, 220b, 220c-2nd XOR Network

230a, 230b, 230c-D latch

Claims (16)

In a built-in self test device of a phase locked loop, The source output signal of the voltage-controlled oscillator of the phase locked loop and the divided signals obtained by dividing the frequency of the original output signal are input from a frequency divider of the phase locked loop to detect level transitions between the signals. A first transition detector for outputting the digital form; A second transition detector for comparing the level transition values output from the first transition detector with the level transition values previously output in time from the first transition detector and outputting the level transitions in a digital form; And Transition number calculation unit for calculating the number of transitions through the output value of the second transition detection unit, and determines whether or not the phase lock loop failure Self-built test device of a phase locked loop, characterized in that it comprises a. The method of claim 1, And a delay unit for storing the previous output value of the first transition detector and outputting the stored previous output value when the next output value of the previous output value is input from the first transition detector to the second transition detector. Self-testing device of a phase locked loop, characterized in that. The method of claim 2, The delay unit includes a phase latch (Latch) device, characterized in that the self-test device of a phase locked loop. The method of claim 3, And the input clock of the D latch element is a reference frequency input from a reference frequency oscillator of the phase locked loop. The method of claim 4, wherein Self-testing device of a phase-locked loop, characterized in that for testing the normal operation only when the waveform of the reference frequency oscillator is positive (positive). The method of claim 1, The first transition detection unit and the second transition detection unit is a built-in test device of the phase locked loop, characterized in that implemented by an XOR (eXclusive OR) calculator. The method of claim 6, The transition count calculator is configured to determine that the original output signal of the voltage controlled oscillator is distorted except that the value "1" appears only once as a result of combining the output values of the second transition detector. Built-in test device. The method of claim 6, The transition count calculator determines the operation of the phase-locked loop as normal only when the hamming distance between the previous output value and the current output value of the first transition detector is 1, and then the self-test of the phase-locked loop is performed. Device. The first XOR network 1 of claim 2, wherein the first transition detector outputs an XOR operation value between the original output signal and the 1/2 division signal of the division signal, and the 1/2 division signal of the division signal. A first XOR network 2 for outputting an XOR operation value between quarter division signals and a first XOR network 3 for outputting an XOR operation value between the quarter division signal and the 1/8 division signal among the division signals; The delay unit stores D latch 1, which stores and outputs a previous output value of the first XOR network 1, D latch 2, which stores and outputs a previous output value of the first XOR network 2, and a previous output value of the first XOR network 3. It contains D latch 3, which remembers and outputs The second transition detection unit outputs an XOR operation value between the output value of the first XOR network 1 and the output value of the D latch 1, between the output value of the first XOR network 2 and the output value of the D latch 2. A second XOR network 2 for outputting an XOR operation value, and a second XOR network 3 for outputting an XOR operation value between an output value of the first XOR network 3 and an output value of the D latch 3; Self-contained test device. The method of claim 9, The reference terminal is input to the data terminal and the control terminal of the latch 3, the reference frequency is input from the reference frequency oscillator of the phase locked loop, each of the "1" value input loop self-test device. A voltage controlled oscillator (VCO) for generating oscillations in response to changes in voltage; A frequency divider which receives the output frequency output from the voltage controlled oscillator and divides it into a low frequency or synthesizes a new frequency; A phase detector detecting a phase difference between a frequency output from the frequency divider and a reference frequency output from a reference frequency oscillator; A charge pump controlling an internal charge by a phase difference detected by the phase detector; And Self-contained test device according to any one of claims 1 to 10 Phase locked loop, characterized in that it comprises a. In the method of built-in self test of the phase locked loop, (a) receiving the original output signal of the voltage-controlled oscillator of the phase locked loop and the divided signals divided by the frequency of the original output signal, and performing an XOR (eXclusive OR) operation between the signals to output the level transition in digital form. Making; (b) outputting the level transition in digital form by performing an XOR operation between the level transition value output from step (a) and the level transition value previously output in time from step (a); And (c) calculating the number of transitions based on the output value output from step (b), and determining whether the phase locked loop is faulty Self-built test method of a phase-locked loop comprising a. The method of claim 12, And a delay step of storing the previous output value output in the step (a) and outputting the stored previous output value when the current output value is input to perform the step (b). Self-testing method of phase locked loop. The method of claim 12, The step (c) is a combination of the output value of the step (b) is a self-test method of the phase locked loop, characterized in that it is determined that the normal operation only when the "1" value appears only once. The method of claim 13, After receiving the reference frequency clock from the phase locked loop in the delay step and storing the XOR values in step (a) while the reference frequency is active high, the stored value and the stored value in step (b) Self-testing method of a phase locked loop, characterized in that to perform an XOR operation between the current output value. A computer-readable storage medium in which the self-testing method of the phase locked loop according to any one of claims 12 to 15 is recorded as a program.

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