CN113970692A - Method and system for detecting chip difference - Google Patents
Method and system for detecting chip difference Download PDFInfo
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- CN113970692A CN113970692A CN202111133531.4A CN202111133531A CN113970692A CN 113970692 A CN113970692 A CN 113970692A CN 202111133531 A CN202111133531 A CN 202111133531A CN 113970692 A CN113970692 A CN 113970692A
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The embodiment of the application discloses a method and a system for detecting the difference of chips, which are applied to a system for detecting the difference of chips, wherein the system for detecting the difference of chips comprises a plurality of silicon chip classification and calibration Type SCC Type circuits and SCC control circuits; the method comprises the following steps: the plurality of SCC Type circuits input the output SO signals into the SCC control circuit; the SCC control circuit calculates the circuit delay values of a plurality of SCCType circuits to obtain a plurality of circuit delay values; the SCC control circuit determines whether there is a difference in electrical characteristics of the chips based on the plurality of SO signals and the plurality of circuit delay values. The application provides and uses different kinds of transistors to mix and take and constitute basic SCCtype, can show the area that reduces ROSC and take up on the less car rule level chip of overall size, guarantees the coverage of test, satisfies the higher car rule level standard of stability requirement and to the requirement of chip yield.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and a system for detecting chip differences.
Background
A chip, also called a microcircuit (microcircuit), a microchip (microchip), and an integrated circuit (integrated circuit), refers to a silicon chip containing an integrated circuit, and has a small volume, and is an important component of electronic devices such as computers. The production and manufacturing of chips are an inaccurate process, and the chips produced together may show obvious electrical characteristic differences at different positions, which may affect the stability of the operation of the chips, for example, when the applied voltage of the chip is 0.9V, the chip needs to operate to a frequency region of 320MHz, part of logic may stably operate at this frequency, and a timing violation may occur in part of logic, thereby causing abnormal behavior of the chips. These chips with large internal differences cannot be screened out by Automatic Test Equipment (ATE) tests. Therefore, for the car-scale chip with extremely high requirement on chip stability, how to detect the difference of the chip is an urgent problem to be solved.
Disclosure of Invention
The embodiment of the application provides a method and a system for detecting chip difference, and provides a method for forming basic SCCtype by using transistors of different types in a mixed mode, so that the occupied area of ROSC on a vehicle-scale chip with a small overall size can be obviously reduced, the coverage rate of a test is ensured, and the requirement of a vehicle-scale standard with high stability requirement on the yield of the chip is met.
In a first aspect, an embodiment of the present application provides a method for detecting chip differences, which is applied to a system for detecting chip differences, where the system for detecting chip differences includes multiple silicon wafer classification and calibration Type SCC Type circuits and an SCC control circuit, each SCC Type circuit includes multiple ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types;
the method comprises the following steps:
the plurality of SCC Type circuits input the output SO signals into the SCC control circuit;
the SCC control circuit calculates circuit delay values of the plurality of SCC Type circuits to obtain a plurality of circuit delay values;
the SCC control circuit determines whether there is a difference in electrical characteristics of the chips based on the SO signals and the circuit delay values.
In a second aspect, a system for detecting chip differences provided in an embodiment of the present application includes a plurality of silicon chip classification and calibration Type SCC Type circuits and an SCC control circuit, where each SCC Type circuit includes a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types; wherein the content of the first and second substances,
the plurality of SCC Type circuits are used for inputting the output SO signals into the SCC control circuit;
the SCC control circuit is configured to calculate circuit delay values of the plurality of SCC Type circuits to obtain a plurality of circuit delay values;
the SCC control circuit is further configured to determine whether there is a difference in electrical characteristics between the chips according to the SO signals and the circuit delay values.
In a third aspect, an embodiment of the present application provides a detection apparatus, which includes a processor, a memory, a communication interface, and one or more programs, which are stored in the memory and configured to be executed by the processor, and which include instructions for performing some or all of the steps described in the method of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium storing a computer program for electronic data exchange, wherein the computer program causes a computer to perform some or all of the steps described in the method of the first aspect.
In a fifth aspect, embodiments of the present application provide a computer program product comprising instructions, which, when run on an electronic device, cause the electronic device to perform the method of the first aspect.
The technical scheme provided by the application is applied to a detection system of chip difference, the detection system of chip difference comprises a plurality of silicon chip classification and calibration Type SCC Type circuits and an SCC control circuit, each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types; the plurality of SCC Type circuits input the output SO signals into the SCC control circuit; the method comprises the steps that an SCC control circuit calculates circuit delay values of a plurality of SCC Type circuits to obtain a plurality of circuit delay values; the SCC control circuit determines whether there is a difference in electrical characteristics of the chips based on the plurality of SO signals and the plurality of circuit delay values. The application provides and uses different kinds of transistors to mix and take and constitute basic SCCtype, can show the area that reduces ROSC and take up on the less car rule level chip of overall dimension, reflects the electrical characteristics difference of chip through the SO signal with SCC Type circuit output simultaneously, has guaranteed the coverage of test, satisfies the requirement of the higher car rule level standard of stability requirement to the chip yield.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a system for detecting chip differences according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an SCC type circuit according to an embodiment of the present application;
fig. 3 is a schematic flowchart of a method for detecting chip differences according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a detection apparatus provided in an embodiment of the present application.
Detailed Description
Before describing the technical solutions of the embodiments of the present application, the following introduces related concepts that may be involved in the present application.
Ring oscillator (RingOscillator, ROSC): the ring oscillator is mainly characterized in that the ring oscillator can measure the circuit delay with high precision so as to represent the circuit aging.
Silicon wafer classification and calibration (SCC): the method is characterized in that the silicon chips are classified according to physical differences shown after production and manufacturing, parameters such as chip power supply voltage and the like are correspondingly adjusted, and the chips can be guaranteed to operate under the set performance.
Binning: the classification of chips refers to dividing chips into different bins according to the output result of the SCC, so as to characterize the differences of the different bins.
SCCtype: and a minimum SCC execution unit composed of a plurality of ROSCs and a shift register.
Voltage modulation (VT): the voltage regulation operation is particularly performed on sctype.
Automatic integrated circuit tester (ATE): the method is used for detecting the integrity of the functions of the integrated circuit so as to ensure that the internal sequential logic operation of the chip has no hardware errors.
In order to better understand the technical solutions of the present application, the following description is given for clarity and completeness in conjunction with the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person skilled in the art without making any inventive step on the basis of the description of the embodiments of the present application belong to the protection scope of the present application.
The terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, software, product, or apparatus that comprises a list of steps or elements is not limited to those listed but may include other steps or elements not listed or inherent to such process, method, product, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a system for detecting chip differences according to an embodiment of the present disclosure. As shown in fig. 1, the system 100 for detecting chip variability includes a plurality of silicon chip classification and calibration Type SCC Type circuits 110 and an SCC control circuit 120. Wherein the output of every SCC Type circuit 110 is connected with SCC control circuit 120, and every SCC Type circuit 110 carries out chip difference screening to the chip to send the output result of screening to SCC control circuit 120, then judge whether its chip has electrical characteristic difference by SCC control circuit 120 according to the output signal of every SCC Type circuit 110. Illustratively, the SCC control circuitry 120 may connect external components via a BUS (BUS) and receive a BUS signal (Signals).
For example, as shown in fig. 1, the SCC control circuitry 120 may include an SCC Type interface, an SCC controller, and an SCC register set. The whole chip may include a plurality of SCC Type circuits 110, each bit represents one SCC Type circuit, and the SCC control may receive the SO signals output by the plurality of SCC Type circuits 110 through the SCC Type interface, and may select an SO signal of any one SCC Type from the plurality of SO signals to reflect the electrical characteristic differences of the circuits. Where the SCC register sets may be used to store final results and/or parameters required by the SCC controller.
For example, as shown in fig. 2, fig. 2 is a schematic structural diagram of an SCC Type circuit 110 according to an embodiment of the present application. As shown in fig. 2, the SCC Type circuit includes a plurality of ring oscillator ROSC chains each formed of a different kind of transistor, and a ripple counter (ripple counter) that captures a square wave output from the ROSC and converts the square wave into a serial data output SO signal.
Wherein, the ROSC includes different combinational logics (combinational logics such as AND gate, OR gate, NOT gate and the like), each logic selects different kinds of transistors (such as NOT gate selecting type A transistor and AND gate selecting type B transistor) according to different kinds of actual selection cells (cells) in a test area, in the actual process production, the produced transistors have process deviation, that is, the characteristics of transistors produced under the same design are different, the difference is amplified by the delay (delay) generated by an odd number of ring oscillators connected in series, (the phase difference is amplified under the superposition of a plurality of inverters due to the delay, when the phase change reaches 180 degrees compared with the initial phase, the circuit oscillation is realized), by presetting a sampling period number (N), counting the oscillation number in the period by a counter can be used for representing the delay condition of the circuit. Furthermore, the SO signal output by the SCC Type circuit can represent the circuit delay value of the ROSC embedded region, SO that the electrical characteristic difference of the circuit is reflected.
Wherein the plurality of SCC Type circuits are used for inputting the output SO signal into the SCC control circuit; the SCC control circuit is used for calculating circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values, and determining whether the chip has electrical characteristic differences according to the SO signals and the circuit delay values.
Specifically, the delay values of different logic units on the ROSC chain may cause differences in SO signals output by the SCC Type, and the SCC control circuit may perform data conversion on the received SO signals to calculate a circuit delay value corresponding to the SO value, SO as to represent the circuit delay value in the ROSC embedded region, thereby reflecting differences in electrical characteristics of the circuit.
Optionally, in calculating the circuit delay values of the multiple SCC Type circuits to obtain multiple circuit delay values, the SCC control circuit is specifically configured to: acquiring sampling clock cycles of the plurality of SCC Type circuits to obtain a plurality of sampling clock cycles; respectively inputting the multiple sampling clock periods into a first formula for calculation to obtain the multiple circuit delay values, wherein the first formula is represented as: g ═ N × S)/T, where N is a preset number of sampling cycles, S is the sampling clock cycle, and T is a constant.
The set sampling cycle number N can be stored in advance in an SCC register group in the SCC control circuit, wherein the N can be any value, and in order to guarantee the reliability of a test result, the test can be performed in different cycles. T is a single cycle of the delay line on the ROSC chain, which is a constant, process specific, value, which is the time of one square wave period on the ROSC chain, for the process and transistor type, to calculate the standard (golden) value of the square wave number and the process related parameter.
Specifically, the SCC controller calculates a test value (circuit delay value) which is the number of square waves formed after the ROSC in the sampling time by the formula, and the value is a standard value. By comparing the circuit delay value obtained in the actual test with the standard value, whether the tested chip has electrical property difference can be judged. Specifically, if the difference value between the delay value of the circuit and the standard value is greater than or equal to a preset value during actual test, the chip is considered to have electrical property difference; and if the difference value between the circuit delay value and the standard value obtained in the actual test is smaller than the preset value, the chip is considered to have no electrical property difference. The preset value can be preset or set according to actual requirements, and the embodiment of the application does not limit the preset value.
Optionally, the SCC control circuit is disposed in a power domain capable of power down.
In the embodiment of the application, an SCC controller in the SCC control circuit performs data interaction with the outside through an SCC bus interface, and realizes the interaction with the SCCtype circuit through an SCCtype interface. The control circuit of present SCC arranges normally open power domain in, and the consumption that leads to causing is lost great, consequently this application arranges SCC control circuit wholly in the power domain that the chip can fall the electricity, can control to open only when carrying out the ATE test, and the function logic of this logic and circuit normal during operation does not influence each other, can follow the system and close together, has reduced the circuit consumption when actual work to the realization is to the influence minimizing of the whole consumption of system.
Referring to fig. 3, fig. 3 is a schematic flow chart of a method for detecting chip differences according to an embodiment of the present disclosure, applied to a system for detecting chip differences shown in fig. 1. As shown in fig. 3, the method includes the following steps.
And S310, the plurality of SCC Type circuits input the output SO signals into the SCC control circuit.
A plurality of SCC Type circuits may be included in one chip, and each SCC Type circuit includes a plurality of transistors of different types to form a ROSC chain. Since the ROSC chain includes different combinational logics (combinational logics such as AND gate, OR gate, NOT gate and the like), each logic selects different kinds of transistors according to different kinds of actually selected cells in a test area. The characteristics of the transistors are different, the difference is amplified by the delay generated by an odd number of serially connected ring oscillators, and the number of oscillations in the period counted by a counter can be used for representing the delay condition of the circuit. Furthermore, the SO signal output by the SCC Type circuit can represent the circuit delay value of the ROSC embedded region, SO that the electrical characteristic difference of the circuit is reflected. Therefore, each SCC Type circuit sends the SO signal output by the SCC Type circuit to the SCC control circuit, and the SCC control circuit logically judges whether the chip has electrical property difference or not.
Optionally, the SCC Type circuit further includes a ripple counter; the method further comprises the following steps: and the wave connection counter converts the square waves output by the ROSC chains into the serial SO signals.
The SCC Type circuit comprises a plurality of ROSC chains, each ROSC chain has an output result, and the delay values of different logic units on each ROSC chain can cause the SO signals output by the ROSC chains to have difference; while one chip may include multiple SCC Type circuits. Consequently this application catches the square wave of a plurality of ROSC outputs through the ripples counter of linking to change into serial SO signal, thereby make things convenient for the SCC controller to detect the chip through the output SO signal of this SCC Type circuit.
S320, the SCC control circuit calculates circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values.
In this embodiment of the application, the delay values of different logic units in the ROSC chain may cause a difference in SO signals output by the SCC Type, and the SCC control circuit may perform data conversion on the received SO signals to calculate a circuit delay value corresponding to the SO value, SO as to represent the circuit delay value in the ROSC embedded region, thereby reflecting the difference in electrical characteristics of the circuit.
Optionally, the SCC controlling circuit calculates circuit delay values of the multiple SCC Type circuits to obtain multiple circuit delay values, including: the SCC control circuit acquires sampling clock cycles of the plurality of SCC Type circuits to obtain a plurality of sampling clock cycles; the SCC control circuit inputs the sampling clock periods into a first formula respectively for calculation, to obtain the circuit delay values, where the first formula is expressed as: g ═ N × S)/T, where N is a preset number of sampling cycles, S is the sampling clock cycle, and T is a constant.
The set sampling cycle number N can be stored in advance in an SCC register group in the SCC control circuit, wherein the N can be any value, and in order to guarantee the reliability of a test result, the test can be performed in different cycles. T is a single cycle of the delay line on the ROSC chain, which is a constant, process specific, value, which is the time of one square wave period on the ROSC chain, for the process and transistor type, to calculate the standard (golden) value of the square wave number and the process related parameter.
S330, the SCC control circuit determines whether the chip has electrical characteristic difference according to the SO signals and the circuit delay values.
Optionally, the SCC controlling circuit determines whether there is an electrical characteristic difference between the chips according to the plurality of SO signals and the plurality of circuit delay values, including: the SCC control circuit calculates an absolute value of a difference between an ith SO signal and a corresponding circuit delay value to obtain a first difference value; if the first difference is greater than a preset value, the SCC control circuit determines that a first SCC Type circuit has an electrical characteristic difference, where the first SCC Type circuit is an SCC Type circuit corresponding to the ith SO signal; if the first difference is less than or equal to the preset value, the SCC control circuit determines that the first SCC Type circuit has no electrical characteristic difference.
Specifically, the SCC controller may select any one SO signal from the plurality of SO signals to perform the calculation. A test value (circuit delay value) is calculated by the formula, namely the number of square waves formed after ROSC in the sampling time is a standard value. By comparing the circuit delay value obtained in the actual test with the standard value, whether the tested chip has electrical property difference can be judged. Specifically, if the difference value between the delay value of the circuit and the standard value is greater than or equal to a preset value during actual test, the chip is considered to have electrical property difference; and if the difference value between the circuit delay value and the standard value obtained in the actual test is smaller than the preset value, the chip is considered to have no electrical property difference. The preset value can be preset or set according to actual requirements, and the embodiment of the application does not limit the preset value.
Optionally, the SCC control circuit is disposed in a power domain capable of power down.
In the embodiment of the application, an SCC controller in an SCC control circuit performs data interaction with the outside through an SCC bus interface, and realizes the interaction with the SCCtype circuit through an SCCtype interface. The control circuit of present SCC arranges normally open power domain in, and the consumption that leads to causing is lost great, consequently this application arranges SCC control circuit wholly in the power domain that the chip can fall the electricity, can control to open only when carrying out the ATE test, and the function logic of this logic and circuit normal during operation does not influence each other, can follow the system and close together, has reduced the circuit consumption when actual work to the realization is to the influence minimizing of the whole consumption of system.
The method for detecting the chip difference is applied to a detection system of the chip difference, wherein the detection system of the chip difference comprises a plurality of silicon chip classification and calibration Type SCC Type circuits and an SCC control circuit, each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of transistors of different types; the plurality of SCC Type circuits input the output SO signals into the SCC control circuit; the method comprises the steps that an SCC control circuit calculates circuit delay values of a plurality of SCC Type circuits to obtain a plurality of circuit delay values; the SCC control circuit determines whether there is a difference in electrical characteristics of the chips based on the plurality of SO signals and the plurality of circuit delay values. The application provides and uses different kinds of transistors to mix and take and constitute basic SCCtype, can show the area that reduces ROSC and take up on the less car rule level chip of overall dimension, reflects the electrical characteristics difference of chip through the SO signal with SCC Type circuit output simultaneously, has guaranteed the coverage of test, satisfies the requirement of the higher car rule level standard of stability requirement to the chip yield.
The above description has introduced the solution of the embodiment of the present application mainly from the perspective of the method-side implementation process. It is understood that the network device comprises corresponding hardware structures and/or software modules for performing the respective functions in order to realize the above functions. Those of skill in the art will readily appreciate that the present application is capable of hardware or a combination of hardware and computer software implementing the various illustrative elements and algorithm steps described in connection with the embodiments provided herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a detection apparatus provided in an embodiment of the present application, where the detection apparatus includes: one or more processors, one or more memories, one or more communication interfaces, and one or more programs; the one or more programs are stored in the memory and configured to be executed by the one or more processors.
The program includes instructions for performing the steps of: inputting the output SO signal into the SCC control circuit; calculating circuit delay values of the SCC Type circuits to obtain a plurality of circuit delay values; and determining whether the chip has the electrical characteristic difference according to the SO signals and the circuit delay values.
All relevant contents of each scene related to the method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.
It will be appreciated that the memory described above may include both read-only memory and random access memory, and provides instructions and data to the processor. The portion of memory may also include non-volatile random access memory. For example, the memory may also store device type information.
In the embodiment of the present application, the processor of the above apparatus may be a Central Processing Unit (CPU), and the processor may also be other general processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
It is to be understood that reference to "at least one" in the embodiments of the present application means one or more, and "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software elements in a processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in a memory, and a processor executes instructions in the memory, in combination with hardware thereof, to perform the steps of the above-described method. To avoid repetition, it is not described in detail here.
Embodiments of the present application also provide a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any one of the methods as described in the above method embodiments.
Embodiments of the present application further provide a computer program product including instructions, which, when run on an electronic device, cause the electronic device to perform some or all of the steps of any of the methods described in the above method embodiments.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present application.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit may be stored in a computer readable memory if it is implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present application may be substantially or partially contributed by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a TRP, etc.) to execute all or part of the steps of the method of the embodiments of the present application. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash disk, ROM, RAM, magnetic or optical disk, and the like.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. The method for detecting the chip difference is characterized by being applied to a chip difference detection system, wherein the chip difference detection system comprises a plurality of silicon chip classification and calibration Type SCC Type circuits and an SCC control circuit, each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of different types of transistors;
the method comprises the following steps:
the plurality of SCC Type circuits input the output SO signals into the SCC control circuit;
the SCC control circuit calculates circuit delay values of the plurality of SCC Type circuits to obtain a plurality of circuit delay values;
the SCC control circuit determines whether there is a difference in electrical characteristics of the chips based on the SO signals and the circuit delay values.
2. The method of claim 1, wherein the SCC control circuitry calculates circuit delay values for the plurality of SCC Type circuits, resulting in a plurality of circuit delay values, comprising:
the SCC control circuit acquires sampling clock cycles of the plurality of SCC Type circuits to obtain a plurality of sampling clock cycles;
the SCC control circuit inputs the sampling clock periods into a first formula respectively for calculation, to obtain the circuit delay values, where the first formula is expressed as: g ═ N × S)/T, where N is a preset number of sampling cycles, S is the sampling clock cycle, and T is a constant.
3. The method of claim 2, wherein the SCC control circuitry determines whether there is a difference in electrical characteristics of the chip based on the plurality of SO signals and the plurality of circuit delay values, comprising:
the SCC control circuit calculates an absolute value of a difference between an ith SO signal and a corresponding circuit delay value to obtain a first difference value;
if the first difference is greater than a preset value, the SCC control circuit determines that a first SCC Type circuit has an electrical characteristic difference, where the first SCC Type circuit is an SCC Type circuit corresponding to the ith SO signal;
if the first difference is less than or equal to the preset value, the SCC control circuit determines that the first SCC Type circuit has no electrical characteristic difference.
4. The method of any of claims 1-3, wherein the SCC control circuitry is located in a power domain that is powered down.
5. The method of claim 1, wherein the SCC Type circuitry further comprises a ripple counter;
the method further comprises the following steps: and the wave connection counter converts the square waves output by the ROSC chains into the serial SO signals.
6. The system for detecting the chip difference is characterized by comprising a plurality of silicon chip classification and calibration Type SCC Type circuits and an SCC control circuit, wherein each SCC Type circuit comprises a plurality of ring oscillator ROSC chains, and each ROSC chain is composed of different types of transistors; wherein the content of the first and second substances,
the plurality of SCC Type circuits are used for inputting the output SO signals into the SCC control circuit;
the SCC control circuit is configured to calculate circuit delay values of the plurality of SCC Type circuits to obtain a plurality of circuit delay values;
the SCC control circuit is further configured to determine whether there is a difference in electrical characteristics between the chips according to the SO signals and the circuit delay values.
7. The system of claim 6, wherein in calculating the circuit delay values of the plurality of SCC Type circuits to obtain a plurality of circuit delay values, the SCC control circuitry is specifically configured to:
acquiring sampling clock cycles of the plurality of SCC Type circuits to obtain a plurality of sampling clock cycles;
respectively inputting the multiple sampling clock periods into a first formula for calculation to obtain the multiple circuit delay values, wherein the first formula is represented as: g ═ N × S)/T, where N is a preset number of sampling cycles, S is the sampling clock cycle, and T is a constant.
8. The system of claim 6 or 7, wherein the SCC control circuit is provided in a power domain in which power can be lost.
9. A detection device, characterized in that the detection device comprises a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method according to any one of claims 1-5.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program causes a computer to perform the steps of the method according to any one of claims 1-5.
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