CN111371453A - Signal period measuring circuit and method - Google Patents
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- CN111371453A CN111371453A CN201910730102.1A CN201910730102A CN111371453A CN 111371453 A CN111371453 A CN 111371453A CN 201910730102 A CN201910730102 A CN 201910730102A CN 111371453 A CN111371453 A CN 111371453A
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- 238000005070 sampling Methods 0.000 claims abstract description 93
- 230000000737 periodic effect Effects 0.000 claims abstract description 65
- 238000005259 measurement Methods 0.000 claims description 7
- 230000001934 delay Effects 0.000 claims 1
- 101100328957 Caenorhabditis elegans clk-1 gene Proteins 0.000 description 6
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Abstract
The application provides a signal period measuring circuit and a method, wherein the signal period measuring circuit comprises a frequency calculating module, a waveform generating module, a signal sampling module and a period recording module. The frequency calculation module generates a frequency count value in each period of the first frequency. The waveform generation module is used for generating M periodic waveforms from each period of the first frequency, and the M periodic waveforms correspond to M phases of the first frequency. The signal sampling module is electrically connected with the waveform generating module and is used for sampling the input signal according to the M periodic waveforms to generate phase sampling values. The period recording module is electrically connected with the frequency calculating module and the signal sampling module and used for recording the current frequency counting value and the corresponding phase sampling value. Wherein M is a natural number greater than 1.
Description
Technical Field
The present invention relates to a circuit and a method for measuring signal period, and more particularly, to a circuit and a method for dividing a frequency into different phases and measuring signal period respectively.
Background
When a conventional test apparatus measures a periodic input signal, the input signal can only be captured by a positive edge of a system frequency (system clock), so that the period of the input signal can be estimated by marking a time point at which the input signal is captured. However, if the system frequency is not high, there is often a problem of insufficient resolution, and the period of the input signal cannot be estimated correctly. For example, referring to fig. 1, fig. 1 is a schematic diagram illustrating a conventional input signal and a system frequency. As shown in fig. 1, after the system clock clk catches the high-level input signal S _ in the 1 st cycle, the system clock clk catches the high-level input signal S _ in again in the 10 th cycle, and the length of the input signal can be estimated to be 9 system clock cycles. If the period of one system frequency is 5ns, the length of the input signal is 45 ns.
However, as can be seen from fig. 1, in practice the length of the input signal is closer to 8 system frequency cycles, and the error can reach one system frequency. If the period of the input signal is shorter, it is clear that the measured period error is relatively larger. Therefore, there is a need for a circuit and method for measuring signal period with higher resolution.
Disclosure of Invention
In view of the above, the present application provides a signal period measuring circuit, which can divide the frequency into a plurality of periodic waveforms with different phases and measure the period of the input signal according to the plurality of periodic waveforms, thereby achieving higher resolution.
The application provides a signal period measuring circuit, which comprises a frequency calculating module, a waveform generating module, a signal sampling module and a period recording module. The frequency calculation module generates a frequency count value in each period of the first frequency. The waveform generation module is used for generating M periodic waveforms from each period of the first frequency, and the M periodic waveforms correspond to M phases of the first frequency. The signal sampling module is electrically connected with the waveform generating module and is used for sampling the input signal according to the M periodic waveforms to generate phase sampling values. The period recording module is electrically connected with the frequency calculating module and the signal sampling module and used for recording the current frequency counting value and the corresponding phase sampling value. Wherein M is a natural number greater than 1.
In some embodiments, the waveform generation module may sequentially delay the first frequency to generate the M periodic waveforms, wherein a positive edge of an i-th periodic waveform and a positive edge of an i + 1-th periodic waveform have a time interval, i is a natural number and i is less than M. In addition, the phase sampling values can respectively sample the sampling results of the input signal corresponding to the M periodic waveforms. In addition, the phase sampling value may have M bits, the M bits sequentially correspond to M phases of the first frequency, a jth bit of the phase sampling value may correspond to a sampling result of the jth periodic waveform sampling input signal, j is a natural number and j is not greater than M.
In some embodiments, the signal sampling module may further determine whether the phase sampling value changes in different periods of the first frequency, and when the signal sampling module determines that the phase sampling value changes, the period recording module records the current frequency count value and the corresponding phase sampling value. In addition, the period recording module comprises a memory, and the memory is used for storing the current frequency counting value and the corresponding phase sampling value. When the signal sampling module judges that the phase sampling value is not changed, the period recording module does not record the current frequency counting value and the corresponding phase sampling value.
The application provides a signal period measuring method, which can divide the frequency into a plurality of periodic waveforms with different phases and measure the period of an input signal according to the periodic waveforms, thereby having higher resolution.
The application provides a signal period measuring method, which comprises the following steps. A frequency count value is generated at each cycle of the first frequency. M periodic waveforms are generated from each period of the first frequency, the M periodic waveforms corresponding to M phases of the first frequency. Sampling the input signal according to the M periodic waveforms to generate phase sampling values. The current frequency count value and the corresponding phase sample value are recorded. Wherein M is a natural number greater than 1.
To sum up, the signal period measuring circuit and method provided by the application can divide the frequency into a plurality of periodic waveforms with different phases, and sample the input signal by utilizing each periodic waveform, so that the sampling times are more, the sampling interval can be shortened more, and the period of the input signal can be judged more accurately and with higher resolution.
Further details regarding other functions and embodiments of the present application are described below with reference to the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram illustrating a prior art sampling of an input signal;
FIG. 2 is a functional block diagram of a signal period measurement circuit according to an embodiment of the present application;
FIG. 3 is a schematic diagram of sampling an input signal according to an embodiment of the present application;
fig. 4 is a flowchart illustrating steps of a signal period measurement method according to an embodiment of the present application.
Description of the symbols
1 signal period measuring circuit 10 frequency calculating module
12 waveform generation module 14 signal sampling module
16-period recording module S20-S26 step flow
CLK system frequency CLK first frequency
CLK _ 1-CLK _4 periodic waveform S _ in input signal
CLK _ count frequency count value Phase _ count Phase sample value
Detailed Description
The foregoing and other technical matters, features and effects of the present application will be apparent from the following detailed description of a preferred embodiment, which is to be read in connection with the accompanying drawings. Directional terms as referred to in the following examples, for example: up, down, left, right, front or rear, etc., are simply directions with reference to the drawings. Accordingly, the directional terminology used is intended to be in the nature of words of description rather than of limitation.
Referring to fig. 2, fig. 2 is a functional block diagram of a signal period measuring circuit according to an embodiment of the present application. As shown in fig. 2, the present embodiment discloses that the signal period measuring circuit 1 is used for measuring the period of the input signal S _ in, and the signal period measuring circuit 1 includes a frequency calculating module 10, a waveform generating module 12, a signal sampling module 14 and a period recording module 16. In practice, the signal period measuring circuit 1 may be used to mark a signal start time point and a signal end time point of the input signal S _ in, record the signal start time point and the signal end time point, and convert the signal start time point and the signal end time point into a period by another testing device. In other words, the signal period measuring circuit 1 may be incorporated in another test apparatus or externally connected to another test apparatus. Of course, the present embodiment is not limited thereto, and for example, the signal period measuring circuit 1 may convert the period of the input signal S _ in by itself. The overall function of the signal period measuring circuit 1 will be described below with reference to each block.
The frequency calculating module 10 generates a frequency count value at each period of the first clock CLK. In one example, the first frequency CLK may be a system clock (system clock), a baseband frequency, or any other designated frequency, which is not limited in this embodiment. In addition, the frequency calculation module 10 may count the first frequency CLK triggered by a positive edge of the first frequency CLK after receiving the first frequency CLK. It should be understood by those skilled in the art that either positive edge triggered or negative edge triggered could achieve the same effect, and for convenience of description, the following embodiments are described with positive edge triggered. For convenience of description, please refer to fig. 2 and fig. 3 together, and fig. 3 is a schematic diagram illustrating sampling of an input signal according to an embodiment of the present application. As shown, the frequency count value generated by the frequency calculation module 10 may be denoted as CLK _ count, and the initial value may be any natural number N.
In an example, the frequency calculating module 10 may accumulate the first frequency CLK in the frequency count value CLK _ count, and the accumulated value may be 1 or other fixed value, which is not limited herein. In other words, in the example shown in fig. 3, the clock calculation module 10 may initially transmit the clock count value CLK _ count of N to the cycle recording module 16 (e.g., the 1 st cycle), and may transmit the clock count value CLK _ count of N +1 to the cycle recording module 16 at the next cycle (e.g., the 2 nd cycle) of the first clock CLK, and so on.
The waveform generating module 12 is configured to generate M periodic waveforms from each period of the first frequency CLK, where the M periodic waveforms correspond to M phases of the first frequency. In the example shown in fig. 3, the waveform generating module 12 can generate 4 periodic waveforms CLK _1, CLK _2, CLK _3, and CLK _4 according to the first clock CLK, wherein the phase of each periodic waveform is different by 90 degrees. In one example, the waveform generating module 12 may include a phase-locked loop (PLL) for delaying the first clock CLK to generate a plurality of periodic waveforms with different phases. Although the waveform generation module 12 generates 4 periodic waveforms in this embodiment, the invention is not limited thereto, and the waveform generation module 12 may generate 8 or 16 periodic waveforms.
The signal sampling module 14 is electrically connected to the waveform generating module 12, and is configured to sample the input signal S _ in according to the M periodic waveforms to generate phase sampling values. In one example, the signal sampling module 14 may sample the input signal S _ in using the positive edge of the periodic waveform. For the example shown in FIG. 3, the signal sampling module 14 can determine that the periodic waveform CLK _1 is not sampled to the input signal S _ in during the 1 st period of the first clock CLK (the clock count value CLK _ count is between N and N + 1), because the input signal S _ in is still low during the positive edge of the periodic waveform CLK _ 1. The signal sampling module 14 can determine that the input signal S _ in is sampled by the periodic waveforms CLK _2, CLK _3, CLK _4 because the input signal S _ in is high when the periodic waveforms CLK _2, CLK _3, CLK _4 are positive. Accordingly, the signal sampling module 14 may record the phase sample value phase _ count as 0111, indicating that the input signal S _ in starts from the 2 nd phase. Here, the present embodiment demonstrates that the number of bits of the phase sample value phase _ count can correspond to the number of periodic waveforms, and it can be known to which phase (which periodic waveform) the signal start time point of the input signal S _ in corresponds to through the order of bits.
Similarly, during the 10 th cycle of the first clock signal CLK (the clock count CLK _ count is between N +9 and N + 10), the signal sampling module 14 can determine that the periodic waveforms CLK _1, CLK _2, CLK _3 are not sampled to the input signal S _ in because the input signal S _ in is still low when the periodic waveforms CLK _1, CLK _2, CLK _3 are positive. The signal sampling module 14 can determine that the periodic waveform CLK _4 has been sampled to the input signal S _ in because the input signal S _ in is high at the positive edge of the periodic waveform CLK _ 4. Accordingly, the signal sampling module 14 may record the phase sampling value phase _ count as 0001, which indicates that the input signal S _ in of the next period starts from the 4 th phase. Since the input signal S _ in is a continuous signal, by measuring the signal start time point of the input signal S _ in of the next cycle, i.e., the signal end time point equal to the input signal S _ in of the previous cycle is measured. In one example, the signal sampling module 14 may generate the phase sample value phase _ count after the input signal S _ in is completely sampled by the 4 periodic waveforms CLK _1, CLK _2, CLK _3, and CLK _4, and output the phase sample value phase _ count to the period recording module 16 in the next period of the first clock CLK.
In one example, the signal sampling module 14 can determine which phase samples have physical significance. For example, if the previous phase sample value phase _ count is recorded as 0000, the current phase sample value phase _ count is still recorded as 0000, which indicates that the input signal S _ in is always at the low level, and thus the signal sampling module 14 records such a phase sample value without help to the measurement period. Similarly, if the previous phase sample value phase _ count is recorded as 1111, the current phase sample value phase _ count is also recorded as 1111, which indicates that the input signal S _ in is at the high level, so that the signal sampling module 14 does not help the measurement period to record such phase sample value. However, if the previous phase sample value phase _ count is recorded as 0000, the current phase sample value phase _ count is also recorded as 0111, and the signal sampling module 14 finds a change in the phase sample value phase _ count, the signal sampling module 14 may determine that the current phase sample value phase _ count is significant, and further output the phase sample value phase _ count to the period recording module 16. On the contrary, if the signal sampling module 14 determines that the current phase sampling value phase _ count is meaningless, the phase sampling value phase _ count may not be output to the period recording module 16.
The period recording module 16 is electrically connected to the frequency calculating module 10 and the signal sampling module 14, and is configured to record a current frequency count value CLK _ count and a corresponding phase sampling value phase _ count. For the example shown in fig. 3, although the positive edge of the input signal S _ in is within the 1 st period of the first clock CLK, it can be understood by those skilled in the art that the circuit elements cannot sample and send out the sampling result batch immediately in the same period, so that the period recording module 16 may not receive the data from the signal sampling module 14 until the next period (2 nd period) of the first clock CLK. Accordingly, the period recording module 16 records the signal start time point of the input signal S _ in, the corresponding frequency count value CLK _ count is N +1 and the phase sample value phase _ count is 0111.
Similarly, although the next positive edge of the input signal S _ in is within the 10 th cycle of the first clock CLK, the period recording module 16 will wait until the next cycle (11 th cycle) of the first clock CLK to receive the data from the signal sampling module 14. Accordingly, the period recording module 16 records the signal ending time point of the input signal S _ in, and the corresponding frequency count value CLK _ count is N +10 and the phase sample value phase _ count is 0001. In other words, one cycle of the input signal S _ in is different by 9 cycles in the frequency count value CLK _ count, and the phase sample value phase _ count is different by 2 phases. It is assumed that when 1 cycle of the first frequency CLK corresponds to 4ns, each of the 4 phases is exactly spaced by 1 ns. For the example shown in fig. 3, 9 cycles of the first clock CLK can be converted to 36ns, and 2 phases of the first clock CLK can be converted to 2ns, so that the cycle of the input signal S _ in can be quickly estimated to be 38ns by the clock count value CLK _ count and the phase sample value phase _ count.
Here, one of ordinary skill in the art can find that when the period recording module 16 obtains the phase sample value phase _ count does not affect the estimation of the period of the input signal S _ in. For example, even if the period recording module 16 waits until the next 5 periods of the first clock signal CLK receive data from the signal sampling module 14, the signal start time point of the input signal S _ in is changed to correspond to the clock count value CLK _ count of N +5 and the phase sampling value phase _ count of 0111. Similarly, the signal ending time point of the input signal S _ in is changed to correspond to the frequency count value CLK _ count being N +14 and the phase sample value phase _ count being 0001. Since the delay error is subtracted, it can still be calculated that one cycle of the input signal S _ in is different by 9 cycles in the frequency count value CLK _ count and the phase sample value phase _ count is different by 2 phases. Accordingly, it can be deduced that the period of the input signal S _ in is 38ns, and the period measurement result of the input signal S _ in is not affected.
It should be noted that the signal sampling module 14 samples the positive edge of the input signal S _ in twice, so as to obtain the start and end time points of a complete cycle of the input signal S _ in. However, the present embodiment is not limited thereto, for example, the signal sampling module 14 may also sample the positive edge and the next negative edge of the input signal S _ in, so as to obtain the starting and ending time points of one half cycle of the input signal S _ in. In this way, the time length of a complete cycle can still be deduced via a half cycle.
In the foregoing example, the period recording module 16 may further calculate the period of the input signal S _ in addition to recording the frequency count value CLK _ count and the phase sample value phase _ count. Of course, in another example, the period recording module 16 may be used to mark only the signal start time point and the signal end time point of the input signal S _ in, store the frequency count value CLK _ count and the phase sample value phase _ count in a memory, and exchange the frequency count value CLK _ count and the phase sample value phase _ count with other testing devices to calculate the period. For example, the signal period measuring circuit 1 may be a Field Programmable Gate Array (FPGA), and the memory of the period recording module 16 may be a block random access memory (block RAM) in the FPGA.
For explaining the signal period measuring method of the present disclosure, please refer to fig. 2, fig. 3 and fig. 4 together, and fig. 4 is a flowchart illustrating steps of the signal period measuring method according to an embodiment of the present disclosure. As shown in step S20, the clock calculation module 10 generates a clock count value CLK _ count for each cycle of the first clock CLK. In step S22, the waveform generating module 12 is configured to generate M periodic waveforms from each period of the first clock CLK, where the M periodic waveforms correspond to M phases of the first clock. In step S24, the signal sampling module 14 is electrically connected to the waveform generating module 12 for sampling the input signal S _ in according to the M periodic waveforms to generate a phase sampling value phase _ count. In step S26, the period recording module 16 is electrically connected to the frequency calculating module 10 and the signal sampling module 14 for recording the current frequency count value CLK _ count and the corresponding phase sampling value phase _ count. Since the signal period measurement method of the present embodiment has been fully described and supported in the foregoing embodiments, it is not repeated herein.
To sum up, the signal period measuring circuit and method provided by the application can divide the frequency into a plurality of periodic waveforms with different phases, and sample the input signal by utilizing each periodic waveform, so that the sampling times are more, the sampling interval can be shortened more, and the period of the input signal can be judged more accurately and with higher resolution.
The above-described embodiments and/or implementations are only illustrative of the preferred embodiments and/or implementations for implementing the technology of the present application, and are not intended to limit the implementations of the technology of the present application in any way, and those skilled in the art can make many changes or modifications to the equivalent embodiments without departing from the scope of the technology disclosed in the present application, but should still be considered as the technology or implementations substantially the same as the present application.
Claims (15)
1. A signal period measurement circuit, comprising:
a frequency calculating module, generating a frequency counting value in each period of a first frequency;
a waveform generating module for generating M periodic waveforms from each of the periods of the first frequency, the M periodic waveforms corresponding to M phases of the first frequency;
a signal sampling module, electrically connected to the waveform generating module, for sampling an input signal according to the M periodic waveforms to generate a phase sampling value; and
a period recording module electrically connected to the frequency calculating module and the signal sampling module for recording the current frequency count value and the corresponding phase sampling value;
wherein M is a natural number greater than 1.
2. The signal period measuring circuit of claim 1, wherein the waveform generating module sequentially delays the first frequency to generate the M periodic waveforms, wherein a positive edge of an i-th periodic waveform and a positive edge of an i + 1-th periodic waveform have a time interval, i is a natural number and i is less than M.
3. The signal period measuring circuit of claim 1, wherein the phase sample value samples the sampling result of the input signal for each of the M periodic waveforms.
4. The signal period measurement circuit of claim 3 in which the phase samples have M bits that sequentially correspond to the M phases of the first frequency.
5. The signal period measurement circuit of claim 4 wherein the jth bit of the phase sample corresponds to a sampling of the input signal for a jth periodic waveform, j being a natural number and j being no greater than M.
6. The signal period measuring circuit of claim 1, wherein the signal sampling module further determines whether the phase sampling value changes in different periods of the first frequency, and the period recording module records the current frequency count value and the corresponding phase sampling value when the signal sampling module determines that the phase sampling value changes.
7. The signal period measuring circuit of claim 6, wherein the period recording module comprises a memory for storing the current frequency count value and the corresponding phase sample value.
8. The signal period measuring circuit of claim 6, wherein the period recording module does not record the current frequency count value and the corresponding phase sample value when the signal sampling module determines that the phase sample value is unchanged.
9. A method for measuring signal period, comprising:
generating a frequency count value in each period of a first frequency;
generating M periodic waveforms from each of the periods of the first frequency, the M periodic waveforms corresponding to M phases of the first frequency;
sampling an input signal according to the M periodic waveforms to generate a phase sampling value; and
recording the current frequency count value and the corresponding phase sampling value;
wherein M is a natural number greater than 1.
10. The method of claim 9, wherein the step of generating M periodic waveforms from each of the cycles of the first frequency further comprises:
sequentially delaying the first frequency to generate the M periodic waveforms;
wherein, the positive edge of the ith periodic waveform and the positive edge of the (i + 1) th periodic waveform have a time interval, i is a natural number and i is less than M.
11. The method of claim 9, wherein the phase sampling value samples the sampling result of the input signal for each of the M periodic waveforms.
12. The method of claim 11, wherein the phase samples have M bits, the M bits sequentially corresponding to the M phases at the first frequency.
13. The method of claim 12, wherein a jth bit of the phase samples corresponds to a sampling of the input signal by a jth periodic waveform, j being a natural number and j being no greater than M.
14. The method of claim 9, wherein the step of sampling the input signal according to the M periodic waveforms to generate the phase samples further comprises:
determining whether the phase samples change in different periods of the first frequency;
when the phase sampling value is judged to be changed, the current frequency counting value and the corresponding phase sampling value are recorded.
15. The method of claim 14, wherein when it is determined that the phase samples are unchanged, the current frequency count value and the corresponding phase samples are not recorded.
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| Application Number | Priority Date | Filing Date | Title |
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| TW107147109A TWI668453B (en) | 2018-12-26 | 2018-12-26 | Circuit and method for measuring signal period |
| TW107147109 | 2018-12-26 |
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| CN113823245A (en) * | 2021-09-08 | 2021-12-21 | 富奥汽车零部件股份有限公司 | Display screen brightness control method, control device and readable storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06347569A (en) * | 1993-06-07 | 1994-12-22 | Hokuto Denko Kk | Frequency multiplier circuit and pulse time interval measuring device |
| JP2003317260A (en) * | 2002-04-23 | 2003-11-07 | Matsushita Electric Ind Co Ltd | Optical disk drive |
| CN101599276A (en) * | 2009-06-30 | 2009-12-09 | 中国科学院上海光学精密机械研究所 | CD jitter characteristics proving installation and method of testing thereof |
| US20110301895A1 (en) * | 2009-02-27 | 2011-12-08 | Kazunori Miyahara | Phase measuring device and frequency measuring device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW445722B (en) * | 2000-04-07 | 2001-07-11 | Via Tech Inc | Glitch-free phase converting method of timing signal and circuit of the same |
| US6771103B2 (en) * | 2001-03-14 | 2004-08-03 | Denso Corporation | Time measurement apparatus, distance measurement apparatus, and clock signal generating apparatus usable therein |
| US9541591B2 (en) * | 2014-08-11 | 2017-01-10 | Synopsys, Inc. | Periodic signal measurement using statistical sampling |
-
2018
- 2018-12-26 TW TW107147109A patent/TWI668453B/en not_active IP Right Cessation
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06347569A (en) * | 1993-06-07 | 1994-12-22 | Hokuto Denko Kk | Frequency multiplier circuit and pulse time interval measuring device |
| JP2003317260A (en) * | 2002-04-23 | 2003-11-07 | Matsushita Electric Ind Co Ltd | Optical disk drive |
| US20110301895A1 (en) * | 2009-02-27 | 2011-12-08 | Kazunori Miyahara | Phase measuring device and frequency measuring device |
| CN101599276A (en) * | 2009-06-30 | 2009-12-09 | 中国科学院上海光学精密机械研究所 | CD jitter characteristics proving installation and method of testing thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113823245A (en) * | 2021-09-08 | 2021-12-21 | 富奥汽车零部件股份有限公司 | Display screen brightness control method, control device and readable storage medium |
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| TWI668453B (en) | 2019-08-11 |
| TW202024649A (en) | 2020-07-01 |
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