CN116155243A

CN116155243A - Ultra-narrow pulse stretching circuit, method and electronic equipment

Info

Publication number: CN116155243A
Application number: CN202310035774.7A
Authority: CN
Inventors: 王宾
Original assignee: Hangzhou Aochuang Photonics Technology Co ltd
Current assignee: Hangzhou Aochuang Photonics Technology Co ltd
Priority date: 2023-01-10
Filing date: 2023-01-10
Publication date: 2023-05-23

Abstract

The application provides an ultra-narrow pulse stretching circuit, a method and electronic equipment, wherein the circuit comprises: the calibration module is used for performing inverse transformation and delay processing on the control signal to obtain a calibration signal; the OR gate is used for carrying out logical OR operation on the detected signal and the calibration signal to obtain a clock signal; a D trigger for outputting a spread signal according to the control signal and the clock signal; the input end of the D trigger is connected with a control signal, and the clock end of the D trigger is connected with the output end of the OR gate; the first input end of the OR gate is connected with the output end of the calibration module, and the second input end is connected with a tested signal; and the input end of the calibration module is connected with a control signal. By adopting the method and the device, the broadening of the ultra-narrow pulse of the detected signal, especially the broadening of a plurality of ultra-narrow sub-pulses with uncertain quantity, can be realized, and the pulse after broadening can be stably sampled.

Description

Ultra-narrow pulse stretching circuit, method and electronic equipment

Technical Field

The present disclosure relates to the field of signal processing, and in particular, to an extremely narrow pulse stretching circuit, an extremely narrow pulse stretching method, and an electronic device.

Background

In some existing high-precision ultrafast pulse laser products, a limited electric control system controls a driving circuit to output an extremely narrow pulse signal through an electric control signal, and the extremely narrow pulse signal needs to be subjected to pulse sampling based on the requirement of a control system. However, existing off-the-shelf chips such as logic gate chips have difficulty or even fail to sample the identification of such extremely narrow pulse signals. Also, multi-envelope pulse signals make stable pulse sampling increasingly difficult due to the extremely narrow nature of the pulse widths that make up the envelope pulses. In addition, in some specific process debugging scenes, the pulse width of the single pulse needs to be adjusted according to the requirements of actual scenes, so that the number of sub-pulses in the pulse signal is increased or reduced, and the difficulty in sampling the pulse envelope frequency is further increased due to the variation of the number of the sub-pulses. In this demanding scenario, there is a very narrow pulse envelope of multiple sub-pulses in addition to the single very narrow sub-pulse, the very narrow sub-pulse envelope or the frequency of the very narrow sub-pulse needs to be sampled, and the stability of the sampling needs to be ensured. Limited by the sampling conditions, in the case of occasional fluctuations in the peak power of the light pulses, unstable and distorted sampling results may occur.

In order to solve the technical problems listed above, in the application of some existing ultrafast pulse laser products, one method is to design an analog stretching circuit, realize pulse width stretching by using the charge-discharge characteristics of a stretching capacitor, and then make the stretched pulse adapt to the pulse with the frequency that can be sampled by an intelligent chip to keep the minimum time. However, for some scenes in which the number of the sub-pulses can be adjusted online, because the energy of a plurality of sub-pulses is more than that of a single sub-pulse, the widening capacitance parameter of one sub-pulse is adapted, and the application scene of a plurality of sub-pulses is not adapted, if the corresponding widening capacitance parameter is not changed, sampling failure and metastable state can be caused, and the stability of a product is affected. Another method is to sample the pulse by using a higher-cost and higher-performance sequential logic chip, but in view of the fact that the pulse width of the signal is extremely narrow and the energy is extremely weak, and the number of sub-pulses is not fixed, the sampling result also lacks better stability and is high in cost.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, it is an object of the present application to provide an extremely narrow pulse stretching circuit, method and electronic device for realizing stretching of extremely narrow pulses, especially having a plurality of extremely narrow sub-pulses of indefinite number, facilitating more stable sampling of the stretched pulses.

To achieve the above and other related objects, a first aspect of the present application provides an extremely narrow pulse stretching circuit comprising: the calibration module is used for performing inverse transformation and delay processing on the control signal to obtain a calibration signal; the OR gate is used for carrying out logical OR operation on the measured signal and the calibration signal to obtain a clock signal; a D trigger for outputting a spread signal according to the control signal and the clock signal; the input end of the D trigger is connected with a control signal, and the clock end of the D trigger is connected with the output end of the OR gate; the first input end of the OR gate is connected with the output end of the calibration module, and the second input end is connected with a tested signal; and the input end of the calibration module is connected with a control signal.

In some embodiments of the first aspect of the present application, the calibration module includes: the inverter is used for carrying out inverse transformation on the control signal to obtain an inverse control signal; the phase difference delay unit is used for carrying out dislocation delay on the reverse phase control signal to obtain a calibration signal; the output end of the phase difference delay unit is connected with the input end of the phase difference delay unit.

In some embodiments of the first aspect of the present application, the control signal is generated by a control system and is a square wave signal with a duty cycle of 50%, and the frequency of the control signal is synchronous with the measured signal.

In some embodiments of the first aspect of the present application, the frequency of the control signal is between 100KHz and 1MHz.

In some embodiments of the first aspect of the present application, the calibration signal and the control signal differ by 10ns.

In some embodiments of the first aspect of the present application, the measured signal includes one or more sub-pulses having a pulse width of 200ps to 5 ns.

To achieve the above and other related objects, a second aspect of the present application provides an extremely narrow pulse stretching method, including: the control signal is subjected to inverse transformation and delay treatment to obtain a calibration signal; after the calibration signal and the measured signal are subjected to logical OR operation, a clock signal is obtained; and inputting the control signal into an input signal end of the D trigger, inputting the clock signal into a clock signal end of the D trigger, and outputting a widening signal by an output signal end of the D trigger according to the level state of the clock signal.

In some embodiments of the second aspect of the present application, the measured signal includes one or more sub-pulses having a pulse width of 200ps to 5 ns.

In some embodiments of the second aspect of the present application, the control signal is generated by a control system and is a square wave signal with a duty cycle of 50%, and the frequency of the control signal is 100 KHz-1 MHz and is synchronous with the measured signal.

To achieve the above and other related objects, a third aspect of the present application provides an electronic device comprising an extremely narrow pulse stretching circuit as described in any one of the previous embodiments.

As described above, the ultra-narrow pulse stretching circuit, the ultra-narrow pulse stretching method and the electronic equipment have the following beneficial effects:

the method and the device can output a mapping waveform of the detected signal after the detected extremely-narrow pulse signal is processed, the waveform is larger in duty ratio than the original signal, and the intelligent detection and frequency counting can be performed for a subsequent measuring circuit, so that the effect of stable sampling is achieved. In addition, the method can be realized by reasonably careful code programming optimization, so that the method is realized by FPGA hardware logic language programming, and also can be realized by a pure hardware combination logic circuit, stable frequency measurement can still be realized under the condition that a plurality of extremely narrow sub-pulses appear in a measured signal, and the tiny optical power jitter is insufficient to influence at a frequency measurement input end, so that the method has better reliability, and the method is sufficient to be applied to industrial laser products.

Drawings

FIG. 1 is a schematic diagram of an extremely narrow pulse stretching circuit in accordance with one embodiment of the present application.

Fig. 2 is a schematic diagram of circuit operation logic in a single sub-pulse scenario according to an embodiment of the present application.

FIG. 3 is a schematic diagram showing the logic of the circuit operation in a multiple sub-pulse scenario according to one embodiment of the present application.

Fig. 4 is a flow chart illustrating a method of stretching very narrow pulses according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of an electronic device including the circuit according to an embodiment of the present application.

Detailed Description

Other advantages and effects of the present application will become apparent to those skilled in the art from the present disclosure, when the following description of the embodiments is taken in conjunction with the accompanying drawings. The present application may be embodied or carried out in other specific embodiments, and the details of the present application may be modified or changed from various points of view and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

It is noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present application. It is to be understood that other embodiments may be utilized and that mechanical, structural, electrical, and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description is not to be taken in a limiting sense, and the scope of embodiments of the present application is defined only by the claims of the issued patent. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Spatially relative terms, such as "upper," "lower," "left," "right," "lower," "upper," and the like, may be used herein to facilitate a description of one element or feature as illustrated in the figures as being related to another element or feature.

In this application, unless specifically stated and limited otherwise, the terms "mounted," "connected," "secured," "held," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, operations, elements, components, items, categories, and/or groups. The terms "or" and/or "as used herein are to be construed as inclusive, or meaning any one or any combination. Thus, "A, B or C" or "A, B and/or C" means "any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; A. b and C). An exception to this definition will occur only when a combination of elements, functions or operations are in some way inherently mutually exclusive.

In order to solve the problems in the background art, the invention provides an ultra-narrow pulse stretching circuit, an ultra-narrow pulse stretching method and electronic equipment, and aims to realize stretching of ultra-narrow pulses, particularly a plurality of ultra-narrow sub-pulses with uncertain quantity, so that the stretched pulses can be sampled more stably. Meanwhile, in order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be further described in detail by the following examples with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Before explaining the present invention in further detail, terms and terminology involved in the embodiments of the present invention will be explained, and the terms and terminology involved in the embodiments of the present invention are applicable to the following explanation:

<1> inverter (phase inverter): the inverter can invert the phase of the input signal by 180 degrees, and such a circuit is applied to an analog circuit, such as an audio amplifier, a clock oscillator, and the like. In electronic circuit design, inverters are often used. The CMOS inverter circuit is composed of two enhancement type MOS field effect transistors. A typical TTL NAND gate consists of an input stage, an intermediate stage and an output stage.

<2> OR gate: OR gate is also known as OR circuit, logic, and circuit. If one of several conditions is met, an event occurs, which is called an or logical relationship. A circuit having an or logic relationship is called an or gate. The OR gate has a plurality of input terminals and an output terminal, and the output is high level (logic '1') whenever one of the input terminals is high level (logic '1'); the output is low (logic "0") only if all inputs are low (logic "0").

<3>D trigger (data flip-flop or delayflip): the D flip-flop is an information storage device with a memory function and two stable states, is the most basic logic unit for forming various time sequence circuits, and is also an important unit circuit in a digital logic circuit. Thus, D flip-flops have wide application in digital systems and computers. The flip-flop has two stable states, namely "0" and "1", and can flip from one stable state to the other under the action of a certain external signal. The D flip-flop has a flip-flop composed of an integrated flip-flop and a gate circuit. The triggering mode includes level triggering and edge triggering, the former can be triggered when CP (clock pulse) =1, and the latter is triggered at the front edge (positive jump 0→1) of CP. The minor state of the D flip-flop depends on the state of the D-terminal before triggering, i.e., the minor state=d. Therefore, it has two functions of setting 0 and setting 1. For an edge D flip-flop, since the circuit has a hold blocking effect during cp=1, the data state change at the D terminal during cp=1 does not affect the output state of the flip-flop. D flip-flops are widely used and can be used as registers for digital signals, shift registers, frequency dividers, waveform generators, etc.

<4> sub-pulse (burst): a sub-pulse is a pulse sequence consisting of 100 or more modulated bits that is transmitted in one time slot carrying different logical channels in different information formats. The sub-pulses can thus be regarded as carriers of the logical channel transmissions on the physical channel. The sub-pulses are different depending on the logical channel. The sub-pulse signal means a sudden instant change, and the voltage or current with extremely short action time is called a pulse signal. It may be periodically repeated, or it may be aperiodic or single-shot.

The embodiment of the invention provides an ultra-narrow pulse stretching circuit, an ultra-narrow pulse stretching method and electronic equipment. With respect to a specific structure of an extremely narrow pulse stretching circuit, the embodiment of the present invention will be described with respect to a circuit structure of an extremely narrow pulse stretching circuit.

As shown in fig. 1, a schematic diagram of an extremely narrow pulse stretching circuit in an embodiment of the present invention is shown.

In one embodiment, an extremely narrow pulse stretching circuit includes: the calibration module is used for performing inverse transformation and delay processing on the control signal to obtain a calibration signal; the OR gate is used for carrying out logical OR operation on the detected signal and the calibration signal to obtain a clock signal; and the D trigger is used for outputting a widening signal according to the control signal and the clock signal.

Specifically, the calibration module is used for generating a calibration signal, the calibration signal needs to be opposite to the phase of the control signal input to the calibration module, and a certain delay exists between the phase of the calibration signal and the phase of the control signal. It should be noted that, in the present invention, the control signal input to the calibration module is actually a source envelope menu signal pulse of the electronic control unit, and this signal is generated by the control circuit of the preamble and is frequency-synchronized with the actual measured light pulse signal. Because the invention needs to map the single or multiple sub-pulses with extremely narrow pulse width of the detected extremely narrow optical pulse signal to the calibration signal completely, the rising edge and the falling edge of the sub-pulses of the detected optical signal should not coincide with the rising edge or the falling edge of the calibration signal so as to prevent the level signals from overlapping. Therefore, in order to solve the problem, the invention firstly carries out the inverse processing on the control signal, and then adjusts the phase difference delay between the calibration signal and the control signal according to the quantity and the pulse width of the actual ultra-narrow sub-pulses in the measured light signal so as to obtain the calibration signal meeting the requirement.

The OR gate is used for performing logical OR operation on the measured signal and the calibration signal to obtain a clock signal. Through the logical operation of the OR gate on the input signal, the ultra-narrow sub-pulse in the tested optical signal can be mapped onto the adjusted calibration signal, and then the signal output by the OR gate (the result of the logical OR operation of the calibration signal and the tested optical signal) is connected to the clock end of the D trigger to be used as the clock signal of the D trigger.

The D flip-flop functions to output a spread signal based on the control signal and the clock signal. In this application, the D flip-flop includes a signal input, a signal output, and a clock signal. The signal input end of the D trigger is connected with a control signal (the control signal is preferably a square wave signal with stable 50% duty ratio) generated by a control system, and the clock signal end of the D trigger is connected with a calibration signal processed by an OR gate and a processing result of a tested light signal. Based on the inputs of the signal input end and the clock signal end, the D trigger can generate corresponding output signals according to the input signals of the clock signal end and the level information of the input signals of the signal input end. When the clock signal input by the clock signal terminal is at the level rising edge (0-1), the output signal generated by the D trigger after the moment is the level value of the signal received by the D trigger at the signal input terminal at the moment (the level rising edge of the clock signal). For example, when the clock signal connected to the clock signal terminal of the D flip-flop is at the level rising edge, if the connection signal of the signal input terminal of the D flip-flop is 1 at this time (when the clock signal is at the level rising edge), the output signal of the D flip-flop at this time up to the stage of the next level rising edge of the clock signal is 1.

Based on the improvement, the D trigger only focuses on the level state of the input signal of the signal input end when the clock signal accessed by the clock signal end is in the rising edge, and the rising edge of the clock signal in the invention actually represents the occurrence time of the extremely narrow sub-pulse of the tested light signal, so the D trigger essentially maps the sub-pulse of the tested light signal based on the clock signal and the signal output by the input signal, and the output signal is the stretched tested light signal, and the duty ratio of the output signal is larger than that of the tested light signal, so the D trigger can be used as a sampling circuit sampling object to realize the frequency measurement of the extremely narrow pulse of the tested light signal.

On the connection relation of the calibration module, the OR gate and the D trigger, the signal input end of the D trigger is connected with a control signal, and the clock signal end of the D trigger is connected with the output end of the OR gate; the first input end of the OR gate is connected with the output end of the calibration module, and the second input end is connected with a tested signal; and the input end of the calibration module is connected with a control signal.

It should be noted that, in some existing circuits and methods for implementing stretching for narrow pulses, the characteristic of resetting the D flip-flop at the rising edge is also adopted to implement stretching for narrow pulses, but these existing methods generally use the clock end of the D flip-flop directly input to the narrow pulse signal before stretching as a clock signal, which may occur when the rising edge or the falling edge of the narrow pulse signal coincides with the rising edge or the falling edge of the input signal, so that the stretched output signal is distorted, and the state that the level of the narrow pulse input by the clock end of the D flip-flop changes with time cannot be accurately represented. However, in order to solve the above technical problem, in the present application, the clock signal that the D flip-flop accesses at the clock end is not an original narrow pulse signal, but is a logic operation result of the inverted and delayed control signal and the measured optical pulse signal after the or gate logic operation, which actually maps a single or multiple extremely narrow sub-pulses of the measured optical pulse signal into the control signal, so that the D flip-flop can output a stretched signal that is more accurate and mapped with the measured optical pulse signal.

In a more specific embodiment, the calibration module includes: the inverter is used for carrying out inverse transformation on the control signal to obtain an inverse control signal; and the phase difference delay unit is used for carrying out dislocation delay on the reverse phase control signal to obtain a calibration signal. And the output end of the phase difference delay unit is connected with the input end of the phase difference delay unit on the connection relation of the phase inverter and the phase difference delay unit.

Specifically, the inverter, i.e., the not gate in the logic gate, may invert the phase of the input signal by 180 degrees. For example, when the input signal of the inverter is at a high level, the output signal processed by the inverter is at a low level; when the input signal of the inverter is at low level, the output signal processed by the inverter is at high level.

The phase difference delay unit is a phase delay circuit, the phase delay circuit can adjust the phase of an input signal, namely, the phase of the input signal is subjected to phase shifting treatment, and the phase of the input signal can be adjusted to different degrees by adjusting circuit parameters of the phase delay circuit, so that a specific phase shifting signal which is actually needed (determined according to parameters such as pulse width, quantity and the like of extremely narrow sub-pulses of a detected signal) is generated.

In a more specific embodiment, the control signal is generated by the control system and is a square wave signal having a duty cycle of 50%. Specifically, the control signal is a source envelope menu signal pulse of the electronic control unit, and the control signal is generated by a preamble circuit, and the frequency of the control signal is synchronous with that of an actual measured signal.

In a more specific embodiment, the frequency of the control signal is between 100KHz and 1MHz.

In a more specific embodiment, the calibration signal and the control signal differ by 10ns. It should be noted that the phase difference between the calibration signal and the control signal is not always fixed, the phase difference between the calibration signal and the control signal can be determined according to the actual situation of the measured signal, and the adjustment of the phase difference can be realized by adjusting the parameters of the phase delay circuit.

In a more specific embodiment, the measured signal includes one or more sub-pulses with a pulse width of 200 ps-5 ns. Specifically, because the pulse width of the sub-pulse of the detected signal is extremely narrow (the pulse width is 200 ps-5 ns), the conventional sampling circuit cannot directly detect and sample the extremely narrow pulse signal, and therefore, after the extremely narrow detected light signal is widened, the extremely narrow detected light signal is enabled to meet the sampling condition of the sampling circuit so as to realize the detection of the extremely narrow pulse.

It should be noted that, in some existing applications of ultrafast pulse laser products, an analog stretching circuit is used to realize pulse width stretching by using charge and discharge characteristics of a stretching capacitor, so that a stretched pulse is adapted to a pulse which can be sampled by an intelligent chip and is kept for a minimum time, but the method is only suitable for a situation that only a single sub-pulse exists in a detected signal. For some practical applications, the number of the multiple sub-pulses can be adjusted online, because the energy of the multiple sub-pulses is greater than that of the single sub-pulse, the parameters of the broadening capacitance of one sub-pulse are adapted, and not the scene where the multiple sub-pulses exist is adapted, so that the parameters of the broadening capacitance need to be correspondingly adjusted to adapt to the scene, otherwise, sampling failure and metastable state occur, and even the stability of the product is affected. In the prior art, a time sequence logic chip with higher cost and higher performance is used for sampling the pulse, but in view of the fact that the pulse width of a signal is extremely narrow, the energy is extremely weak, the number of sub-pulses is not fixed, and the method can not solve the sampling requirement under the application scene of a plurality of sub-pulses.

The working logic of the very narrow pulse stretching circuit in single and multiple sub-pulse scenarios is described below in connection with fig. 2 and 3.

As shown in fig. 2, a schematic diagram of the circuit operation logic in a single sub-pulse scenario in an embodiment of the present application is shown.

As shown in the figure, a control system firstly generates a stable pulse waveform with 50% duty ratio, the pulse waveform is divided into two paths, the first path is connected to the input end of a D trigger, the second path is connected to the input end of an inverter, the inverter performs inversion processing, then the pulse waveform after the inversion processing is connected to a phase difference delay circuit, the phase difference delay circuit performs delay dislocation processing to generate a stable phase difference meeting actual requirements, and the signal after the phase difference delay processing is used as a calibration signal. And then accessing the calibration signal and the tested light pulse signal into two input ends of an OR gate for logic OR processing, and accessing the processed logic OR result into a clock end of the D trigger as a clock signal for carrying out signal reset on the rising edge of the clock signal by the D trigger so as to change the level value of the input signal. Based on the steps, the D trigger can reset the input signal through the clock signal to output a mapping waveform of the stretched and optimized tested signal, and the mapping waveform has a larger duty ratio compared with the tested signal, so that the mapping waveform can be used as a sampling object of a conventional sampling circuit to achieve the detection of the tested extremely narrow pulse.

As shown in fig. 3, a schematic diagram of the circuit operation logic under a plurality of sub-pulse scenarios in an embodiment of the present application is shown.

As shown in the figure, when a plurality of sub-pulses appear in the detected light signal, the output signal of the output end of the D trigger can still be kept stable, and because the pulse widening circuit is composed of a pure hardware logic circuit, under the condition that a plurality of sub-pulses appear in the detected light pulse, stable frequency detection of extremely narrow pulses can still be realized, and small light power jitter is insufficient to influence the frequency detection input end, so that the frequency detection device has better reliability and is suitable for being applied to industrial laser products.

As shown in fig. 4, a flow chart of an extremely narrow pulse stretching method in an embodiment of the present invention is shown. The ultra-narrow pulse stretching method in the embodiment mainly comprises the following steps:

step S41: and performing inverse transformation and delay processing on the control signal to obtain a calibration signal.

Specifically, the physical hardware corresponding to step S41 may be a calibration module, which may include an inverter and a phase difference delay unit. The inverter is used for performing inverse transformation on the control signal to obtain an inverse control signal; the phase difference delay unit is used for carrying out dislocation delay on the reverse phase control signal so as to obtain a calibration signal.

Step S42: and carrying out logical OR operation on the calibration signal and the measured signal to obtain a clock signal.

Specifically, the physical hardware corresponding to step S42 may be an or gate, or may be other digital circuit elements capable of implementing a logic operation function equivalent to that of the or gate, which is used for performing a logic or operation on the calibration signal and the measured signal to obtain a clock signal.

Step S43: and inputting the control signal into an input signal end of the D trigger, inputting the clock signal into a clock signal end of the D trigger, and outputting a widening signal by the D trigger according to the level state of the clock signal.

Specifically, the physical hardware corresponding to step S43 may be a D flip-flop, which is configured to reset the input signal at the time of the rising edge of the clock according to the clock signal received by the clock and the input signal received by the input terminal, so as to output the stretched signal that finally meets the pulse width requirement.

In some implementations of this embodiment, the measured signal includes one or more sub-pulses having a pulse width of 200ps to 5 ns. Because the pulse width of the sub-pulse of the detected signal is extremely narrow (the pulse width is 200 ps-5 ns), the conventional sampling circuit cannot directly detect and sample the extremely narrow pulse signal, and therefore, after the extremely narrow detected light signal is widened, the extremely narrow detected light signal meets the sampling condition of the sampling circuit so as to realize the detection of the extremely narrow pulse.

In some implementations of this embodiment, the control signal is generated by the control system and is a square wave signal having a duty cycle of 50% and a frequency of 100KHz to 1MHz. The control signal is a source envelope menu signal pulse of the electric control unit, and is generated by a preamble circuit, and the frequency of the control signal is synchronous with that of an actual measured signal.

Although the steps are described in the above-described sequential order in the above-described embodiments, it will be appreciated by those skilled in the art that in order to achieve the effects of the present embodiments, the steps need not be performed in such order, and may be performed simultaneously (in parallel) or in reverse order, and such simple variations are within the scope of the present invention.

According to the method, the source envelope menu signal pulse of the electronic control unit is connected to the input end of the D trigger, the calibration signal after logic OR processing and the processing result of the detected signal are connected to the clock end of the D trigger, rising edge level reset is carried out on the D trigger, the D trigger output level signal is turned over, the output signal of the D trigger follows the detected light signal pulse, when the detected light pulse generates jitter or a lost pulse string, the jitter or the lost pulse string can be immediately reflected through the frequency change of the output end, and the burst is timely detected by the control system, so that the control system generates protection actions or other execution actions.

In addition, the ultra-narrow pulse stretching circuit provided by the invention can be used in electronic equipment as an important component of a communication component, a sensor component or an input/output interface. The electronic device herein refers to a computer device that can be used in a mobile environment and supports multiple communication systems such as GSM, EDGE, TD _scdma, tdd_lte, fdd_lte, 5G, and the like, including mobile phones, notebook computers, tablet computers, and vehicle-mounted computers.

As shown in fig. 5, the electronic device at least includes a processor and a memory, and may further include a communication component, a sensor component, a power supply component, a multimedia component, and an input/output interface according to actual needs. The memory, the communication component, the sensor component, the power component, the multimedia component and the input/output interface are all connected with the processor. The memory may be a Static Random Access Memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a Central Processing Unit (CPU), a Graphics Processor (GPU), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. may be implemented using common components, and are not specifically described herein.

Compared with the prior art, the ultra-narrow pulse stretching circuit and the corresponding electronic equipment provided by the invention can realize the width expansion of ultra-narrow pulse signals through novel and ingenious circuit design, and the circuit implementation cost is lower.

In summary, the present application provides an extremely narrow pulse stretching circuit, an extremely narrow pulse stretching method and an electronic device, and the present invention provides a method for improving the stretching efficiency of extremely narrow pulses, which is used for realizing the stretching of extremely narrow pulses, especially a plurality of sub pulses with uncertain number, so as to facilitate the realization of more stable sampling of the stretched pulses. The invention can neglect the cost through the digital logic circuit, and realize the stable frequency measurement sampling function under the condition of adapting to single or a plurality of ultra-narrow sub-pulses. And because of the stationarity of the transmission time of the path of the combinational logic circuit, the absolute phase difference of the sampled signal relative to the original optical signal is unchanged, so that the stretched signal is synchronous with the original optical signal, and more optical and technological fine control is possible. Therefore, the method effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles of the present application and their effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present application. Accordingly, it is intended that all equivalent modifications and variations which may be accomplished by persons skilled in the art without departing from the spirit and technical spirit of the disclosure be covered by the claims of this application.

Claims

1. An extremely narrow pulse stretching circuit, comprising:

the calibration module is used for performing inverse transformation and delay processing on the control signal to obtain a calibration signal;

the OR gate is used for carrying out logical OR operation on the measured signal and the calibration signal to obtain a clock signal;

a D trigger for outputting a spread signal according to the control signal and the clock signal;

the input end of the D trigger is connected with a control signal, and the clock end of the D trigger is connected with the output end of the OR gate; the first input end of the OR gate is connected with the output end of the calibration module, and the second input end is connected with a tested signal; and the input end of the calibration module is connected with a control signal.

2. The ultra-narrow pulse stretching circuit according to claim 1, wherein the scaling module comprises:

the inverter is used for carrying out inverse transformation on the control signal to obtain an inverse control signal;

the phase difference delay unit is used for carrying out dislocation delay on the reverse phase control signal to obtain a calibration signal;

the output end of the phase difference delay unit is connected with the input end of the phase difference delay unit.

3. The ultra-narrow pulse stretching circuit according to any one of claims 1 or 2, wherein the control signal is generated by a control system and is a square wave signal having a duty cycle of 50%, the frequency of the control signal being synchronized with the measured signal.

4. The ultra-narrow pulse stretching circuit according to claim 3, wherein the frequency of the control signal is 100 KHz-1 MHz.

5. The ultra-narrow pulse stretching circuit according to any one of claims 1 or 2, wherein the nominal signal and the control signal differ by 10ns.

6. The ultra-narrow pulse stretching circuit according to any one of claims 1 or 2, wherein the measured signal comprises one or more sub-pulses having a pulse width of 200ps to 5 ns.

7. A method of ultra-narrow pulse stretching comprising:

the control signal is subjected to inverse transformation and delay treatment to obtain a calibration signal;

after the calibration signal and the measured signal are subjected to logical OR operation, a clock signal is obtained;

and inputting the control signal into an input signal end of the D trigger, inputting the clock signal into a clock signal end of the D trigger, and outputting a widening signal by an output signal end of the D trigger according to the level state of the clock signal.

8. The ultra-narrow pulse stretching method according to claim 7, wherein the measured signal comprises one or more sub-pulses having a pulse width of 200ps to 5 ns.

9. The method of claim 7, wherein the control signal is a square wave signal with a duty cycle of 50% and is generated by a control system, and the frequency of the control signal is 100 KHz-1 MHz and is synchronized with the measured signal.

10. An electronic device comprising an extremely narrow pulse stretching circuit as set forth in any one of claims 1 to 6.