CN115542131B - Chip testing method and circuit - Google Patents
Chip testing method and circuit Download PDFInfo
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- CN115542131B CN115542131B CN202211472908.3A CN202211472908A CN115542131B CN 115542131 B CN115542131 B CN 115542131B CN 202211472908 A CN202211472908 A CN 202211472908A CN 115542131 B CN115542131 B CN 115542131B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2882—Testing timing characteristics
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a chip testing method and a circuit, which are applied to a chip testing circuit.A microcontroller outputs a first time sequence to a chip to be tested through a first output interface connected with a delay unit and outputs a second time sequence to the chip to be tested through another first output interface; then, according to the clock source frequency of the microcontroller, the delay unit delays the level change time point of the circuit connected in series; then, responding to a third time sequence sent by the tested chip based on the received first time sequence, and receiving the third time sequence by the microcontroller through the first input interface; then, the oscilloscope measures the time difference of the time sequence level change edge of the test circuit connected with the two meter pens, and determines the time characteristic limit value according to the time difference of the time sequence level change edge. According to the requirement of the change edge interval time of the time sequences of two paths of signals and the delay time of the delay unit, the change edge interval time which meets the requirement of the change edge interval time is obtained, and a high-frequency clock source is not needed.
Description
Technical Field
The present disclosure relates to chip testing technologies, and in particular, to a chip testing method and circuit.
Background
In the chip test, the characteristics of the tested chip, such as voltage, current, rising or falling time value of an output port level signal, time interval from data receiving of an input port to data output of an output port and the like, can be measured by an existing instrument. The test of the time characteristic between the two input ports of the chip to be tested needs to use devices or equipment to simulate two paths of time sequences, and the time interval between two change edges is required to be adjustable between the two paths of time sequences.
For example, when two signal timings and/or two timings are to be generated, and the time interval between two changing edges is 0.1ns, theoretically, a device or equipment generating the two timings needs to use a clock source of at least 10GHz, and a common device or equipment cannot meet the requirement. That is, the time interval between the changing edges of the two paths of signals is smaller between the two paths of signal time sequences and/or the two paths of time sequences, and the device or equipment generating the two paths of time sequences needs a clock source with higher frequency.
Disclosure of Invention
In order to solve the defects of the prior art, the application provides a chip testing method and a chip testing circuit, according to the requirement of the change edge interval time of the time sequences of two paths of signals, the delay time of the delay unit is obtained, the change edge interval time which meets the requirement of the change edge interval time is obtained, and a high-frequency clock source is not needed.
The technical effect that this application will reach is realized through following scheme:
in a first aspect, the present application provides a chip testing method, which is applied to a chip testing circuit, where the chip testing circuit includes:
the microcontroller comprises a plurality of first input interfaces and a plurality of first output interfaces, wherein the first input interfaces are connected with the second output interfaces of the chip, and the first output interfaces are connected with the second input interfaces of the chip to form a plurality of test circuits;
the delay unit is connected in series with the test circuit of which any one first output interface is connected with the second input interface;
the two meter pens of the oscilloscope are respectively connected with the two test circuits connected with the first output interfaces and the second input interfaces, one of the test circuits is connected with the delay unit in series and is positioned between the delay unit and the chip;
the chip testing method comprises the following steps:
the microcontroller outputs a first time sequence to a chip to be tested through the first output interface connected with one delay unit and outputs a second time sequence to the chip to be tested through the other first output interface;
according to the clock source frequency of the microcontroller, the delay unit delays the level change time point of the circuit connected in series with the delay unit;
in response to a third timing issued by the chip under test based on receiving the first timing, the microcontroller receiving the third timing through the first input interface;
and the oscilloscope measures the time sequence level change edge time difference of the test circuit connected with the two meter pens, and determines the time characteristic limit value according to the time sequence level change edge time difference.
Optionally, the delaying unit delays a level change time point of a circuit connected in series according to a clock source frequency of the microcontroller, including:
setting the clock source frequency of the microcontroller to be highest, and delaying the level change time point of the circuit connected in series by the delay unit by preset time;
and reducing the clock source frequency of the microcontroller step by step, wherein each time the clock source frequency of the controller is reduced, the delay units delay the level change time points of the circuits connected in series by preset time.
Optionally, the delaying unit delays a level change time point of a circuit connected in series according to a clock source frequency of the microcontroller, and further includes:
repeating the steps: and reducing the clock source frequency of the microcontroller step by step, and reducing the clock source frequency of the controller each time, wherein the delay units delay the level change time point of the series circuit with preset time until the microcontroller receives the third time sequence through the first input interface, and the level change time interval of the test circuit, which is connected with the first output interface and the second input interface, of the two paths is taken as a target time interval.
Optionally, the chip testing method includes:
when the frequency of a clock source of the microcontroller is higher than a first threshold value, the level change time point of a test circuit connected in series with the delay unit lags behind a test circuit connected with another oscilloscope stylus;
when the frequency of the clock source of the microcontroller is lower than a second threshold value, the level change time point of the test circuit connected with the delay unit in series is ahead of the test circuit connected with the oscilloscope stylus.
Optionally, after the microcontroller receives the third timing step through the first input interface, the method includes:
and the microcontroller reads the data sent by the chip to be tested.
In a second aspect, the present application provides a chip test circuit, which is used for testing chip input timing characteristics, and the chip test circuit includes:
the microcontroller comprises a plurality of first input interfaces and a plurality of first output interfaces, wherein the first input interfaces are connected with the second output interfaces of the chip, and the first output interfaces are connected with the second input interfaces of the chip to form a plurality of test circuits;
the delay unit is connected in series with the test circuit with any one of the first output interface and the second input interface, and comprises an input end and an output end, wherein the input end is connected with any one of the first output interfaces, and the output end is connected with any one of the second input interfaces;
and two meter pens of the oscilloscope are respectively connected with the two test circuits connected with the first output interface and the second input interface, one of the test circuits is connected with the delay unit in series and is positioned between the delay unit and the chip.
Optionally, the delay unit is a gate logic device, an input level of an input end of the delay unit is the same as an output level of an output end of the delay unit, and the delay unit has a preset time interval between an input of the input end and an output of the output end.
Optionally, the microcontroller includes a clock source, the clock source is an internal phase-locked loop, and/or the microcontroller is connected to an external device, and the clock source is input by the external device.
In a third aspect, the present application provides a medium comprising executable instructions which, when executed by a processor of an electronic device, cause the electronic device to perform the method of any of the first aspects.
In a fourth aspect, the present application provides an electronic device, including the chip testing circuit according to any one of the second aspects, wherein the chip testing circuit employs the chip testing method according to any one of the first aspects.
The application has the following advantages:
the chip testing method is applied to a chip testing circuit, and the microcontroller outputs a first time sequence to a chip to be tested through the first output interface connected with one delay unit and outputs a second time sequence to the chip to be tested through the other first output interface; then, according to the clock source frequency of the microcontroller, the delay unit delays the level change time point of the circuit connected in series with the delay unit; then, responding to a third time sequence sent by the tested chip based on the first time sequence, and receiving the third time sequence by the microcontroller through the first input interface; and then, the oscilloscope measures the time difference of the time sequence level change edges of the test circuits connected with the two meter pens, and determines the time characteristic limit value according to the time difference of the time sequence level change edges. According to the requirement of the change edge interval time of the time sequence of two paths of signals, the delay unit delays the time to obtain the change edge interval time which is concealed by the requirement of the change edge interval time, and a high-frequency clock source is not needed.
Drawings
In order to more clearly illustrate the embodiments or the prior art solutions of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a chip test circuit according to an embodiment of the present application;
FIG. 2 is a first timing diagram of two test circuits according to an embodiment of the present application;
FIG. 3 is a second timing diagram of two test circuits according to an embodiment of the present invention;
FIG. 4 is a schematic flowchart illustrating a chip testing method according to an embodiment of the present application;
FIG. 5 is a timing diagram illustrating a chip testing method according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of the electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be described in detail and completely with reference to the following embodiments and accompanying drawings. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Non-limiting embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a chip test circuit in an embodiment of the present application, where the chip test circuit includes a microcontroller, a delay unit, and an oscilloscope, and is applied to test input timing characteristics of a chip so as to provide data for chip research.
Specifically, the microcontroller comprises a plurality of first input interfaces and a plurality of first output interfaces, wherein the first input interfaces are connected with the second output interfaces of the chip, and the first output interfaces are connected with the second input interfaces of the chip to form a plurality of test circuits. The microcontroller executes codes in sequence, controls level change of each first output interface, and outputs a time sequence to a device under test, wherein the device under test takes a chip as an example in this embodiment, and the microcontroller reads the level of the first input interface to obtain the output time sequence of the device under test, and decodes the read time sequence into received data.
In an embodiment, the first Input interface and the first Output interface are both GPIOs (General Purpose Input/Output), the first Input interface includes GPIO4, and the first Output interface includes GPIO1, GPIO2, and GPIO3. The second input interface comprises a data input interface, a synchronous clock interface and an enabling interface, and the second output interface comprises a data output interface. GPIO1 is connected with the data input interface, GPIO2 is connected with the synchronous clock interface, GPIO3 is connected with the enable interface, and GPIO4 is connected with the data output interface.
In the prior art, when the time interval of the level timings output by the two first output interfaces of the microcontroller is smaller, the microcontroller generating the two level timings needs a clock source with higher frequency, however, when the time interval of the level timings output by the two first output interfaces is a small value, especially a time interval value with a small limit, for example, the time interval is 0.1ns, the clock source with higher frequency is needed, but the common microcontroller cannot provide a clock source with high frequency. The delay unit is connected in series with the test circuit with any one of the first output interface and the second input interface, and comprises an input end and an output end, wherein the input end is connected with any one of the first output interface, and the output end is connected with any one of the second input interface. Namely, the delay unit adjusts the level transmission time of the test circuit, and after the first output interface of the microcontroller outputs level change, the delay unit can delay the time when the second input interface of the chip receives the level change. The time when the second input interface of the chip receives the level change is adjacent to the time when the second input interface of the chip in another test circuit receives the level change. The delay unit delays the time of the second input interface of the chip receiving the level change, and tests the level change time interval of two adjacent test circuits, that is, the two test circuits generate two signal time sequences, and the limit value of two change along the time interval is tested between the two time sequences, for example, the minimum value may be 0.1ns. According to the requirement of the changing edge interval time of the time sequences of the two paths of signals, the delay unit delays the time, so that the changing edge interval time withholding the requirement of the changing edge interval time can be obtained, and a high-frequency clock source is not needed.
And two meter pens of the oscilloscope are respectively connected with the two test circuits connected with the first output interface and the second input interface, wherein one test circuit is connected with the delay unit in series and is positioned between the delay unit and the chip. The oscilloscope can display the level change time of the two circuits, record the time sequence of two paths of signals generated by the two test circuits, and analyze the time interval of certain two change edges according to the time sequence of the two circuits of signals.
In an embodiment, as shown in fig. 2, the first output interface 1 of the microcontroller outputs a signal, and the original falling edge time and rising edge time of the signal received by the oscilloscope are t1 'and t 3', respectively, which is the first timing sequence. After the delay T ' time of the delay unit, the falling edge time received by the oscilloscope is changed into T1 ' and the rising edge time is changed into T3 '. The first output interface 2 of the microcontroller outputs a signal, the falling edge time of the signal is t2 ', and the rising edge time of the signal is t 4', which is the second time sequence. The time intervals between the time t1 'and the time t 3', and between the time t1 ″ and the time t3 ″, the time intervals between the time t2 'and the time t 4' may be the same as or different from the time intervals between the time t1 'and the time t 3', which is one of the reasons for the time interval value of the two-way timing sequence being changeable. The delay unit changes the time interval value between time t3 'and time t 4' to the time interval value t between time t3 'and time t 4', so as to facilitate the test chip to receive the limit value of the time interval value of the two signals. Wherein the first output interface 1 may be a GPIO1, and the first output interface 2 may be a GPIO2. That is, the first output interface 1 and the first output interface 2 may be any two of GPIO1, GPIO2, and GPIO3.
In another example, as shown in fig. 3, a clock source of a microcontroller changes a timing sequence of level output, a first output interface 1 of the microcontroller outputs a signal, and the original falling edge time and rising edge time of the signal received by an oscilloscope are T1 and T3, which are the first timing sequence. After the output of the first output interface 1 is delayed by the delay unit for T ', the falling edge time and the rising edge time received by the oscilloscope become T1 ' and T3 '. The first output interface 2 of the microcontroller outputs a signal, the falling edge time of the signal is T2, and the rising edge time of the signal is T4, which is the second timing sequence. The time intervals between the time T1 and the time T3, and between the time T1 'and the time T3' are the same, and the time interval between the time T2 and the time T4 may be the same as or different from the time interval between the time T1 and the time T3, which is one of the reasons for the time interval value of the two-way timing sequence to be variable. The delay unit changes the time interval between time T3 and time T4 to the time interval between time T3 ' and time T4 ' T ' so that the test chip can receive the limit value of the time interval between two signals. Wherein the first output interface 1 may be a GPIO1, and the first output interface 2 may be a GPIO2. That is, the first output interface 1 and the first output interface 2 may be any two of GPIO1, GPIO2, and GPIO3.
The delay time T ″ and the delay time T' in the above two embodiments are equal, in this case, the delay time of the delay unit is a fixed value, and the delay time of the delay unit is not adjustable.
In one embodiment, the delay unit is a gate logic device, and the input level of the input end of the delay unit is the same as the output level of the output end of the delay unit, so that circuit signal variation is prevented. The delay unit has a preset time interval between the input of the input terminal and the output of the output terminal.
In one embodiment, the microcontroller includes a clock source that is an internal phase locked loop. The internal phase-locked loop controls the frequency and the phase of an internal oscillation signal of the loop by using an externally input reference signal, and realizes the automatic tracking of the frequency of an output signal to the frequency of an input signal. In one example, the microcontroller is directly connected to an external device, and the clock source is input by the external device.
The application provides a chip testing method, which is applied to testing the input time sequence characteristics of a chip and adopts any one of the chip testing circuits to test. The specific structure of the chip test circuit refers to the above embodiments, and since the chip test method adopts all technical solutions of all the above embodiments, all the beneficial effects brought by the technical solutions of the above embodiments are at least achieved, and are not repeated here.
In one embodiment, as shown in fig. 4, the chip testing method includes:
s101: the microcontroller outputs a first time sequence to a chip to be tested through the first output interface connected with one delay unit and outputs a second time sequence to the chip to be tested through the other first output interface;
s102: according to the clock source frequency of the microcontroller, the delay unit delays the level change time point of the circuit connected in series with the delay unit;
s103: responding to a third timing sequence sent by the tested chip based on the first timing sequence, and receiving the third timing sequence by the microcontroller through the first input interface;
s104: and the oscilloscope measures the time difference of the time sequence level change edges of the test circuits connected with the two meter pens, and determines the time characteristic limit value according to the time difference of the time sequence level change edges.
The above steps may be performed out of order, and the above order is only the order of this implementation, and there is no limitation on the chip testing method of the present application.
The level change time of the test circuit between the microcontroller and the test chip is adjusted by the delay unit, the level change time interval of two adjacent test circuits can be set to different values, the limit value of the level change time of the two adjacent test circuits is tested, a device or equipment generating the time sequence of the two test circuits at least does not need to use a 10GHz clock source, and common devices or equipment can meet the test requirements. In an example, the test chip is a non-volatile flash memory chip, and the external connection of the test chip is an SPI (Serial Peripheral Interface) slave Interface, the data input Interface, the synchronous clock Interface, and the enable Interface are all second input interfaces, and the data output Interface is a second output Interface. For example, the minimum value of the time between the rising edges of the data input interface and the synchronous clock interface of the nonvolatile flash memory chip needs to be measured, the method can be adopted, and the delay time of the delay unit is adjusted, so that the time between the rising edges of the data input interface and the synchronous clock interface is the minimum value. A first output interface of the microcontroller is a general purpose output port and comprises a GPIO1, a GPIO2 and a GPIO3; the first input interface of the microcontroller is a general purpose input port and comprises GPIO4.GPIO1 is connected with the data input of the nonvolatile flash memory chip, GPIO2 is connected with the synchronous clock interface of the nonvolatile flash memory chip, GPIO3 is connected with the enable interface of the nonvolatile flash memory chip, and GPIO4 is connected with the data output interface of the nonvolatile flash memory chip, so as to form four test circuits.
In an embodiment, the delay unit delays the level change time point of the circuit connected in series according to the clock source frequency of the microcontroller, the clock source frequency of the microcontroller can be set to be the highest, and the delay unit delays the level change time point of the circuit connected in series by a preset time; and reducing the clock source frequency of the microcontroller step by step, wherein each time the clock source frequency of the controller is reduced, the delay units delay the level change time points of the circuits connected in series by preset time.
Referring to fig. 5, a timing chart of the chip testing method is shown, wherein the timing chart comprises a timing chart of level changes of an enable interface, a synchronous clock interface, a data input interface and a data output interface. t1 and t6 are time intervals of the falling edge of the enable interface level and the rising edge of the synchronous clock interface level, and t3 and t5 are time intervals of the rising edge of the enable interface level and the falling edge of the synchronous clock interface level. t1, t3, t5 and t6 are time intervals of level changes of the test circuit where the enable interface is located and the test circuit where the synchronous clock interface is located. t4 is the time interval between the level rising edge of the synchronous clock interface and the level falling edge of the data input interface, i.e. the time interval between the level changes of the test circuit where the synchronous clock interface is located and the test circuit where the data input interface is located. t2 is the time interval between the level rising edge of the synchronous clock interface and the level rising edge of the data input interface, and t2 is the time interval between the level change of the test circuit where the synchronous clock interface is located and the level change of the test circuit where the data input interface is located. Taking t2 as an example, how the chip testing method tests the time value of t2 will be described in detail below.
Specifically, the microcontroller code reads and executes a GPIO1 or GPIO2 output flip instruction requiring 2 clock cycles, the clock source frequency f of the microcontroller is 250mhz at the highest, the flip time from GPIO1 output flip to GPIO2 output flip is 8ns, and the delay time T of the delay unit device is 10ns. The turning instruction of the microcontroller chip end GPIO1 is advanced and is close to the turning instruction of the GPIO2, the GPIO2 is a synchronous clock as shown in figure 5 after passing through a delay unit, and T2=2/f-T.
In one example, when the clock source frequency of the microcontroller is 250MHz, the turning time of the GPIO1 output by the microcontroller chip before the turning of the GPIO2 is 8ns, after being delayed by the delay unit for 10ns, the turning time of the data input signal is delayed by the synchronous clock signal at the tested chip end for 2ns, and at this time, the t2 time is-2 ns;
in one example, when the clock source frequency of the microcontroller is 200MHz, the time for the microcontroller chip to output GPIO1 flip ahead of GPIO2 flip is 10ns, after 10ns delay by the delay unit, the data input signal and the synchronous clock signal flip at the same time at the tested chip end, and at this time, the time t2 is 0ns;
in one example, when the master frequency of the microcontroller is 198MHz, the time for turning over the GPIO1 output by the microcontroller chip and advancing the turning over of the GPIO2 is 10.1ns, after the delay of 10ns by the delay unit, at the end of a chip to be tested, the time t2 is 0.1ns when the data input signal turns over and advances the turning over of the synchronous clock signal;
in one example, when the master frequency of the microcontroller is 180MHz, the time for turning over the GPIO1 output by the microcontroller chip to advance the turning over of the GPIO2 is 11.1ns, after being delayed by the delay unit for 10ns, the time for turning over the data input signal to advance the turning over of the synchronous clock signal is 1.1ns at the tested chip end, and at this time, the time t2 is 1.1ns;
in an embodiment, the delaying unit delays the level change time point of the circuit connected in series according to the clock source frequency of the microcontroller, which may include repeating step-by-step reduction of the clock source frequency of the microcontroller, and each time the clock source frequency of the controller is reduced, the delaying unit delays the level change time point of the circuit connected in series by a preset time until the microcontroller receives the third timing sequence through the first input interface, and the level change time intervals of the test circuit in which the two paths of first output interfaces are connected to the second input interface are target time intervals.
And repeating the steps, wherein when the clock frequency of the microcontroller is gradually changed from high to low, the t2 time can be gradually changed from-2 ns to a positive number at the end of the chip to be tested. As in the above example, at a clock frequency of 200MHz of the microcontroller, a clock frequency change of 2MHz can achieve a change of 0.1ns in the timing, where 0.1ns is the target time interval.
In one example, the output frequency of a phase-locked loop of the microcontroller is up to 250MHz, an external clock or the output frequency of an internal phase-locked loop is adjusted, the clock frequency of the microcontroller is reduced by 2MHz, the microcontroller controls a command reading state register with GPIO1, GPIO2 and GPIO3 analog values of 0x05, when 0x05 byte is sent, the commands bit0 and bit3 are 1, the rest bits are 0, level inversion occurs when the GPIO1 outputs bit3, then the rising edge of the SCLK output by the GPIO2 is adjacent to the rising edge of the SCLK output by the GPIO1, and the two command times are adjacent to each other. After the register reading instruction is sent, the synchronous clock GPIO4 is continuously sent to read the output of the chip to be tested and organize the output into receiving data. Repeating the steps, when t2 is beyond the limit value of 0.1ns, the chip to be tested reads bit3 into 0, the instruction is received as 01H, and the chip to be tested does not output the value of the state register; when t2 is within the limit value, the tested chip correctly receives the instruction, the state register value is output, and the repetition is stopped. The oscilloscope is used to measure the time value between the inversion of the data input bit3 to the subsequent rising edge of the synchronous clock, which is the minimum value of t 2. The time characteristic limit values of the other two adjacent test circuits can be tested by using the same method.
In one embodiment, the chip testing method includes:
when the frequency of a clock source of the microcontroller is higher than a first threshold value, the level change time point of a test circuit connected in series with the delay unit lags behind a test circuit connected with another oscilloscope stylus;
when the frequency of the clock source of the microcontroller is lower than a second threshold value, the level change time point of the test circuit connected in series with the delay unit is ahead of that of the test circuit connected with the oscilloscope stylus.
Specifically, at the chip end to be tested, when the frequency of the microcontroller clock source is higher than a first threshold value, the level change time point of the path in which the delay unit is connected in series lags behind the other path; when the frequency of the microcontroller clock source is lower than a second threshold value, the level change time point of the path with the delay units is ahead of that of the other path. In short, according to the clock source frequency of the microcontroller, the delay unit controls the level change time point to enable the level changes of two adjacent circuits to have a certain time interval, and the time for adjusting the delay of the delay unit can adjust the time interval of the level changes of the two adjacent circuits, so that the time characteristic limit value determined by the time difference of the time sequence level change is obtained.
Further, after the microcontroller receives the third timing step through the first input interface, the microcontroller reads data sent by the chip to be tested.
The time intervals of the level variations of the other two adjacent test circuits can be tested by the above method, and the time characteristic limit value of the time sequence level variations of the two adjacent test circuits along the time difference is further determined.
The application also provides an electronic device, which comprises the chip test circuit, wherein the chip test circuit adopts the chip test method to test. The specific structure of the chip test circuit refers to the above embodiments, and since the chip test method adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here. Similarly, the specific steps of the chip testing method refer to the above embodiments, so that at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and are not repeated again.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application. On the hardware level, the electronic device further comprises a processor, and optionally further comprises an internal bus, a network interface and a memory. The Memory may include a Memory, such as a Random-Access Memory (RAM), and may further include a non-volatile Memory, such as at least 1 disk Memory. Of course, the electronic device may also include hardware required for other services.
The processor, the network interface, and the memory may be connected to each other via an internal bus, which may be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one double-headed arrow is shown in FIG. 6, but this does not indicate only one bus or one type of bus.
And the memory is used for storing the execution instruction. In particular, a computer program that can be executed by executing instructions. The memory may include both memory and non-volatile storage and provides execution instructions and data to the processor.
In a possible implementation manner, the processor reads the corresponding execution instruction from the nonvolatile memory into the memory and then runs the corresponding execution instruction, and can also obtain the corresponding execution instruction from other devices, so as to form the chip testing method on a logic level. The processor executes the execution instructions stored in the memory, so that the chip testing method provided by any embodiment of the application is realized through the executed execution instructions.
The method executed by the chip testing method provided by the embodiment shown in fig. 4 of the present application may be applied to a processor, or may be implemented by the processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules may be located in ram, flash, rom, prom, or eprom, registers, etc. as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.
The embodiment of the present application further provides a medium, where the medium stores an execution instruction, and when the stored execution instruction is executed by a processor of an electronic device, the electronic device can execute the chip testing method provided in any embodiment of the present application, and is specifically configured to execute the chip testing method.
The electronic device described in the foregoing embodiments may be a computer.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects.
The embodiments in the present application are described in a progressive manner, and the same and similar parts among the embodiments can be referred to each other, and each embodiment focuses on differences from other embodiments. In particular, for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference may be made to the partial description of the method embodiment for relevant points.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising one of 8230; \8230;" 8230; "does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises that element.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art to which the present application pertains. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A chip testing method is applied to a chip testing circuit and is characterized in that,
the chip test circuit includes:
the microcontroller comprises a plurality of first input interfaces and a plurality of first output interfaces, wherein the first input interfaces are connected with the second output interfaces of the chip, and the first output interfaces are connected with the second input interfaces of the chip to form a plurality of test circuits;
the delay unit is connected in series with the test circuit of any one of the first output interface and the second input interface;
the two meter pens of the oscilloscope are respectively connected with the two test circuits connected with the first output interfaces and the second input interfaces, one of the test circuits is connected with the delay unit in series and is positioned between the delay unit and the chip;
the chip testing method comprises the following steps:
the microcontroller outputs a first time sequence to a chip to be tested through the first output interface connected with one delay unit and outputs a second time sequence to the chip to be tested through the other first output interface;
according to the clock source frequency of the microcontroller, the delay unit delays the level change time point of the circuit connected in series with the delay unit;
in response to a third timing issued by the chip under test based on receiving the first timing, the microcontroller receiving the third timing through the first input interface;
and the oscilloscope measures the time difference of the time sequence level change edges of the test circuits connected with the two meter pens, and determines the time characteristic limit value according to the time difference of the time sequence level change edges.
2. The chip testing method according to claim 1, wherein the delaying unit delays a level change time point of a circuit connected in series thereto according to a clock source frequency of the microcontroller, comprising:
setting the clock source frequency of the microcontroller to be the highest, and delaying the level change time point of the series circuit by the delay unit by preset time;
and reducing the clock source frequency of the microcontroller step by step, wherein each time the clock source frequency of the controller is reduced, the delay units delay the level change time points of the circuits connected in series by preset time.
3. The chip testing method according to claim 2, wherein the delay unit delays a level change time point of a circuit connected in series thereto according to a clock source frequency of the microcontroller, further comprising:
repeating the steps: and reducing the clock source frequency of the microcontroller step by step, and reducing the clock source frequency of the controller each time, wherein the delay units delay the level change time point of the series circuit with preset time until the microcontroller receives the third time sequence through the first input interface, and the level change time interval of the test circuit, which is connected with the first output interface and the second input interface, of the two paths is taken as a target time interval.
4. The chip testing method according to claim 3, wherein the chip testing method comprises:
when the frequency of a clock source of the microcontroller is higher than a first threshold value, the level change time point of a test circuit connected in series with the delay unit lags behind a test circuit connected with another oscilloscope stylus;
when the frequency of the clock source of the microcontroller is lower than a second threshold value, the level change time point of the test circuit connected with the delay unit in series is ahead of the test circuit connected with the oscilloscope stylus.
5. The chip testing method according to claim 4, wherein after the step of receiving the third timing by the microcontroller through the first input interface, the method further comprises:
and the microcontroller reads the data sent by the chip to be tested.
6. A chip test circuit is applied to testing the input time sequence characteristics of a chip, and is characterized by comprising:
the microcontroller comprises a plurality of first input interfaces and a plurality of first output interfaces, wherein the first input interfaces are connected with the second output interfaces of the chip, and the first output interfaces are connected with the second input interfaces of the chip to form a plurality of test circuits; the microcontroller is used for outputting a first time sequence to a chip to be tested through the first output interface connected with one delay unit and outputting a second time sequence to the chip to be tested through the other first output interface; receiving a third time sequence sent by the tested chip based on the first time sequence through the first input interface in response;
the delay unit is connected in series with the test circuit of which any one first output interface is connected with the second input interface; the delay unit is used for delaying the level change time point of a circuit connected in series according to the clock source frequency of the microcontroller;
the two meter pens of the oscilloscope are respectively connected with the two test circuits connected with the first output interfaces and the second input interfaces, one of the test circuits is connected with the delay unit in series and is positioned between the delay unit and the chip; the oscilloscope is used for measuring the time sequence level change edge time difference of the test circuit connected with the two meter pens, and determining the time characteristic limit value according to the time sequence level change edge time difference.
7. The chip test circuit according to claim 6, wherein the delay unit is a gate logic device, and has an input level at an input terminal thereof being the same as an output level at an output terminal thereof, and the delay unit has a predetermined time interval between the input at the input terminal and the output at the output terminal.
8. The chip test circuit of claim 6, wherein the microcontroller comprises a clock source, the clock source is an internal phase-locked loop, and/or the microcontroller is connected to an external device, and the clock source is input by the external device.
9. A medium, characterized in that the medium comprises execution instructions which, when executed by a processor of an electronic device, cause the electronic device to perform the method of any one of claims 1-5.
10. An electronic device comprising a chip test circuit according to any one of claims 6 to 8, wherein the chip test circuit is tested using a chip test method according to any one of claims 1 to 5.
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| CN117686890B (en) * | 2024-02-01 | 2024-04-12 | 北京中成康富科技股份有限公司 | Single board testing method and system for millimeter wave therapeutic apparatus |
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