CN112242169B - Method for adjusting sampling phase and serial flash memory controller - Google Patents
Method for adjusting sampling phase and serial flash memory controller Download PDFInfo
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- CN112242169B CN112242169B CN201910640015.7A CN201910640015A CN112242169B CN 112242169 B CN112242169 B CN 112242169B CN 201910640015 A CN201910640015 A CN 201910640015A CN 112242169 B CN112242169 B CN 112242169B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
- H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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Abstract
The application discloses a method for adjusting sampling phase and a serial flash memory controller, wherein the serial flash memory controller comprises a processing path, the processing path comprises a delay circuit, and a register in the delay circuit receives a phase difference adjusting signal; the delay circuit is connected with the register, and delays the associated clock signal or the first data signal according to the phase difference adjusting signal so that the phase difference between the associated clock signal and the first data signal is within a first preset range; the adjusting delay circuit comprises a plurality of serially connected sub delay circuits, the delay time of each sub delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, and the preset quantity is related to the first time and the second time. By means of the mode, the phase difference between the associated clock signal and the first data signal can be adjusted, accurate sampling of the first data signal is achieved, and stable transmission of the data signal is achieved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a method for adjusting sampling phase and a serial flash memory controller.
Background
When the serial flash controller is used to access an external serial flash chip through a serial peripheral interface (SPI, serial Peripheral Interface) bus, the path delay inside the micro control unit (MCU, microcontroller Unit) chip and inside the serial flash chip is obviously changed due to the change of the ambient temperature and the working voltage. In addition, the printed circuit board (PCB, printed Circuit Board) routing delays of the different signal lines in the SPI bus may also be inconsistent.
When a bus Master Output/Slave Input (MOSI) signal in the SPI bus reaches the external serial flash memory chip, it is difficult to be sampled by the channel clock at the optimal sampling position due to the existence of signal delay, and in addition, when a bus Master Input/Slave Output (MISO) signal is sent back to the controller by the external serial flash memory chip under the driving of the channel clock, a problem of sampling point error may also occur.
The inventor of the application finds in long-term research and development that when an external serial flash chip is accessed by utilizing a serial flash controller, if the SPI bus time sequence is not satisfied due to the change of the ambient temperature and the working voltage or the inconsistent delay of a PCB bus, the common practice is to change the function correctly by reducing the frequency of the SPI bus under the condition of performance degradation. By reducing the SPI bus frequency, i.e., reducing the access speed of the serial flash, while normal functions may be achieved, performance is sacrificed and the speed requirements of some applications may not be met.
Disclosure of Invention
The problem that this application mainly solves is to provide a method and serial flash memory controller of adjustment sampling phase place, can adjust the phase difference of following way clock signal and first data signal, realizes the accurate sampling to first data signal, realizes data signal's stable transmission.
In order to solve the technical problem, another technical scheme adopted in the application is to provide: a serial flash controller comprising a processing path, the processing path comprising a delay circuit, the delay circuit comprising: the register is used for receiving the phase difference adjusting signal; the delay adjusting circuit is connected with the register and is used for delaying the associated clock signal or the first data signal according to the phase difference adjusting signal so that the phase difference between the associated clock signal and the first data signal is within a first preset range; the delay adjusting circuit comprises a plurality of serially connected sub-delay circuits, the delay time corresponding to each sub-delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, and the phase difference adjusting signal is used for indicating the associated clock signal or the first data signal to pass through a preset number of the sub-delay circuits, wherein the preset number is related to the first time and the second time.
In order to solve the technical problems, the technical scheme adopted by the application is that: a method of adjusting sampling phase, the method being applied to a serial flash memory controller, the serial flash memory controller comprising a processing path, the processing path comprising a delay circuit, the delay circuit comprising a register and an adjustment delay circuit coupled to the register, the method comprising: the register receives the phase difference adjusting signal; the delay adjusting circuit delays the associated clock signal or the first data signal according to the phase difference adjusting signal so that the phase difference between the delayed associated clock signal and the first data signal is within a first preset range; the delay adjusting circuit comprises a plurality of serially connected sub-delay circuits, the delay time corresponding to each sub-delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, and the phase difference adjusting signal is used for indicating the associated clock signal or the first data signal to pass through a preset number of the sub-delay circuits, wherein the preset number is related to the first time and the second time.
Through above-mentioned scheme, the beneficial effect of this application is: the register is used for receiving a phase difference adjusting signal, and the delay adjusting circuit adjusts delay time of the following clock signal or the first data signal according to the phase difference adjusting signal, so that the phase difference between the following clock signal and the first data signal is within a first preset range; the phase difference between the channel associated clock signal and the first data signal can be adjusted, so that the first data signal can be accurately sampled at the effective edge of the channel associated clock signal, and stable transmission of the data signal can be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a schematic diagram of an embodiment of a serial flash controller according to the present application;
FIG. 2 is a schematic diagram of another embodiment of a serial flash controller provided herein;
FIG. 3 is a schematic diagram of a delay circuit in another embodiment of a serial flash controller according to the present application;
FIG. 4 is a schematic diagram of a serial flash controller according to another embodiment of the present application;
FIG. 5 is a timing diagram of the associated clock signal and the MOSI signal provided by the present application;
FIG. 6 is a timing diagram of a second clock signal and a MISO signal provided by the present application;
FIG. 7 is a flow chart of an embodiment of a method for adjusting sampling phase provided in the present application;
fig. 8 is a flowchart of another embodiment of a method for adjusting sampling phase provided in the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a serial flash memory controller provided in the present application, where the serial flash memory controller includes a processing path 10, the processing path 10 includes a delay circuit 11, and the delay circuit 11 includes: register 111 and adjustment delay circuit 112.
The register 111 is configured to receive a phase difference adjustment signal, where the phase difference adjustment signal is configured to instruct the associated clock signal or the first data signal to pass through a preset number of sub-delay circuits 1121; the phase difference adjusting signal may be generated by an adjusting instruction input by an operator, and the operator obtains the phase difference between the associated clock signal and the first data signal through measurement, and performs a correlation operation according to the phase difference between the associated clock signal and the first data signal, so that the register 111 receives the phase difference adjusting signal.
The adjustment delay circuit 112 is connected to the register 111, and is configured to delay the associated clock signal or the first data signal according to the phase difference adjustment signal, so that the phase difference between the associated clock signal and the first data signal is within a first preset range, where the smaller the first preset range, the better the smaller the first preset range, for example, the phase difference range including 0 ° such as 0 ° to 10 °; specifically, when the associated clock signal lags the first data signal, the adjustment delay circuit 112 delays the first data signal according to the phase difference adjustment signal, so that the phase difference between the associated clock signal and the delayed first data signal is within a first preset range; when the first data signal lags the associated clock signal, the delay adjustment circuit 112 delays the associated clock signal according to the phase difference adjustment signal, so that the phase difference between the delayed associated clock signal and the first data signal is within a first preset range.
The adjusting delay circuit 112 includes a plurality of serially connected sub-delay circuits 1121, wherein a delay time corresponding to each sub-delay circuit 1121 is a first time, an initial phase difference between the associated clock signal and the first data signal is a second time, and a preset number is associated with the first time and the second time; specifically, the preset number may be a ratio of the second time to the first time.
In contrast to the prior art, the present embodiment provides a serial flash memory controller, in which the delay adjustment circuit 112 adjusts the delay time of the associated clock signal or the first data signal according to the phase difference adjustment signal obtained by the register 111, so as to control the phase difference between the associated clock signal and the first data signal within a first preset range; the phase difference between the channel associated clock signal and the first data signal can be adjusted, so that the first data signal can be accurately sampled at the effective edge of the channel associated clock signal, and stable transmission of the data signal can be realized.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of a serial flash memory controller provided in the present application, where the serial flash memory controller further includes: the clock source 21, the processing path includes: the delay circuit includes a first delay circuit 221 and a second delay circuit 231, and a first path 22 and a second path 23.
The clock source 21 is used to generate a standard clock signal, and furthermore, a clock signal of a different phase may be generated using a high-speed clock.
The first path 22 is connected to the clock source 21, and is configured to generate a following clock signal according to a standard clock signal, and transmit the following clock signal to an external device (not shown in the figure), where the following clock signal is a signal obtained by delaying the clock signal by a first preset delay time, and the first preset delay time includes a time when the standard clock signal is transmitted to the external device.
Further, the first passage 22 includes: the first delay circuit 221, the first delay circuit 221 is connected to the clock source 21, and is configured to receive the first phase difference adjustment signal, and delay the associated clock signal by a third preset delay time according to the first phase difference adjustment signal, where the third preset delay time is a difference between the second preset delay time and the first preset delay time, and the second preset delay time includes a time when the data signal to be sent is transmitted to the external device.
The second path 23 is connected to the clock source 21, and is configured to generate a first data signal according to a data signal to be sent, and send the first data signal to an external device; the first data signal is the same as the information contained in the data signal to be transmitted, and is a signal of which the data signal to be transmitted is delayed by a second preset delay time.
Further, the second passage 23 includes: the second delay circuit 231 and the first trigger 232, the second delay circuit 231 is configured to receive the second phase difference adjustment signal, and delay the first data signal by a fourth preset delay time according to the second phase difference adjustment signal, where the fourth preset delay time is a difference between the first preset delay time and the second preset delay time.
The first flip-flop 232 is connected to the clock source 21 and the second delay circuit 231, and is configured to generate a first data signal according to the first clock signal and a data signal to be transmitted, where the first clock signal is a signal obtained by delaying a standard clock signal by a fifth preset delay time.
The registers include a first register 2211 and a second register 2311, and the adjustment delay circuit includes a first adjustment delay circuit 2212 and a second adjustment delay circuit 2312; the first delay circuit 221 includes a first register 2211 and a first adjustment delay circuit 2212, and the first adjustment delay circuit 2212 includes a plurality of first sub-delay circuits 22121 connected in series; the second delay circuit 231 includes a second register 2311 and a second adjustment delay circuit 2312, and the second adjustment delay circuit 2312 includes a plurality of second sub-delay circuits 23121 connected in series.
The first phase difference adjustment signal is used for indicating that the associated clock signal passes through a preset number of first sub-delay circuits 22121, wherein the preset number is a ratio of a third preset delay time to the first time; the second phase difference adjustment signal is used for indicating that the first data signal passes through a preset number of second sub-delay circuits 23121, wherein the preset number is a ratio of a fourth preset delay time to the first time.
With continued reference to fig. 2, the serial flash controller further includes a third path 24, the third path 24 being connected to the clock source 21, the third path 24 including a third delay circuit 241 and a second flip-flop 242 connected to each other.
The third delay circuit 241 is connected to the second flip-flop 242 and the clock source 21, respectively, and includes a third register 2411 and a third adjustment delay circuit 2412 connected to each other; the third register 2411 is configured to receive a third phase difference adjustment signal, and the third adjustment delay circuit 2412 is configured to delay the second clock signal according to the third phase difference adjustment signal, so that a phase difference between the delayed data signal to be received and the delayed second clock signal is within a second preset range; the second preset range may be the same as the first preset range, and the second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time.
The second flip-flop 242 is configured to receive a data signal to be received sent by the external device, and generate a second data signal according to the delayed second clock signal and the data signal to be received.
Further, the third adjusting delay circuit 2412 includes a plurality of third sub-delay circuits 24121 connected in series, and the third phase difference adjusting signal is used to instruct the data signal to be received to pass through a preset number of the third sub-delay circuits 24121.
In a specific embodiment, as shown in fig. 3, each delay circuit further includes a selector, and an output terminal of each sub-delay circuit is connected to the selector, and the selector is connected to a register, and the register may receive the phase difference adjustment signal, and the selector is configured to determine the number of connected sub-delay circuits according to an output of the register.
The delay value of each sub-delay circuit is substantially the same under the same condition (in the case of the same temperature or voltage), and the sub-delay circuit is composed of a certain number and type of circuit units, such as inverters or buffers (not shown in the figure). By configuring the corresponding registers, the number of sub-delay circuits through which the signals pass can be selected, thereby realizing different delay value settings. When the register configuration value is 0, it means that no sub-delay circuit is passed, the delay circuit (including the first delay circuit 221 to the third delay circuit 241) has the minimum delay value, and the larger the register configuration value is, the larger the number of sub-delay circuits the signal passes through, and the larger the delay value of the corresponding delay circuit is.
For each sub-delay circuit, the higher the temperature, the larger the delay value, the higher the voltage, and the smaller the delay value. When the temperature is highest and the voltage is lowest, the sub-delay circuit has the largest delay value; the sub-delay circuit has the smallest delay value when the temperature is lowest and the voltage is highest.
Based on the sensitivity of the individual sub-delay circuits to temperature and voltage, STA (Static Timing Analysis ) analysis is typically used to obtain the maximum delay value, the typical delay value, and the minimum delay value.
In this embodiment, the phase difference between the associated clock signal and the first data signal is adjusted by the first delay circuit 221 and the second delay circuit 231, so that the first data signal is sampled at the rising edge of the associated clock signal, and the delay time of the second clock signal is adjusted by the third delay circuit 241 according to the associated clock signal, so that the data signal to be received can be sampled at the rising edge of the delayed second clock signal, thereby realizing stable transmission of the data signal.
In a specific embodiment, as shown in fig. 4, the clock source 21 is configured to generate the standard clock signal CLK, and may be further configured to generate other clock signals as needed, where the delay time of the slave clock signal SCK compared to the standard clock signal CLK is t1_a+t2_a+t3_a+t4_a, and the delay time generated by the first delay circuit 221 is t2_a. The MOSI signal is a data signal sent from the serial flash controller 20 to the serial flash chip 25, and is generated by the D flip-flop 232 driven by the first clock signal CLK1, wherein the phase relationship between the first clock signal CLK1 and the standard clock signal CLK is fixed regardless of the delay factor.
The selection principle of the delay times t2_a and t2_b of the first delay circuit 221 and the second delay circuit 231 is to select a delay value having a smaller value of t2_a as much as possible in the case where the delay difference between the channel clock signal SCK and the MOSI signal is minimum.
The external serial flash memory chip 25 samples the MOSI signal line with the rising edge of the clock of the channel clock signal, which should be located in the middle of the MOSI signal line data in order to achieve the best immunity and the fastest transmission speed, as shown in fig. 5.
To achieve optimal sampling, the relationship between the different delays needs to satisfy the following formula:
T1_A+T2_A+T3_A+T4_A＝T1_B+T2_B+T3_B+T4_B+Tdq
where Tdq is the delay of D flip-flop 232, tdq is typically small and can be selectively ignored. The PCB delay times t4_a and t4_b are estimated based on the trace length and dielectric constant of the PCB after the PCB design is completed, and the values of t1_ A, T3_ A, T1_b and t3_b are analyzed by the STA.
After the external serial flash chip 25 receives the associated clock signal clock SCK, the MISO signal is sent to the serial flash controller 20 after a certain processing delay, and the serial flash controller 20 samples the MISO signal using the sampling clock second clock signal generated by the standard clock signal CLK.
Similar to the MOSI signal, the rising edge of the second clock signal should be in the middle of the MISO signal line, as shown in fig. 6, for optimal immunity and fastest transmission speed.
To achieve optimal sampling, the relationship between the different delays needs to satisfy the following formula:
T1_A+T2_A+T3_A+T4_A+Tproc+T4_C+T3_C＝T1_C+T2_C-T SCK /2
where Tproc is the processing time of the external serial flash chip 25, generally available from a data manual; the PCB delay clock t4_c can be estimated according to the trace length and the dielectric constant of the PCB board, and the values of t1_ C, T2_c and t3_c can be obtained by STA analysis.
Based on the relation between the channel associated clock signal SCK and the MOSI signal, the delay value t2_a of the first delay circuit 221 is obtained, and then, according to the above equation, the delay value t2_c of the third delay circuit 241 is calculated.
As can be seen from the above analysis, by introducing 3 delay circuits, the MOSI signal and the MISO signal can be ensured to be sampled at the optimal sampling point all the time, and the serial flash controller 20 provided in this embodiment can be applied to an integrated circuit that realizes serial flash access by using the SPI bus.
Under different environmental temperature and operating voltage conditions, in order to ensure that the access speed of the serial flash memory is not affected, delay circuits are inserted into the paths of the channel associated clock signals SCK and MOSI signals in the serial flash memory controller 20, so that the delay difference that the channel associated clock signals SCK and MOSI signals reach the corresponding ports of the external serial flash memory chip 25 is changed. In addition, by inserting the third delay circuit 241 to adjust the sampling clock phase of the MISO signal, it is ensured that the MISO signal can be correctly sampled. In addition, the delay value of each delay circuit can be selected through an independent register, and the current SPI bus speed, the ambient temperature, the working voltage and the PCB wiring can be comprehensively considered, so that the most suitable delay value can be selected.
Referring to fig. 1 and 7, fig. 7 is a flowchart of an embodiment of a method for adjusting sampling phase provided in the present application, where the method is applied to a serial flash memory controller, the serial flash memory controller includes a processing path 10, the processing path 10 includes a delay circuit 11, the delay circuit 11 includes a register 111 and an adjusting delay circuit 112 connected to the register, and the method includes:
step 71: the register receives the phase difference adjustment signal.
The adjusting delay circuit 112 includes a plurality of serially connected sub-delay circuits 1121, where a delay time corresponding to each sub-delay circuit 1121 is a first time; the phase difference adjustment signal is used to indicate that the associated clock signal or the first data signal passes through a preset number of sub-delay circuits 1121.
Step 72: the delay adjusting circuit delays the associated clock signal or the first data signal according to the phase difference adjusting signal so that the phase difference between the delayed associated clock signal and the first data signal is within a first preset range.
The channel associated clock signal is a clock signal generated by the serial flash memory controller, the clock signal is sent to the SPI slave device, the first data signal can be MOSI signal, and under the conditions of different environment temperatures and working voltages, in order to ensure that the access speed of the serial flash memory is not affected, the first data signal is accurately sampled according to the channel associated clock signal, and the channel associated clock signal can be realized by adjusting the phase difference between the channel associated clock signal and the first data signal; the initial phase difference between the associated clock signal and the first data signal is a second time, and the preset amount is associated with the first time and the second time.
The operator may obtain the phase difference between the associated clock signal and the first data signal by measuring, and in a specific embodiment, the delay of each node in the circuit may be analyzed by using static timing analysis, so as to obtain the phase difference. After acquiring the phase difference between the associated clock signal and the first data signal, the operator sends an adjustment instruction to the register 111 according to the phase difference to adjust the delay time of the associated clock signal or the first data signal, so that the first data signal can be sampled at the effective edge of the associated clock signal, that is, the phase difference between the associated clock signal and the first data signal is within a first preset range; by setting the delay time of the associated clock signal or the first data signal, the delay difference that the associated clock signal and the first data signal reach the corresponding port of the external slave device is changed.
According to the embodiment, the delay time of the associated clock signal or the first data signal is adjusted according to the phase difference adjusting signal, so that the phase difference between the associated clock signal and the first data signal is within a first preset range; the phase difference between the channel associated clock signal and the first data signal can be adjusted, so that the first data signal can be accurately sampled at the effective edge of the channel associated clock signal, and stable transmission of the data signal can be realized.
Referring to fig. 2 and 8, fig. 8 is a flowchart illustrating another embodiment of a method for adjusting sampling phase provided in the present application, where the registers include a first register 2211, a second register 2311, and a third register 2411, the adjusting delay circuit includes a first adjusting delay circuit 2212, a second adjusting delay circuit 2312, and a third adjusting delay circuit 2412, the first adjusting delay circuit 2212 includes a plurality of first sub-delay circuits 22121 connected in series, the second adjusting delay circuit 2312 includes a plurality of second sub-delay circuits 23121 connected in series, and the third adjusting delay circuit 2412 includes a plurality of third sub-delay circuits 24121 connected in series; the method comprises the following steps:
step 81: a first flip-flop in the serial flash memory controller generates a first data signal according to a first clock signal and a data signal to be transmitted.
The data signal to be transmitted is a data signal to be transmitted to the SPI slave device by the serial flash controller, the first clock signal is a signal obtained by delaying the standard clock signal by a fifth preset delay time, and the standard clock signal is a signal generated by the clock source 21 in the serial flash controller.
The first clock signal and the data signal to be transmitted are input into the first flip-flop 232, and the first flip-flop 232 samples the data signal to be transmitted at a rising edge of the first clock signal, so as to obtain a first data signal, where the first data signal is a MOSI signal, and the first data signal is a signal after the data signal to be transmitted is delayed by a second preset delay time, and the second preset delay time includes a time when the data signal to be transmitted is transmitted to an external device.
Step 82: the register receives the phase difference adjustment signal.
Step 83: the first register receives a first phase difference adjusting signal, and the first adjusting delay circuit delays the associated clock signal by a third preset delay time according to the first phase difference adjusting signal.
The associated clock signal is a signal obtained by delaying the standard clock signal, which is generated by the clock source 21, by a first predetermined delay time, which includes the time the standard clock signal is transmitted to the external device.
The first phase difference adjustment signal is used for indicating that the associated clock signal passes through a preset number of first sub-delay circuits 22121, the third preset delay time is a difference value between the second preset delay time and the first preset delay time, and the preset number is a ratio of the third preset delay time to the first time.
Step 84: the second register receives a second phase difference adjusting signal, and the second adjusting delay circuit delays the first data signal by a fourth preset delay time according to the second phase difference adjusting signal.
The fourth preset delay time is a difference between the first preset delay time and the second preset delay time, and the second phase difference adjustment signal is used for indicating that the first data signal passes through a preset number of second sub-delay circuits 23121, wherein the preset number is a ratio of the fourth preset delay time to the first time.
Step 85: the serial flash memory controller transmits the delayed channel associated clock signal and the first data signal to the external device, or transmits the channel associated clock signal and the delayed first data signal to the external device.
If the second preset delay time is greater than the first preset delay time, the following clock signal is indicated to be advanced compared with the first data signal, and the following clock signal is delayed by a third preset delay time in order to accurately sample the first data signal at the rising edge of the following clock signal.
If the second preset delay time is less than or equal to the first preset delay time, the delay of the first data signal by a fourth preset delay time is indicated to be delayed by the channel associated clock signal compared with the first data signal so as to accurately sample the first data signal at the rising edge of the channel associated clock signal.
In a specific embodiment, the rising edge of the associated clock signal may correspond to an intermediate position of the first data signal, that is, the phase difference between the associated clock signal and the first data signal is 0, as shown in fig. 5.
After the channel associated clock signal or the first data signal is delayed, the channel associated clock signal and the first data signal are transmitted to an external device, which may be an external slave device.
Step 86: the second trigger receives a data signal to be received sent by the external device.
The serial flash memory controller samples the first data signal at a rising edge of the associated clock signal, and also receives a data signal to be received sent by the external device, where the data signal to be received may be a MISO signal.
Step 87: the third register receives a third phase difference adjustment signal.
The third phase difference adjustment signal is used to instruct the data signal to be received to pass through the preset number of third sub-delay circuits 24121.
Step 88: the third adjusting delay circuit delays the second clock signal according to the third phase difference adjusting signal so that the phase difference between the delayed data signal to be received and the delayed second clock signal is within a second preset range.
Step 89: the serial flash memory controller generates a second data signal according to the delayed second clock signal and the data signal to be received.
The second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time, and in order to accurately sample the signal to be received at the rising edge of the second clock signal, the delay time of the second clock signal is adjusted according to the associated clock signal, so that the phase difference between the data signal to be received and the delayed second clock signal is within a second preset range.
In a specific embodiment, the rising edge of the second clock signal may correspond to an intermediate position of the data signal to be received, that is, the phase difference between the second clock signal and the data signal to be received is 0, as shown in fig. 6.
After the phase difference between the second clock signal and the data signal to be received is adjusted, the data signal to be received and the delayed second clock signal are input into the second flip-flop 242 to generate a second data signal, where the second data signal is a signal delayed from the signal to be received, and the data information contained in the second data signal is the same.
According to the embodiment, the phase difference between the random clock signal and the first data signal is adjusted, so that the first data signal is sampled at the rising edge of the random clock signal, the delay time of the second clock signal is adjusted according to the random clock signal, and the data signal to be received can be sampled at the rising edge of the delayed second clock signal, so that stable transmission of the data signal is realized.
In the several embodiments provided in the present application, it should be understood that the disclosed methods and apparatuses may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated units may be implemented in hardware or in software functional units.
The foregoing is only examples of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.
Claims (13)
1. A serial flash memory controller comprising a processing path, the processing path comprising a delay circuit, the delay circuit comprising:
a register for receiving a phase difference adjustment signal;
the delay adjusting circuit is connected with the register and used for delaying the associated clock signal or the first data signal according to the phase difference adjusting signal so that the phase difference between the associated clock signal and the first data signal is within a first preset range;
the delay adjusting circuit comprises a plurality of serially connected sub-delay circuits, the delay time corresponding to each sub-delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, the phase difference adjusting signal is used for indicating that the associated clock signal or the first data signal passes through a preset number of the sub-delay circuits, and the preset number is related to the first time and the second time;
wherein the processing path comprises a first path and a second path, and the delay circuit comprises a first delay circuit and a second delay circuit;
the first path comprises the first delay circuit, and is used for receiving a first phase difference adjusting signal and delaying the associated clock signal by a third preset delay time according to the first phase difference adjusting signal;
the second path includes the second delay circuit for receiving a second phase difference adjustment signal and delaying the first data signal by a fourth preset delay time according to the second phase difference adjustment signal.
2. The serial flash controller of claim 1, further comprising a clock source for generating a standard clock signal;
the first path is connected with the clock source and is used for generating a channel associated clock signal according to the standard clock signal and transmitting the channel associated clock signal to external equipment; the channel associated clock signal is a signal of the standard clock signal delayed by a first preset delay time, wherein the first preset delay time comprises the time of the standard clock signal transmitted to external equipment;
the second path is connected with the clock source and is used for generating the first data signal according to a data signal to be sent and sending the first data signal to the external equipment; the first data signal is the same as the information contained in the data signal to be sent, and is a signal of the data signal to be sent delayed by a second preset delay time, wherein the second preset delay time comprises the time of transmission of the data signal to be sent to the external equipment.
3. The serial flash controller of claim 2, wherein the third predetermined delay time is a difference between the second predetermined delay time and the first predetermined delay time;
the fourth preset delay time is a difference value between the first preset delay time and the second preset delay time.
4. The serial flash controller of claim 3, wherein the serial flash controller comprises a memory controller,
the register comprises a first register and a second register, and the adjustment delay circuit comprises a first adjustment delay circuit and a second adjustment delay circuit; the first delay circuit comprises the first register and the first adjustment delay circuit, and the first adjustment delay circuit comprises a plurality of first sub-delay circuits connected in series; the second delay circuit comprises the second register and the second adjustment delay circuit, and the second adjustment delay circuit comprises a plurality of second sub-delay circuits connected in series; the first phase difference adjusting signal is used for indicating the channel associated clock signal to pass through the preset number of the first sub-delay circuits, wherein the preset number is the ratio of the third preset delay time to the first time; the second phase difference adjustment signal is configured to instruct the first data signal to pass through the preset number of the second sub-delay circuits, where the preset number is a ratio of the fourth preset delay time to the first time.
5. The serial flash controller of claim 4, wherein the serial flash controller comprises a memory controller,
the second path further comprises a first trigger which is respectively connected with the clock source and the second delay circuit and is used for generating the first data signal according to a first clock signal and the data signal to be transmitted;
the first clock signal is a signal obtained by delaying the standard clock signal by a fifth preset delay time.
6. The serial flash controller of claim 2, further comprising a third path comprising:
a third delay circuit connected to the clock source and including a third register and a third adjustment delay circuit; the third register is configured to receive a third phase difference adjustment signal, and the third adjustment delay circuit is configured to delay a second clock signal according to the third phase difference adjustment signal, so that a phase difference between a delayed data signal to be received and the delayed second clock signal is within a second preset range, where the second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time;
the second trigger is connected with the third delay circuit and is used for receiving a data signal to be received sent by the external equipment and generating a second data signal according to the delayed second clock signal and the data signal to be received;
the third adjusting delay circuit comprises a plurality of third sub-delay circuits connected in series, and the third phase difference adjusting signal is used for indicating the data signal to be received to pass through the preset number of third sub-delay circuits.
7. The serial flash controller of claim 1, wherein the serial flash controller comprises a memory controller,
the delay circuit further comprises a selector, the output end of each sub delay circuit is connected with the selector, the selector is connected with the register, and the selector is used for determining the number of the connected sub delay circuits according to the output of the register.
8. A method of adjusting sampling phase, applied to a serial flash controller, the serial flash controller comprising a processing path including a delay circuit, the delay circuit including a register and an adjustment delay circuit coupled to the register, the method comprising:
the register receives a phase difference adjustment signal;
the delay adjustment circuit delays an associated clock signal or a first data signal according to the phase difference adjustment signal so that the phase difference between the associated clock signal and the first data signal is within a first preset range;
the delay adjusting circuit comprises a plurality of serially connected sub-delay circuits, the delay time corresponding to each sub-delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, the phase difference adjusting signal is used for indicating that the associated clock signal or the first data signal passes through a preset number of the sub-delay circuits, and the preset number is related to the first time and the second time;
wherein the processing path comprises a first path and a second path, and the delay circuit comprises a first delay circuit and a second delay circuit;
the first path comprises the first delay circuit, and is used for receiving a first phase difference adjusting signal and delaying the associated clock signal by a third preset delay time according to the first phase difference adjusting signal;
the second path includes the second delay circuit for receiving a second phase difference adjustment signal and delaying the first data signal by a fourth preset delay time according to the second phase difference adjustment signal.
9. The method of adjusting a sampling phase according to claim 8, wherein,
the associated clock signal is a signal of a standard clock signal delayed by a first preset delay time, wherein the first preset delay time comprises the time of the standard clock signal transmitted to external equipment; the first data signal is a signal of which the data signal to be sent is delayed by a second preset delay time; the standard clock signal is a signal generated by a clock source in the serial flash memory controller, and the second preset delay time comprises the time when the data signal to be sent is transmitted to the external device.
10. The method of adjusting sampling phase according to claim 9, wherein the register comprises a first register and a second register, the adjustment delay circuit comprising a first adjustment delay circuit and a second adjustment delay circuit, the first adjustment delay circuit comprising a plurality of first sub-delay circuits connected in series, the second adjustment delay circuit comprising a plurality of second sub-delay circuits connected in series; the step of delaying the associated clock signal or the first data signal by the delay adjustment circuit according to the phase difference adjustment signal so that the phase difference between the associated clock signal and the first data signal is within a first preset range includes:
the first register receives a first phase difference adjustment signal, wherein the first phase difference adjustment signal is used for indicating the channel-associated clock signal to pass through the preset number of first sub-delay circuits; the first delay adjusting circuit delays the associated clock signal by a third preset delay time according to the first phase difference adjusting signal, wherein the third preset delay time is a difference value between the second preset delay time and the first preset delay time, and the preset number is a ratio of the third preset delay time to the first time; or alternatively
The second register receives a second phase difference adjustment signal, wherein the second phase difference adjustment signal is used for indicating the first data signal to pass through the preset number of second sub-delay circuits; the second adjustment delay circuit delays the first data signal by a fourth preset delay time according to the second phase difference adjustment signal, wherein the fourth preset delay time is a difference value between the first preset delay time and the second preset delay time, and the preset number is a ratio of the fourth preset delay time to the first time.
11. The method of adjusting sampling phase according to claim 9, wherein prior to the step of the register receiving a phase difference adjustment signal, comprising:
a first trigger in the serial flash memory controller generates a first data signal according to a first clock signal and the data signal to be transmitted;
the first clock signal is a signal obtained by delaying the standard clock signal by a fifth preset delay time.
12. The method of adjusting sampling phase according to claim 9, further comprising:
the serial flash memory controller transmits the delayed associated clock signal and the first data signal to an external device, or transmits the associated clock signal and the delayed first data signal to the external device.
13. The method of adjusting sampling phase of claim 12, wherein the register further comprises a third register, the adjustment delay circuit further comprising a third adjustment delay circuit comprising a plurality of third sub-delay circuits in series, the method further comprising:
a second trigger receives a data signal to be received sent by the external equipment;
the third register receives a third phase difference adjusting signal, wherein the third phase difference adjusting signal is used for indicating the data signal to be received to pass through the preset number of third sub-delay circuits;
the third adjusting delay circuit delays a second clock signal according to the third phase difference adjusting signal so that the phase difference between the delayed data signal to be received and the delayed second clock signal is within a second preset range;
the serial flash memory controller generates a second data signal according to the delayed second clock signal and the data signal to be received;
the second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time.
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| CN116879725B (en) * | 2023-09-06 | 2023-12-08 | 西安紫光国芯半导体股份有限公司 | Sampling circuit, self-test circuit and chip |
| CN117590897A (en) * | 2023-11-23 | 2024-02-23 | 北京国科天迅科技股份有限公司 | Chip and chip control method |
| CN117785069B (en) * | 2024-02-26 | 2024-05-24 | 合肥康芯威存储技术有限公司 | Memory and parameter adjustment method thereof |
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