CN112242169A - Method for adjusting sampling phase and serial flash memory controller - Google Patents
Method for adjusting sampling phase and serial flash memory controller Download PDFInfo
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- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
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Abstract
The application discloses a method for adjusting sampling phase and a serial flash memory controller, wherein the serial flash memory controller comprises a processing path, the processing path comprises a delay circuit, and a register in the delay circuit receives a phase difference adjusting signal; an adjusting delay circuit in the delay circuit is connected with the register and delays the associated clock signal or the first data signal according to the phase difference adjusting signal so as to enable the phase difference between the associated clock signal and the first data signal to be within a first preset range; the adjusting delay circuit comprises a plurality of sub-delay circuits connected in series, the delay time of each sub-delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, and the preset number is associated with the first time and the second time. By means of the method, the phase difference between the associated clock signal and the first data signal can be adjusted, accurate sampling of the first data signal is achieved, and stable transmission of the data signal is achieved.
Description
Technical Field
The present application relates to the field of electronic technologies, and in particular, to a method for adjusting a sampling phase and a serial flash memory controller.
Background
When a Serial flash memory controller is used for accessing an external Serial flash memory chip through a Serial Peripheral Interface (SPI) bus, path delay changes inside a Micro Control Unit (MCU) chip and inside the Serial flash memory chip are significant due to changes in ambient temperature and operating voltage. In addition, Printed Circuit Board (PCB) routing delays for different signal lines in the SPI bus may also be inconsistent.
When a bus Master Output/Slave Input (MOSI) signal in the SPI bus reaches the external serial flash memory chip, it is difficult to sample the signal at the optimal sampling position by the Slave clock due to the signal delay, and when a bus Master Input/Slave Output (MISO) signal is sent back to the controller by the external serial flash memory chip under the driving of the Slave clock, a problem of sampling point errors may also occur.
The inventor of the present application found in long-term research and development that, when a serial flash memory controller is used to realize external serial flash memory chip access, if the SPI bus timing sequence is not satisfied due to environmental temperature, operating voltage variation, or PCB bus delay inconsistency, the function is often corrected on the condition of performance degradation by reducing the frequency of the SPI bus. By reducing the SPI bus frequency, i.e., reducing the access speed of the serial flash memory, while normal functionality can be achieved, performance is sacrificed and the speed requirements of some applications may not be met.
Disclosure of Invention
The main problem to be solved in the present application is to provide a method for adjusting a sampling phase and a serial flash memory controller, which can adjust a phase difference between a channel associated clock signal and a first data signal, implement accurate sampling of the first data signal, and implement stable transmission of the data signal.
In order to solve the above technical problem, another technical solution adopted by the present application is to provide: a serial flash memory controller, the serial flash memory controller comprising a processing path, the processing path comprising a delay circuit, the delay circuit comprising: the register is used for receiving the phase difference adjusting signal; the adjusting delay circuit is connected with the register and used for delaying the associated clock signal or the first data signal according to the phase difference adjusting signal so as to enable the phase difference between the associated clock signal and the first data signal to be within a first preset range; the adjusting delay circuit comprises a plurality of sub-delay circuits connected in series, the delay time corresponding to each sub-delay circuit is first time, the initial phase difference between the channel associated clock signal and the first data signal is second time, the phase difference adjusting signal is used for indicating that the channel associated clock signal or the first data signal passes through a preset number of sub-delay circuits, and the preset number is associated with the first time and the second time.
In order to solve the technical problem, the technical scheme adopted by the application is to provide: a method for adjusting sampling phase is applied to a serial flash memory controller, the serial flash memory controller comprises a processing path, the processing path comprises a delay circuit, the delay circuit comprises a register and an adjusting delay circuit connected with the register, the method comprises the following steps: the register receives the phase difference adjusting signal; the adjusting delay circuit delays the associated clock signal or the first data signal according to the phase difference adjusting signal, so that the phase difference between the delayed associated clock signal and the first data signal is within a first preset range; the adjusting delay circuit comprises a plurality of sub-delay circuits connected in series, the delay time corresponding to each sub-delay circuit is first time, the initial phase difference between the channel associated clock signal and the first data signal is second time, the phase difference adjusting signal is used for indicating that the channel associated clock signal or the first data signal passes through a preset number of sub-delay circuits, and the preset number is associated with the first time and the second time.
Through the scheme, the beneficial effects of the application are that: the register is used for receiving the phase difference adjusting signal, and the adjusting delay circuit adjusts the delay time of the associated clock signal or the first data signal according to the phase difference adjusting signal, so that the phase difference between the associated clock signal and the first data signal is within a first preset range; the phase difference between the channel associated clock signal and the first data signal can be adjusted, and the first data signal can be accurately sampled at the effective edge of the channel associated clock signal, so that the stable transmission of the data signal is realized.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic diagram illustrating a serial flash memory controller according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a serial flash memory controller according to another embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a delay circuit in another embodiment of a serial flash memory controller according to the present application;
FIG. 4 is a schematic diagram illustrating a serial flash memory controller according to another embodiment of the present disclosure;
FIG. 5 is a timing diagram of the associated clock signal and the MOSI signal provided herein;
FIG. 6 is a timing diagram of the second clock signal and the MISO signal provided herein;
FIG. 7 is a flowchart illustrating an embodiment of a method for adjusting a sampling phase according to the present disclosure;
fig. 8 is a flowchart illustrating another embodiment of a method for adjusting a sampling phase according to the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an embodiment of a serial flash memory controller provided in the present application, where the serial flash memory controller includes a processing path 10, the processing path 10 includes a delay circuit 11, and the delay circuit 11 includes: a register 111 and an adjusting delay circuit 112.
The register 111 is configured to receive a phase difference adjustment signal, where the phase difference adjustment signal is used to indicate that the associated clock signal or the first data signal passes through the sub-delay circuits 1121 in the predetermined number; the phase difference adjustment signal may be generated by an adjustment instruction input by an operator, and the operator obtains the phase difference between the associated clock signal and the first data signal through measurement, and performs a correlation operation according to the phase difference between the associated clock signal and the first data signal, so that the register 111 receives the phase difference adjustment signal.
The adjusting delay circuit 112 is connected to the register 111, and is configured to delay the associated clock signal or the first data signal according to the phase difference adjusting signal, so that a phase difference between the associated clock signal and the first data signal is within a first preset range, where the smaller the first preset range, the better the first preset range is, and the phase difference range may be a phase difference range including 0 °, for example, 0 ° to 10 °; specifically, when the slave clock signal lags behind the first data signal, the adjustment delay circuit 112 delays the first data signal according to the phase difference adjustment signal, so that the phase difference between the slave clock signal and the delayed first data signal is within a first preset range; when the first data signal lags the slave clock signal, the adjustment delay circuit 112 delays the slave clock signal according to the phase difference adjustment signal, so that the phase difference between the delayed slave clock signal and the first data signal is within a first preset range.
The adjusting delay circuit 112 includes a plurality of sub-delay circuits 1121 connected in series, where a delay time corresponding to each sub-delay circuit 1121 is a first time, an initial phase difference between a channel clock signal and a first data signal is a second time, and a preset number is associated with the first time and the second time; specifically, the preset number may be a ratio of the second time to the first time.
Different from the prior art, the embodiment provides a serial flash memory controller, where the adjusting delay circuit 112 adjusts the delay time of the channel clock signal or the first data signal according to the phase difference adjusting signal obtained by the register 111, and controls the phase difference between the channel clock signal and the first data signal within a first preset range; the phase difference between the channel associated clock signal and the first data signal can be adjusted, and the first data signal can be accurately sampled at the effective edge of the channel associated clock signal, so that the stable transmission of the data signal is realized.
Referring to fig. 2, fig. 2 is a schematic structural diagram of another embodiment of a serial flash memory controller provided in the present application, the serial flash memory controller further including: clock source 21, the processing path includes: a first path 22 and a second path 23, the delay circuit includes a first delay circuit 221 and a second delay circuit 231.
The clock source 21 is used to generate standard clock signals, and high-speed clocks can be used to generate clock signals with different phases.
The first path 22 is connected to the clock source 21, and configured to generate a channel associated clock signal according to the standard clock signal, and transmit the channel associated clock signal to an external device (not shown in the figure), where the channel associated clock signal is a signal obtained by delaying the clock signal by a first preset delay time, and the first preset delay time includes a time for transmitting the standard clock signal to the external device.
Further, the first passage 22 includes: and the first delay circuit 221, where the first delay circuit 221 is connected to the clock source 21, and is configured to receive the first phase difference adjustment signal, and delay the associated clock signal by a third preset delay time according to the first phase difference adjustment signal, where the third preset delay time is a difference between a second preset delay time and the first preset delay time, and the second preset delay time includes a time for transmitting the data signal to be transmitted to the external device.
The second path 23 is connected to the clock source 21, and is configured to generate a first data signal according to a data signal to be sent, and send the first data signal to an external device; the first data signal is the same as the information contained in the data signal to be transmitted, and the first data signal is a signal obtained by delaying the data signal to be transmitted by a second preset delay time.
Further, the second passage 23 includes: the second delay circuit 231 is configured to receive the second phase difference adjustment signal, and delay the first data signal by a fourth preset delay time according to the second phase difference adjustment signal, where the fourth preset delay time is a difference between the first preset delay time and the second preset delay time.
The first flip-flop 232 is connected to the clock source 21 and the second delay circuit 231, respectively, and is configured to generate a first data signal according to a first clock signal and a data signal to be transmitted, where the first clock signal is a signal obtained by delaying a standard clock signal by a fifth preset delay time.
The registers include a first register 2211 and a second register 2311, and the trim delay circuit includes a first trim delay circuit 2212 and a second trim delay circuit 2312; the first delay circuit 221 includes a first register 2211 and a first adjusted delay circuit 2212, the first adjusted delay circuit 2212 includes a plurality of first sub-delay circuits 22121 connected in series; the second delay circuit 231 includes a second register 2311 and a second adjusted delay circuit 2312, and the second adjusted delay circuit 2312 includes a plurality of second sub-delay circuits 23121 connected in series.
The first phase difference adjustment signal is used to indicate that the associated clock signal passes through a preset number of first sub-delay circuits 22121, where the preset number is a ratio of a third preset delay time to the first time; the second phase difference adjustment signal is used to indicate that the first data signal passes through a predetermined number of second sub-delay circuits 23121, wherein the predetermined number is a ratio of the fourth predetermined delay time to the first time.
With reference to fig. 2, the serial flash memory controller further includes a third path 24, the third path 24 is connected to the clock source 21, and the third path 24 includes a third delay circuit 241 and a second flip-flop 242 connected to each other.
The third delay circuit 241 is respectively connected to the second flip-flop 242 and the clock source 21, and includes a third register 2411 and a third adjusting delay circuit 2412 connected to each other; the third register 2411 is configured to receive a third phase difference adjustment signal, and the third adjustment delay circuit 2412 is configured to delay the second clock signal according to the third phase difference adjustment signal, so that a phase difference between the delayed data signal to be received and the delayed second clock signal is within a second preset range; the second preset range may be the same as the first preset range, and the second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time.
The second flip-flop 242 is configured to receive a data signal to be received sent by an external device, and generate a second data signal according to the delayed second clock signal and the data signal to be received.
Further, the third adjusting delay circuit 2412 includes a plurality of third sub-delay circuits 24121 connected in series, and the third phase difference adjusting signal is used to indicate that the data signal to be received passes through a preset number of the third sub-delay circuits 24121.
In a specific embodiment, as shown in fig. 3, each delay circuit further includes a selector, an output terminal of each sub-delay circuit is connected to the selector, the selector is connected to the register, the register can receive the phase difference adjustment signal, and the selector is configured to determine the number of the connected sub-delay circuits according to an output of the register.
The delay value of each sub-delay circuit is substantially the same under the same condition (under the same temperature or voltage), and the sub-delay circuit is composed of a certain number and types of circuit units, such as inverters or buffers (not shown). Through configuring the corresponding register, the number of the sub-delay circuits through which the signals pass can be selected, thereby realizing different delay value settings. When the register allocation value is 0, it indicates that the delay circuit (including the first to third delay circuits 221 to 241) has the minimum delay value without passing through any of the sub-delay circuits, and the larger the register allocation value is, the larger the number of sub-delay circuits through which the signal passes is, and the larger the delay value of the corresponding delay circuit is.
For each sub-delay circuit, the higher the temperature, the larger the delay value, and the higher the voltage, the smaller the delay value. When the temperature is highest and the voltage is lowest, the sub-delay circuit has the largest delay value; when the temperature is lowest and the voltage is highest, the sub-delay circuit has the smallest delay value.
Based on the sensitivity of each sub-delay circuit to temperature and voltage, STA (Static Timing Analysis) Analysis is usually used to obtain a maximum delay value, a typical delay value, and a minimum delay value.
In this embodiment, the phase difference between the channel-associated clock signal and the first data signal is adjusted by the first delay circuit 221 and the second delay circuit 231, so that the first data signal is sampled at the rising edge of the channel-associated clock signal, and the delay time of the second clock signal is adjusted by the third delay circuit 241 according to the channel-associated clock signal, so that the data signal to be received can be sampled at the delayed rising edge of the second clock signal, thereby realizing stable transmission of the data signal.
In a specific embodiment, as shown in fig. 4, the clock source 21 is used for generating the standard clock signal CLK, and it can also be used for generating other required clock signals, the delay time of the slave clock signal SCK from the standard clock signal CLK is T1_ a + T2_ a + T3_ a + T4_ a, wherein the delay time generated by the first delay circuit 221 is T2_ a. The MOSI signal, which is a data signal transmitted from the serial flash controller 20 to the serial flash chip 25, is generated by the D flip-flop 232 driven by the first clock signal CLK1, and the phase relationship of the first clock signal CLK1 and the standard clock signal CLK is fixed regardless of the delay factor.
The delay times T2_ a and T2_ B of the first delay circuit 221 and the second delay circuit 231 are selected in such a manner that a delay value of T2_ a is selected as small as possible in the case where the delay difference between the slave clock signal SCK and the MOSI signal is minimum.
The external serial flash memory chip 25 samples the MOSI signal line using the rising edge of the slave clock signal clock, and in order to achieve the best anti-interference performance and the fastest transmission speed, the rising edge of the slave clock signal should be located in the middle of the data of the MOSI signal line, as shown in fig. 5.
In order to achieve optimal sampling, the relationship between the different delays needs to satisfy the following formula:
T1_A+T2_A+T3_A+T4_A＝T1_B+T2_B+T3_B+T4_B+Tdq
where Tdq is the delay of D flip-flop 232, Tdq is usually small and can be selectively ignored. The PCB delay times T4_ a and T4_ B can be estimated according to the trace length and the dielectric constant of the PCB after the PCB is designed, and the values of T1_ A, T3_ A, T1_ B and T3_ B can be obtained by STA analysis.
After receiving the associated clock signal clock SCK, the external serial flash memory chip 25 transmits the MISO signal to the serial flash memory controller 20 after a certain processing delay, and the serial flash memory controller 20 samples the MISO signal using the second clock signal of the sampling clock generated by the standard clock signal CLK.
Similar to the MOSI signal, the rising edge of the second clock signal should be in the middle of the MISO signal line for best immunity and fastest transmission speed, as shown in fig. 6.
In order to achieve optimal sampling, the relationship between the different delays needs to satisfy the following formula:
T1_A+T2_A+T3_A+T4_A+Tproc+T4_C+T3_C＝T1_C+T2_C-TSCK/2
where Tproc is the processing time of the external serial flash memory chip 25, and is typically available from data manuals; the PCB delay clock T4_ C can be estimated according to the trace length and the dielectric constant of the PCB, and the values of T1_ C, T2_ C and T3_ C can be obtained by STA analysis.
Based on the relationship between the associated clock signal SCK and the MOSI signal, the delay value T2_ a of the first delay circuit 221 is obtained, and then the delay value T2_ C of the third delay circuit 241 can be calculated according to the above formula.
From the above analysis, it can be known that by introducing 3 delay circuits, it can be ensured that the MOSI signal and the MISO signal are always sampled at the optimal sampling point, and the serial flash memory controller 20 provided in this embodiment can be applied to an integrated circuit that utilizes an SPI bus to implement serial flash memory access.
Under the conditions of different environmental temperatures and working voltages, in order to ensure that the access speed of the serial flash memory is not influenced, a delay circuit is inserted into a path of the associated clock signal SCK and the MOSI signal in the serial flash memory controller 20, so that the delay difference that the associated clock signal SCK and the MOSI signal reach the corresponding port of the external serial flash memory chip 25 is changed. In addition, by inserting the third delay circuit 241 to adjust the sampling clock phase of the MISO signal, it is ensured that the MISO signal can be correctly sampled certainly. In addition, the delay value of each delay circuit can be selected through an independent register, and the current SPI bus speed, the ambient temperature, the working voltage and the PCB wiring can be comprehensively considered, so that the most appropriate delay value is selected.
Referring to fig. 1 and 7, fig. 7 is a schematic flowchart illustrating an embodiment of a method for adjusting a sampling phase according to the present application, the method is applied to a serial flash memory controller, the serial flash memory controller includes a processing path 10, the processing path 10 includes a delay circuit 11, the delay circuit 11 includes a register 111 and an adjusting delay circuit 112 connected to the register, the method includes:
step 71: the register receives the phase difference adjustment signal.
The adjusting delay circuit 112 includes a plurality of sub-delay circuits 1121 connected in series, and the delay time corresponding to each sub-delay circuit 1121 is a first time; the phase difference adjustment signal is used to indicate that the associated clock signal or the first data signal passes through the predetermined number of sub-delay circuits 1121.
Step 72: the adjusting delay circuit delays the associated clock signal or the first data signal according to the phase difference adjusting signal, so that the phase difference between the delayed associated clock signal and the first data signal is within a first preset range.
The channel associated clock signal is a clock signal generated by the serial flash controller, the clock signal is sent to the SPI slave device, the first data signal can be an MOSI signal, and accurate sampling of the first data signal is realized according to the channel associated clock signal under the conditions of different environmental temperatures and working voltages in order to ensure that the access speed of the serial flash memory is not affected, and the accurate sampling can be realized by adjusting the phase difference between the channel associated clock signal and the first data signal; the initial phase difference between the associated clock signal and the first data signal is a second time, and the preset number is associated with the first time and the second time.
The operator may obtain the phase difference between the associated clock signal and the first data signal by measurement, and in a specific embodiment, the phase difference may be obtained by analyzing the delay of each node in the circuit by using static timing analysis. After acquiring the phase difference between the channel associated clock signal and the first data signal, an operator sends an adjustment instruction to the register 111 according to the phase difference to adjust the delay time of the channel associated clock signal or the first data signal, so that the first data signal can be sampled at the effective edge of the channel associated clock signal, that is, the phase difference between the channel associated clock signal and the first data signal is within a first preset range; the delay time of the channel associated clock signal or the first data signal is set, so that the delay difference of the channel associated clock signal and the first data signal reaching the corresponding port of the external slave equipment is changed.
In this embodiment, the delay time of the channel associated clock signal or the first data signal is adjusted according to the phase difference adjustment signal, so that the phase difference between the channel associated clock signal and the first data signal is within a first preset range; the phase difference between the channel associated clock signal and the first data signal can be adjusted, and the first data signal can be accurately sampled at the effective edge of the channel associated clock signal, so that the stable transmission of the data signal is realized.
Referring to fig. 2 and 8, fig. 8 is a flowchart illustrating another embodiment of a method for adjusting a sampling phase according to the present disclosure, in which the registers include a first register 2211, a second register 2311 and a third register 2411, the adjusting delay circuit includes a first adjusting delay circuit 2212, a second adjusting delay circuit 2312 and a third adjusting delay circuit 2412, the first adjusting delay circuit 2212 includes a plurality of first sub-delay circuits 22121 connected in series, the second adjusting delay circuit 2312 includes a plurality of second sub-delay circuits 23121 connected in series, and the third adjusting delay circuit 2412 includes a plurality of third sub-delay circuits 24121 connected in series; the method comprises the following steps:
step 81: a first trigger in the serial flash memory controller generates a first data signal according to a first clock signal and a data signal to be sent.
The data signal to be sent is a data signal that the serial flash controller prepares to send to the SPI slave device, the first clock signal is a signal after the standard clock signal is delayed by a fifth preset delay time, and the standard clock signal is a signal generated by the clock source 21 in the serial flash controller.
The first clock signal and the data signal to be transmitted are input into the first flip-flop 232, the first flip-flop 232 samples the data signal to be transmitted at a rising edge of the first clock signal, so as to obtain a first data signal, where the first data signal is a MOSI signal, the first data signal is a signal obtained by delaying the data signal to be transmitted by a second preset delay time, and the second preset delay time includes a time for transmitting the data signal to be transmitted to an external device.
Step 82: the register receives the phase difference adjustment signal.
Step 83: the first register receives a first phase difference adjusting signal, and the first adjusting delay circuit delays the associated clock signal by a third preset delay time according to the first phase difference adjusting signal.
The associated clock signal is a signal obtained by delaying a standard clock signal by a first preset delay time, the standard clock signal is a signal generated by the clock source 21, and the first preset delay time includes a time for transmitting the standard clock signal to an external device.
The first phase difference adjustment signal is used to indicate that the associated clock signal passes through a predetermined number of first sub-delay circuits 22121, the third predetermined delay time is a difference between the second predetermined delay time and the first predetermined delay time, and the predetermined number is a ratio of the third predetermined delay time to the first time.
Step 84: the second register receives a second phase difference adjusting signal, and the second adjusting delay circuit delays the first data signal by a fourth preset delay time according to the second phase difference adjusting signal.
The fourth predetermined delay time is a difference between the first predetermined delay time and the second predetermined delay time, the second phase difference adjustment signal is used to indicate that the first data signal passes through a predetermined number of the second sub-delay circuits 23121, and the predetermined number is a ratio of the fourth predetermined delay time to the first time.
Step 85: and the serial flash memory controller transmits the delayed channel associated clock signal and the first data signal to the external equipment, or transmits the channel associated clock signal and the delayed first data signal to the external equipment.
If the second preset delay time is greater than the first preset delay time, it indicates that the channel associated clock signal is ahead of the first data signal, and in order to accurately sample the first data signal at the rising edge of the channel associated clock signal, the channel associated clock signal is delayed by a third preset delay time.
If the second predetermined delay time is less than or equal to the first predetermined delay time, it indicates that the associated clock signal lags behind the first data signal, and the first data signal is delayed by a fourth predetermined delay time in order to accurately sample the first data signal at the rising edge of the associated clock signal.
In a specific embodiment, the rising edge of the channel-associated clock signal may correspond to a middle position of the first data signal, i.e., the phase difference between the channel-associated clock signal and the first data signal is 0, as shown in fig. 5.
After delaying the channel associated clock signal or the first data signal, the channel associated clock signal and the first data signal are transmitted to an external device, which may be an external slave device.
Step 86: the second trigger receives a data signal to be received sent by the external equipment.
The serial flash memory controller samples the first data signal at the rising edge of the associated clock signal, and also receives a data signal to be received sent by an external device, wherein the data signal to be received may be a MISO signal.
Step 87: the third register receives a third phase difference adjustment signal.
The third phase difference adjustment signal is used to indicate that the data signal to be received passes through a predetermined number of third sub-delay circuits 24121.
Step 88: the third adjusting delay circuit delays the second clock signal according to the third phase difference adjusting signal, so that the phase difference between the delayed data signal to be received and the delayed second clock signal is within a second preset range.
Step 89: and the serial flash controller generates a second data signal according to the delayed second clock signal and the data signal to be received.
And the second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time, and in order to accurately sample the signal to be received at the rising edge of the second clock signal, the delay time of the second clock signal is adjusted according to the associated clock signal, so that the phase difference between the data signal to be received and the delayed second clock signal is within a second preset range.
In a specific embodiment, the rising edge of the second clock signal may correspond to the middle position of the data signal to be received, i.e. the phase difference between the second clock signal and the data signal to be received is 0, as shown in fig. 6.
After the phase difference between the second clock signal and the data signal to be received is adjusted, the data signal to be received and the delayed second clock signal are input to the second flip-flop 242 to generate a second data signal, which is a signal after the delay of the signal to be received and contains the same data information.
In this embodiment, the phase difference between the channel associated clock signal and the first data signal is adjusted to sample the first data signal at the rising edge of the channel associated clock signal, and the delay time of the second clock signal is adjusted according to the channel associated clock signal, so that the data signal to be received can be sampled at the delayed rising edge of the second clock signal, thereby realizing stable transmission of the data signal.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules or units is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.
Claims (13)
1. A serial flash memory controller comprising a processing path including a delay circuit, the delay circuit comprising:
a register for receiving the phase difference adjustment signal;
the adjustment delay circuit is connected with the register and used for delaying a channel associated clock signal or a first data signal according to the phase difference adjustment signal so as to enable the phase difference between the channel associated clock signal and the first data signal to be within a first preset range;
the adjusting delay circuit comprises a plurality of sub-delay circuits connected in series, the delay time corresponding to each sub-delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, the phase difference adjusting signal is used for indicating that the associated clock signal or the first data signal passes through a preset number of the sub-delay circuits, and the preset number is associated with the first time and the second time.
2. The serial flash memory controller according to claim 1, further comprising a clock source for generating a standard clock signal; the processing path includes:
the first path is connected with the clock source and used for generating a channel associated clock signal according to the standard clock signal and transmitting the channel associated clock signal to external equipment; the associated clock signal is a signal obtained by delaying the standard clock signal by a first preset delay time, wherein the first preset delay time includes a time for transmitting the standard clock signal to an external device.
The second channel is connected with the clock source and used for generating the first data signal according to a data signal to be sent and sending the first data signal to the external equipment; the first data signal is the same as information contained in the data signal to be transmitted, the first data signal is a signal obtained by delaying the data signal to be transmitted by a second preset delay time, and the second preset delay time includes the time for transmitting the data signal to be transmitted to the external device.
3. The serial flash memory controller of claim 2, wherein the delay circuit comprises a first delay circuit and a second delay circuit,
the first path comprises the first delay circuit and is used for receiving a first phase difference adjusting signal and delaying the associated clock signal by a third preset delay time according to the first phase difference adjusting signal; the third preset delay time is the difference value between the second preset delay time and the first preset delay time;
the second path comprises a second delay circuit, and is used for receiving a second phase difference adjusting signal and delaying the first data signal by a fourth preset delay time according to the second phase difference adjusting signal; and the fourth preset delay time is the difference value between the first preset delay time and the second preset delay time.
4. The serial flash memory controller of claim 3,
the register comprises a first register and a second register, and the adjusting delay circuit comprises a first adjusting delay circuit and a second adjusting delay circuit; the first delay circuit comprises the first register and the first adjusted delay circuit, the first adjusted delay circuit comprising a plurality of first sub-delay circuits connected in series; the second delay circuit comprises the second register and the second adjusted delay circuit, the second adjusted delay circuit comprising a plurality of second sub-delay circuits connected in series; the first phase difference adjustment signal is used for indicating that the associated clock signal passes through the first delay sub-circuits in the preset number, wherein the preset number is a ratio of the third preset delay time to the first time; the second phase difference adjustment signal is used for indicating that the first data signal passes through the second sub-delay circuits in the preset number, wherein the preset number is a ratio of the fourth preset delay time to the first time.
5. The serial flash memory controller of claim 4,
the second path further includes a first flip-flop, and the first flip-flop is connected to the clock source and the second delay circuit, respectively, and is configured to generate the first data signal according to a first clock signal and the to-be-transmitted data signal;
the first clock signal is a signal obtained by delaying the standard clock signal by a fifth preset delay time.
6. The serial flash memory controller of claim 2, further comprising a third path comprising:
the third delay circuit is connected with the clock source and comprises a third register and a third adjusting delay circuit; the third register is configured to receive a third phase difference adjustment signal, and the third adjustment delay circuit is configured to delay a second clock signal according to the third phase difference adjustment signal, so that a phase difference between the delayed data signal to be received and the delayed second clock signal is within a second preset range, where the second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time;
the second trigger is connected with the third delay circuit and used for receiving a data signal to be received sent by external equipment and generating a second data signal according to the delayed second clock signal and the data signal to be received;
the third adjusting delay circuit comprises a plurality of third sub-delay circuits connected in series, and the third phase difference adjusting signal is used for indicating that the data signal to be received passes through the preset number of third sub-delay circuits.
7. The serial flash memory controller of claim 1,
the delay circuit further comprises a selector, the output end of each sub-delay circuit is connected with the selector, the selector is connected with the register, and the selector is used for determining the number of the connected sub-delay circuits according to the output of the register.
8. A method for adjusting sampling phase, applied to a serial flash memory controller, the serial flash memory controller comprising a processing path including a delay circuit, the delay circuit including a register and an adjusting delay circuit connected to the register, the method comprising:
the register receives a phase difference adjusting signal;
the adjusting delay circuit delays a channel associated clock signal or a first data signal according to the phase difference adjusting signal, so that the phase difference between the channel associated clock signal and the first data signal is within a first preset range;
the adjusting delay circuit comprises a plurality of sub-delay circuits connected in series, the delay time corresponding to each sub-delay circuit is a first time, the initial phase difference between the associated clock signal and the first data signal is a second time, the phase difference adjusting signal is used for indicating that the associated clock signal or the first data signal passes through a preset number of the sub-delay circuits, and the preset number is associated with the first time and the second time.
9. The method of adjusting sampling phase of claim 8,
the associated clock signal is a signal obtained by delaying a standard clock signal by a first preset delay time, wherein the first preset delay time comprises the time for transmitting the standard clock signal to external equipment; the first data signal is a signal obtained by delaying a data signal to be transmitted by a second preset delay time; the standard clock signal is a signal generated by a clock source in the serial flash controller, and the second preset delay time includes a time for transmitting the data signal to be transmitted to the external device.
10. The method of adjusting a sampling phase of claim 9, wherein the register comprises a first register and a second register, the trim delay circuit comprises a first trim delay circuit and a second trim delay circuit, the first trim delay circuit comprises a plurality of first sub-delay circuits connected in series, and the second trim delay circuit comprises a plurality of second sub-delay circuits connected in series; the step of delaying a channel associated clock signal or a first data signal by the adjusting delay circuit according to the phase difference adjusting signal so that a phase difference between the channel associated clock signal and the first data signal is within a first preset range includes:
the first register receives a first phase difference adjusting signal, wherein the first phase difference adjusting signal is used for indicating that the associated clock signal passes through the first sub-delay circuits with the preset number; the first adjusting delay circuit delays the associated clock signal by a third preset delay time according to the first phase difference adjusting signal, wherein the third preset delay time is a difference value between the second preset delay time and the first preset delay time, and the preset number is a ratio of the third preset delay time to the first time; or
The second register receives a second phase difference adjustment signal, wherein the second phase difference adjustment signal is used for indicating that the first data signal passes through the second sub-delay circuits with the preset number; the second adjusting delay circuit delays the first data signal by a fourth preset delay time according to the second phase difference adjusting signal, wherein the fourth preset delay time is a difference value between the first preset delay time and the second preset delay time, and the preset number is a ratio of the fourth preset delay time to the first time.
11. The method of adjusting a sampling phase of claim 9, wherein the step of the register receiving a phase difference adjustment signal is preceded by the steps of:
a first trigger in the serial flash memory controller generates the first data signal according to a first clock signal and the data signal to be sent;
the first clock signal is a signal obtained by delaying the standard clock signal by a fifth preset delay time.
12. The method of adjusting sampling phase of claim 8, further comprising:
and the serial flash memory controller sends the delayed channel associated clock signal and the first data signal to external equipment, or sends the channel associated clock signal and the delayed first data signal to the external equipment.
13. The method of adjusting a sampling phase of claim 12, wherein the register further comprises a third register, wherein the trim delay circuit further comprises a third trim delay circuit comprising a plurality of third sub-delay circuits connected in series, and wherein the method further comprises:
the second trigger receives a data signal to be received sent by the external equipment;
the third register receives a third phase difference adjusting signal, wherein the third phase difference adjusting signal is used for indicating that the data signals to be received pass through the preset number of third sub-delay circuits;
the third adjusting delay circuit delays a second clock signal according to the third phase difference adjusting signal, so that the phase difference between the delayed data signal to be received and the delayed second clock signal is within a second preset range;
the serial flash controller generates a second data signal according to the delayed second clock signal and the data signal to be received;
and the second clock signal is a signal obtained by delaying the standard clock signal by a sixth preset delay time.
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