CN111696617A - Non-volatile memory read data speed test circuit and test method - Google Patents
Non-volatile memory read data speed test circuit and test method Download PDFInfo
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- CN111696617A CN111696617A CN202010465009.5A CN202010465009A CN111696617A CN 111696617 A CN111696617 A CN 111696617A CN 202010465009 A CN202010465009 A CN 202010465009A CN 111696617 A CN111696617 A CN 111696617A
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
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Abstract
The application relates to the technical field of semiconductor integrated circuit design and test, in particular to a circuit and a method for testing the data reading speed of a nonvolatile memory. The test circuit comprises a read signal path, and the output end of the read signal path is connected with the read end of the nonvolatile memory; the read signal path can output a read signal to the read signal input end according to the test clock signal; an address path including a first address unit for outputting a timing-balanced address signal and a timing balance selector for selecting and outputting an output signal of the first address unit; and the comparison output path is connected with the output end of the non-volatile memory at the comparison end and used for comparing the output data of the output end of the non-volatile memory with preset comparison data and outputting a comparison result, so that the problem of deviation in measurement and calculation of the time TAA of reading data by the non-volatile memory in the related technology can be solved, and the accuracy of the TAA test can be improved.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit design and test, in particular to a nonvolatile memory read data speed test circuit and a nonvolatile memory read data speed test method.
Background
The memory is the main medium for storing data in the computer, and the read-write speed of the memory greatly influences the working speed of the computer. Particularly, in recent years, with the rapid development of internet technologies such as cloud computing, the demand for memory read/write speed has been increasing.
For a non-volatile memory, the general measurement method of the reading speed is as follows: by continuously adjusting the period of an external clock of the reading operation of the memory, the critical clock period which can be accurately read by the memory is used as the time for reading data by the nonvolatile memory.
However, this method causes a problem of difficult signal balance, which results in a deviation of the final read non-critical clock cycle, and once the critical clock cycle including the deviation of the final read non-critical clock cycle is used as the time for reading data, the deviation of the time for reading data is caused.
Disclosure of Invention
The application provides a circuit and a method for testing data reading speed of a non-volatile memory, which can solve the problem of deviation in measurement and calculation of data reading time of the non-volatile memory in the related technology.
As a first aspect of the present application, there is provided a circuit for testing data reading speed of a nonvolatile memory, the nonvolatile memory including a read signal input terminal, an address signal input terminal, and an output terminal, the circuit comprising:
the output end of the reading signal path is connected with the reading end of the non-volatile memory; in a test mode, the read signal path can output a read signal to the read signal input end according to a test clock signal;
an address path including a first address unit for outputting a timing-balanced address signal and a timing balance selector for selecting and outputting an output signal of the first address unit;
and the comparison end of the comparison output path is connected with the output end of the non-volatile memory and is used for comparing the output data of the output end of the non-volatile memory with preset comparison data and outputting a comparison result.
Optionally, the first address unit includes a first address register, a first address logic operator, and an address latch;
when the first address register receives the current rising edge of the test clock signal, the first address register outputs the current address to the first address logic arithmetic unit;
the current address is transmitted to the address latch through the first address logic arithmetic unit and is latched in the address latch; on a trailing rising edge of the test clock signal, the address latch outputs a current address to the timing balance selector.
Optionally, the address path further comprises a second address unit for outputting an address signal that is not time-sequence balanced;
the timing balance selector is used for selecting between the output signal of the first address unit or the output signal of the second address unit and outputting a corresponding output signal.
Optionally, the second address unit comprises a second address register and a second address logical operator;
when the second address register receives the current rising edge of the test clock signal, the second address register outputs the current address to a second address logic arithmetic unit;
the current address is transmitted to the timing balance selector through the second address logic operator.
Optionally, the address path further includes: a first test mode selector;
the first test mode selector is used for selecting and outputting an output signal of the timing balance selector.
Optionally, the read signal path includes: a read signal register and a read signal logic operator;
and the reading signal register outputs a reading signal to the reading signal logic arithmetic unit when receiving the rising edge of the test clock signal.
Optionally, the read signal path further comprises: a second test mode selector for selecting and outputting an output signal of the read signal logic operator.
Optionally, the comparing output path includes: an output latch, a comparator and a comparison result register;
the input end of the output latch is the comparison end of the comparison output path, and the clock end of the output latch is connected with the test clock signal;
the comparator is preset with comparison data, the input end of the comparator is connected with the output end of the output latch, and the comparator is used for comparing the output data of the output latch with the preset comparison data and outputting a comparison result, and the comparison result register is used for registering the comparison result.
As a second aspect of the present application, a method for testing the read data speed of a nonvolatile memory is provided, where the method is based on a circuit for testing the read data speed of the nonvolatile memory according to the first aspect of the present application, and includes at least the following steps:
providing a test clock signal having a specific period;
sending a current rising edge of the test clock signal;
after the delay, the read signal input end of the nonvolatile memory receives the current rising edge pulse output by the read signal path;
sending a trailing rising edge that follows the current rising edge;
after the delay, the read signal input end of the nonvolatile memory receives the read signal path and outputs a pulse at a rear rising edge; the address signal input end of the non-volatile memory receives the current address output by the address path;
under the action of the pulse of the back rising edge of the reading signal, the non-volatile memory outputs corresponding output data to the comparison end of the comparison output path according to the current address of the address signal;
the comparison output path compares the output data output by the non-volatile memory with preset comparison data and outputs a comparison result;
by continuously shortening the period of the test clock signal, a critical period that can ensure the consistency of the comparison results is determined.
Optionally, at least one rising edge of the test clock signal is passed from sending a current rising edge of the test clock signal to sending a trailing rising edge of the current rising edge.
The technical scheme at least comprises the following advantages: under the action of a test clock signal, a read signal path generates a rising edge pulse of a read signal, and the rising edge pulse of the read signal can enable the nonvolatile memory to output data to a comparison output path according to an address in a received address signal when the rising edge pulse of the read signal occurs; the comparison output path compares the received output data with preset comparison data under the action of the test clock signal, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable a comparison result to be between reading error and reading accuracy is determined, and the critical period is used as the time for reading data of the nonvolatile memory, so that the accuracy of the TAA test can be improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a circuit for testing the read data speed of a nonvolatile memory according to an embodiment of the present disclosure;
FIG. 2 is a timing diagram of read signals and address signals in an embodiment of the present application;
FIG. 3 is a circuit for testing the read data speed of a nonvolatile memory according to an embodiment of the present application;
FIG. 4 is a timing diagram of a read signal, a first address register output signal, and an address signal in an embodiment of the present application;
FIG. 5 is a block diagram of another method for reading data speed of a nonvolatile memory according to an embodiment of the present application;
fig. 6 is a signal timing chart in the embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, a circuit for testing the READ data speed of a non-volatile memory NVM according to an embodiment of the present application is shown, wherein the non-volatile memory NVM includes a READ signal input READ, an address signal input ADDR and an output DOUT; the reading data speed test circuit suitable for the nonvolatile memory NVM comprises:
a READ signal path 11, an output end of the READ signal path 11 is connected to a READ signal input end READ of the non-volatile memory NVM; in the test mode, the READ signal path 11 is capable of outputting a READ signal to the READ signal input READ according to the test clock signal CLK. The reading signal comprises a rising edge pulse and a falling edge pulse which are alternately generated, and the rising edge pulse of the reading signal can excite the nonvolatile memory NVM to carry out reading operation.
An address path 12, an output terminal of the address path 12 is connected to an address signal input terminal ADDR of the non-volatile memory NVM, the address path 12 includes a first address unit 121 for outputting a timing balanced address signal and a timing balance selector 123, and the timing balance selector 123 is used for selecting and outputting an output signal of the first address unit 121. The address signal includes a plurality of data addresses, and the time-sequence balanced address signal refers to the time when the address signal starts to reach the address signal input terminal ADDR of the non-volatile memory NVM, and is the same as the time when the rising edge pulse of the read signal can excite the non-volatile memory NVM to perform the read operation.
As shown in fig. 2, the address signals include an address a0, an address a1, and an address a2, a first rising edge pulse of the READ signal reaches the READ signal input terminal READ of the nonvolatile memory after a first rising edge of the test clock signal CLK passes a first delay time T1 from the time Q0, a first rising edge pulse of the READ signal reaches the READ signal input terminal READ of the nonvolatile memory after a second delay time T2, i.e., at the time Q1, passes a third rising edge of the test clock signal CLK, a first address a0 of the address signals reaches the address signal input terminal ADDR of the nonvolatile memory, and a second rising edge pulse of the READ signal reaches the READ signal input terminal READ of the nonvolatile memory at the time Q1, the address signals shown in fig. 2 are time-balanced address signals, and start to reach the address signal input terminal ADDR of the nonvolatile memory at the same time as the rising edge pulse of the READ signal can trigger the nonvolatile memory to perform the READ operation, and this timing is the timing Q1.
And a comparison output path 13, wherein a comparison end of the comparison output path 13 is connected to the output end DOUT of the non-volatile memory NVM, and is configured to compare output data of the output end DOUT of the non-volatile memory NVM with preset comparison data, and output a comparison result from the output end TDO of the comparison output path 13. If the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong.
In summary, under the action of the test clock signal, the read signal path generates a rising edge pulse of the read signal, and the rising edge pulse of the read signal can enable the nonvolatile memory NVM to output data to the comparison output path according to the address in the received address signal when the rising edge pulse of the read signal occurs; the comparison output path compares the received output data with preset comparison data under the action of the test clock signal, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable the comparison result to be between reading error and reading accuracy is determined, and the critical period is used as the time for reading data of the nonvolatile memory NVM, so that the accuracy of the TAA test can be improved.
Referring to fig. 3, which shows another nonvolatile memory read data speed test circuit provided in the embodiment of the present application, the address path of the present embodiment further includes a second address unit 122 for outputting an address signal without timing balance on the basis of fig. 1; the control terminal of the timing balance selector 123 is connected to the TAA mode control signal TAA _ mode, and the timing balance selector 123 selects between the output signal of the first address unit 121 or the output signal of the second address unit 122 according to the TAA mode control signal TAA _ mode and outputs the corresponding output signal.
When the nonvolatile memory NVM is in a test mode, not only TAA test but also other tests are required; for other testing processes, the timing balanced address signals affect the testing structure, so the timing balanced selector 123 can be controlled to select the second address unit 122 of the address signals which are not subjected to timing balance, and the timing balanced selector 123 can be controlled to select the first address unit 121 of the address signals which are subjected to timing balance when the TAA test is required.
As shown in fig. 3, the first address unit 121 includes a first address register REG1_ ad, a first address logic operator Log1_ ad, and an address latch REG _ pl _ ad. The output terminal of the first address register REG1_ ad is connected to the input terminal of the first address logic operator Log1_ ad, the output terminal of the first address logic operator Log1_ ad is connected to the input terminal of the address latch REG _ pl _ ad, and the output terminal of the address latch REG _ pl _ ad is connected to an input terminal of the timing balance selector 123. The first address register REG1_ ad, the first address logic operator Log1_ ad, and the address latch REG _ pl _ ad cooperate to perform a timing balance function on the address signals, so that the first address unit 121 outputs the timing-balanced address signals.
As shown in FIG. 4, the address signals include address A0, address A1, address A2, and address A3. The first address register REG1_ ad outputs the current address to the first address logic operator Log1_ ad when receiving the current rising edge of the test clock signal CLK. The current address is transmitted to the address latch REG _ pl _ ad through the first address logic operator and latched in the address latch REG _ pl _ ad; at the trailing rising edge of the test clock signal CLK, the address latch REG _ pl _ ad outputs the current address to the timing balance selector. The test clock signal includes rising edges and falling edges that are alternately generated, and the trailing rising edge refers to the rising edge of the test clock signal that is generated after the occurrence of the current rising edge.
The second address unit 122 includes a second address register REG2_ ad and a second address logical operator Log2_ ad; the second address register REG2_ ad has a clock terminal connected to the test clock signal CLK, an output terminal connected to an input terminal of the second address logic operator Log2_ ad, and an output terminal connected to another input terminal of the timing balance selector 123. The second address register REG2_ ad outputs the current address to the second address logic operator Log2_ ad upon receiving the current rising edge of the test clock signal CLK; the current address is transmitted to the timing balance selector 123 via the second address logic operator Log2_ ad.
The address path 12 further comprises: a first test mode selector 124; an input terminal of the first test mode selector 124 is connected to the output terminal of the timing balance selector 123, and a control terminal thereof is connected to the test mode control signal test _ mode, for selecting and outputting the output signal of the timing balance selector 123 according to the test mode control signal test _ mode.
The read signal path 12 includes: a read signal register REG _ re, a read signal logic operator Log _ re, and a second test mode selector 111; the clock end of the READ signal register REG _ re is connected to the test clock signal CLK, the output end is connected to the READ signal logic operator Log _ re, the output end of the READ signal logic operator Log _ re is connected to an output end of the second test mode selector 111, the control end of the second test mode selector 111 is connected to the test mode control signal test _ mode, the READ signal register REG _ re outputs a READ signal to the READ signal logic operator Log _ re when receiving a rising edge of the test clock signal CLK, the READ signal logic operator Log _ re outputs a signal to the second test mode selector 111, and the second test mode selector 111 controls the READ signal to be output to the READ signal input end READ of the non-volatile memory NVM according to the test mode control signal test _ mode.
The comparison output path 13 includes: an output latch REG1_ co, a comparator COMPARE, and a comparison result register REG2_ co; the input terminal of the output latch REG1_ co is the opposite terminal of the comparison output path 13 and is used for connecting the output terminal DOUT of the non-volatile memory NVM, the clock terminal of the output latch REG1_ co is connected to the test clock signal CLK, the output terminal of the output latch REG1_ co is connected to the input terminal of the comparator COMPARE, the output terminal of the comparator COMPARE is connected to the input terminal of the comparison result register REG2_ co, and the output terminal of the comparison result register REG2_ co is the output terminal TDO of the comparison output path 13.
The comparator COMPARE is preset with comparison data for comparing the output data of the output latch REG1_ co with the preset comparison data and outputting a comparison result, and the comparison result register REG2_ co is used for registering the comparison result.
In summary, under the action of the test clock signal, the read signal path generates a rising edge pulse of the read signal, and the rising edge pulse of the read signal can enable the nonvolatile memory NVM to output data to the comparison output path according to the address in the received address signal when the rising edge pulse of the read signal occurs; the comparison output path compares the received output data with preset comparison data under the action of the test clock signal, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable the comparison result to be between reading error and reading accuracy is determined, and the critical period is used as the time for reading data of the nonvolatile memory NVM, so that the accuracy of the TAA test can be improved.
Referring to fig. 5, another method for testing the read data speed of the non-volatile memory according to the embodiment of the present application is shown, and the method is based on the read data speed test circuit of the non-volatile memory shown in any one of fig. 1 and fig. 3, as shown in fig. 6, the method at least includes the following steps:
step 501: a test clock signal CLK having a certain period is provided.
Step 502: at time Q2, the current rising edge C1 of the test clock signal CLK is sent.
Step 503: the READ signal path sends a current rising edge pulse R1 according to the current rising edge C1, and after a first delay time T1, i.e., at the time of Q3, the READ signal input terminal READ of the non-volatile memory receives the READ signal path and outputs a current READ signal.
The first address register REG1_ ad in the address path generates the current address A0 on the current rising edge C1, and the address latches of the address path latch the current address A0 waiting on the following rising edge C2.
Step 504: at time Q4, when a trailing rising edge C2 is sent after the current rising edge C1, the trailing rising edge C2 is illustratively located the second rising edge after the current rising edge C1.
Step 505: the READ signal path sends a pulse R2 at a trailing rising edge C2, and after a first delay time T1, i.e., at time Q1, the READ signal input READ of the non-volatile memory receives the pulse R2 at the trailing rising edge. The first delay time T1 is the time from the time when the trailing rising edge C2 is asserted to the time before the non-volatile memory receives the trailing rising edge pulse R2.
The address latch of the address path releases the current address a0 latched therein according to the rising edge C2, and receives the current address AO output by the address path at the address signal input ADDR of the nonvolatile memory after the second delay time T1, i.e., at the time of Q1, and after the first delay time T2, i.e., at the time of Q1. Wherein the second delay time T2 is the time from when the trailing rising edge C2 is issued until the non-volatile memory receives the current address AO.
The first delay time T1 is equal to the second delay time T2.
Step 506: under the action of the pulse R2 at the trailing rising edge of the read signal, the nonvolatile memory outputs corresponding output Data0 to the opposite end of the comparison output path at the time of Q5 according to the current address A0. It should be noted that the time TAA for reading Data is represented as the time interval between the time when the nonvolatile memory receives the output Data0 corresponding to the output at the time of the trailing rising edge pulse R2 and the current address a0 of the read signal, i.e., the time interval from the time of Q1 to the time of Q5.
Step 507: the comparison output path compares the output Data0 output by the non-volatile memory with preset comparison Data and outputs a comparison result.
After a set time T4 elapses from the time when the output Data0 is received from the output latch REG1_ co, the output latch REG1_ co outputs the output Data0 latched therein by the rising edge of the next test clock signal after the elapse of T4, i.e., the rising edge C3 received by the output latch REG1_ co. It should be noted that since there is a delay in the transmission of the test clock signal to the clock terminal of the output latch REG1_ co, i.e., the third delay time T3, the output latch REG1_ co receives the rising edge C3 with a delay of the third delay time T3 than when the rising edge C3 occurs.
Step 508: by continuously shortening the period of the test clock signal, a critical period that can ensure the consistency of the comparison results is determined.
And entering a TAA test mode under the control of a TAA mode control signal TAA _ mode, wherein the test circuit automatically scans and compares the full address data, and gradually reduces the period of an external test clock signal until a critical period that can ensure the comparison result to be consistent.
Namely, the critical period is TAA + T1-T3+ T4;
since the first delay time T1 and the second delay time T2 are equal through the timing balance, the time TAA of reading data can be calculated more accurately by the critical period, the first delay time T1, the third delay time T3, and the set time T4.
If the first delay time T1 elapsed when the nonvolatile memory receives the read signal is the same as the third delay time T3 when the output latch REG1_ co receives the test clock signal CLK, the time TAA of reading data is the difference between the critical period and the set time T4, so that the measurement deviation can be removed when the time TAA of reading data is measured according to the critical period, and the measurement accuracy of TAA is ensured. It should be explained that the first delay time T1 is the same as the third delay time T3 when the clock terminal of the output latch REG1_ co reaches timing balance with the READ signal input terminal READ of the nonvolatile memory. Alternatively, the clock terminal of the output latch REG1_ co and the READ signal input terminal READ of the nonvolatile memory are timing-balanced by setting the number of device stages and the kinds of devices in the clock path to the clock terminal of the output latch REG1_ co and the READ signal input terminal READ of the nonvolatile memory to be the same.
It is to be explained that, as shown in fig. 6, the address signals include an address a0, an address a1, an address a2, and an address A3, and the output signals include output Data0 and output Data 1. In the above embodiment, the Data0 is outputted according to the address a0 as an example, and the process of reading the corresponding Data from the nonvolatile memory according to the address under the action of the rising edge pulse of the read signal according to other addresses is the same as that described above, and is not repeated herein.
In summary, under the action of the test clock signal, the read signal path generates a rising edge pulse of the read signal, and the rising edge pulse of the read signal can enable the nonvolatile memory NVM to output data to the comparison output path according to the address in the received address signal when the rising edge pulse of the read signal occurs; the comparison output path compares the received output data with preset comparison data under the action of the test clock signal, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable the comparison result to be between reading error and reading accuracy is determined, and the critical period is used as the time for reading data of the nonvolatile memory NVM, so that the accuracy of the TAA test can be improved.
Claims (10)
1. A circuit for testing the read data speed of a non-volatile memory, wherein the non-volatile memory comprises a read signal input terminal, an address signal input terminal and an output terminal, the circuit comprising:
the output end of the reading signal path is connected with the reading end of the non-volatile memory; the read signal path can output a read signal to the read signal input end according to a test clock signal;
an address path including a first address unit for outputting a timing-balanced address signal and a timing balance selector for selecting and outputting an output signal of the first address unit;
and the comparison end of the comparison output path is connected with the output end of the non-volatile memory and is used for comparing the output data of the output end of the non-volatile memory with preset comparison data and outputting a comparison result.
2. The circuit for reading data speed of nonvolatile memory as in claim 1, wherein the first address unit comprises a first address register, a first address logic operator and an address latch;
when the first address register receives the current rising edge of the test clock signal, the first address register outputs the current address to the first address logic arithmetic unit;
the current address is transmitted to the address latch through the first address logic arithmetic unit and is latched in the address latch; on a trailing rising edge of the test clock signal, the address latch outputs a current address to the timing balance selector.
3. The non-volatile memory read data speed test circuit of claim 1, wherein the address path further comprises a second address unit for outputting an address signal that is not time-sequence balanced;
the timing balance selector is used for selecting between the output signal of the first address unit or the output signal of the second address unit and outputting a corresponding output signal.
4. The nonvolatile memory read data speed test circuit of claim 3, wherein the second address unit comprises a second address register and a second address logic operator;
when the second address register receives the current rising edge of the test clock signal, the second address register outputs the current address to a second address logic arithmetic unit;
the current address is transmitted to the timing balance selector through the second address logic operator.
5. The non-volatile memory read data speed test circuit of claim 1, wherein the address path further comprises: a first test mode selector;
the first test mode selector is used for selecting and outputting an output signal of the timing balance selector.
6. The non-volatile memory read data speed test circuit of claim 1, wherein the read signal path comprises: a read signal register and a read signal logic operator;
and the reading signal register outputs a reading signal to the reading signal logic arithmetic unit when receiving the rising edge of the test clock signal.
7. The non-volatile memory read data speed test circuit of claim 6, wherein the read signal path further comprises: a second test mode selector for selecting and outputting an output signal of the read signal logic operator.
8. The circuit for reading data speed of nonvolatile memory as claimed in claim 1, wherein the comparison output path comprises: an output latch, a comparator and a comparison result register;
the input end of the output latch is the comparison end of the comparison output path, and the clock end of the output latch is connected with the test clock signal;
the comparator is preset with comparison data, the input end of the comparator is connected with the output end of the output latch, and the comparator is used for comparing the output data of the output latch with the preset comparison data and outputting a comparison result, and the comparison result register is used for registering the comparison result.
9. A method for testing the reading data speed of a nonvolatile memory, which is based on the reading data speed testing circuit of the nonvolatile memory as claimed in any one of claims 1 to 8, and comprises at least the following steps:
providing a test clock signal having a specific period;
sending a current rising edge of the test clock signal;
after the delay, the read signal input end of the nonvolatile memory receives the current rising edge pulse output by the read signal path;
sending a trailing rising edge that follows the current rising edge;
after the delay, the read signal input end of the nonvolatile memory receives the read signal path and outputs a pulse at a rear rising edge; the address signal input end of the non-volatile memory receives the current address output by the address path;
under the action of the pulse of the back rising edge of the reading signal, the non-volatile memory outputs corresponding output data to the comparison end of the comparison output path according to the current address of the address signal;
the comparison output path compares the output data output by the non-volatile memory with preset comparison data and outputs a comparison result;
by continuously shortening the period of the test clock signal, a critical period that can ensure the consistency of the comparison results is determined.
10. The method of claim 9, wherein at least one rising edge of the test clock signal is passed from sending a current rising edge of the test clock signal to sending a trailing rising edge of the current rising edge.
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| CN202010465009.5A CN111696617B (en) | 2020-05-28 | 2020-05-28 | Nonvolatile memory reading speed test circuit and test method |
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| CN202010465009.5A Active CN111696617B (en) | 2020-05-28 | 2020-05-28 | Nonvolatile memory reading speed test circuit and test method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115542131A (en) * | 2022-11-23 | 2022-12-30 | 北京紫光青藤微系统有限公司 | Chip testing method and circuit |
| TWI818682B (en) * | 2022-05-06 | 2023-10-11 | 大陸商長鑫存儲技術有限公司 | Method for checking test circuit, test platform, storage medium and test system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366824A (en) * | 2012-03-31 | 2013-10-23 | 上海华虹Nec电子有限公司 | Non-volatile memory reading speed test circuit |
| CN103871481A (en) * | 2012-12-12 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Logic controller for nonvolatile memory |
| CN104575620A (en) * | 2014-09-26 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Calibrating circuit and calibrating method for data reading speed of non-volatile memory |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103366824A (en) * | 2012-03-31 | 2013-10-23 | 上海华虹Nec电子有限公司 | Non-volatile memory reading speed test circuit |
| CN103871481A (en) * | 2012-12-12 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Logic controller for nonvolatile memory |
| CN104575620A (en) * | 2014-09-26 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Calibrating circuit and calibrating method for data reading speed of non-volatile memory |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI818682B (en) * | 2022-05-06 | 2023-10-11 | 大陸商長鑫存儲技術有限公司 | Method for checking test circuit, test platform, storage medium and test system |
| CN115542131A (en) * | 2022-11-23 | 2022-12-30 | 北京紫光青藤微系统有限公司 | Chip testing method and circuit |
| CN115542131B (en) * | 2022-11-23 | 2023-03-10 | 北京紫光青藤微系统有限公司 | Chip testing method and circuit |
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| CN111696617B (en) | 2023-10-20 |
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