CN104575620A - Calibrating circuit and calibrating method for data reading speed of non-volatile memory - Google Patents
Calibrating circuit and calibrating method for data reading speed of non-volatile memory Download PDFInfo
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- CN104575620A CN104575620A CN201410503104.4A CN201410503104A CN104575620A CN 104575620 A CN104575620 A CN 104575620A CN 201410503104 A CN201410503104 A CN 201410503104A CN 104575620 A CN104575620 A CN 104575620A
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Abstract
The invention discloses a calibrating circuit for data reading speed of a non-volatile memory. Clock ends of two triggers D are respectively connected with a data reading clock signal, an end Q of a first trigger D is connected to an end D through a phase inverter, an end D of the second trigger D is connected to the output end of a data logic processing unit, and an end Q of the second trigger D is connected to an end S of a trigger RS; the end Q of the first trigger D outputs a switching signal of a switching switch group, so that the input end of the data logic processing unit is switched between a state for reading first data and a state for reading second data, and the data logic processing unit outputs 1 under the normal reading speed and outputs 0 under the abnormal reading speed; the end R of the trigger RS is connected with an enabling signal, and the end Q of the trigger RS is used for detecting whether the reading speed is normal or not. The invention also discloses a calibrating method for data reading speed of the non-volatile memory. By adopting the calibrating circuit and the calibrating method, the problems caused by a metastable state can be avoided.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) design and field tests, particularly relate to a kind of circuit of calibration non-volatility memorizer (NVM) read data speed, the invention still further relates to a kind of calibration steps of non-volatility memorizer read data speed.
Background technology
The method of existing following calibration (trimming) NVM read rate:
Use build-in self-test (BIST) read data order, regulate testing clock frequency, by data reading to test machine, relatively and check that whether data are correct.
Use BIST chessboard (checkerboard) order, to non-volatility memorizer write data 55H or aaH, BIST checkerboard condition is set and regulates test machine frequency, after data to be compared complete, see whether checkerboard is successful.
As shown in Figure 1, be the signal graph of existing non-volatility memorizer read data method of testing; This method of testing produces read data clock signal ACLK by the rising edge of test machine clock TCK, as shown in dotted line in Fig. 1 (1) and (3), and to sample sense data at the rising edge of TCK, as shown in dotted line in Fig. 1 (2).By adjusting the position of the frequency adjustment data sampling of TCK, the namely position of dotted line (2), meets the requirement of the specification limit (spec) of the address access time (Taa) of NVM.
The shortcoming of existing method of testing is: NVM is read in the position shown in dotted line (2) in FIG, trigger can data Dout change in sampling Dout data, cause trigger foundation (setup) time inadequate, inevitably generating metastable phenomenon, may cause other digital circuits not work normally.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of circuit calibrating non-volatility memorizer read data speed, can avoid the problem that metastable state is brought.For this reason, the present invention also provides a kind of calibration steps of non-volatility memorizer read data speed.
For solving the problems of the technologies described above, the calibration circuit of non-volatility memorizer read data speed provided by the invention, comprising: two d type flip flops, a rest-set flip-flop and data Logical processing units.
The clock end of two described d type flip flops all connects read data clock signal, the Q end of first d type flip flop in two described d type flip flops is connected to D end by a phase inverter, the S end that D end connects the output terminal of described mathematical logic processing unit, Q end is connected to described rest-set flip-flop of second d type flip flop.
The data of the input end of described mathematical logic processing unit by a switching switches set connection non-volatility memorizer and for reading calibration from described non-volatility memorizer, the reading address of described non-volatility memorizer is changed by described read data clock signal, and by the reading speed of non-volatility memorizer described in the periodic Control of the described read data clock signal of adjustment.
The Q end of described first d type flip flop is also connected to the control end of described change-over switch group.
The data of described calibration comprise the first data and the second data, and everybody of described first data and described second data is anti-phase mutually; The Q of described first d type flip flop holds the rising edge negate in described read data clock signal and described change-over switch group is produced and switches, described change-over switch group makes the annexation of the input end of described mathematical logic processing unit and the output terminal of described non-volatility memorizer switch under two states, described mathematical logic processing unit reads described first data in a first state, and described mathematical logic processing unit reads described second data in a second state; When described read data clock signal frequency is less than the maximum reading speed of described non-volatility memorizer, the output terminal of the described mathematical logic processing unit under the first state described and under described the second state keeps output logic 1, when described read data clock signal frequency is greater than the maximum reading speed of described non-volatility memorizer, the output terminal output logic 0 of the described mathematical logic processing unit under the first state described and under described the second state;
The R end of described rest-set flip-flop connects enable signal, and when described enable signal is logical zero, the S end of described rest-set flip-flop connects supply voltage, Q end exports initial logic 0.
When described enable signal is logical one, described calibration circuit starts, described mathematical logic processing unit reads described first data and described second data successively, when in the scope that described read data clock signal frequency is in the maximum reading speed being less than described non-volatility memorizer, the S end of described rest-set flip-flop is logical one, Q holds logical value to remain logical zero; When in the scope that described read data clock signal frequency is in the maximum reading speed being greater than described non-volatility memorizer, the S end of described rest-set flip-flop is logical zero, Q holds set to be logical one.
Further improvement is, described mathematical logic processing unit comprise one first with door, multiple second and door, described change-over switch group is made up of multiple first change-over switch.
Described first with the output terminal of the door output terminal as described mathematical logic processing unit, described first with the quantity of the input end of door, described second identical with the quantity of described first change-over switch with the quantity of door, each described second with the output terminal of door be connected respectively to described first with an input end of door.
Each described second comprises two input ends with door, and the in-phase signal that first input end gets input signal is input to the described second inversion signal getting input signal with door, the second input end and is input to described second and door.
Each described second to be connected with the two bits signal that described non-volatility memorizer exports respectively by described first change-over switch with two input ends of door and anti-phase each other with each described second two digits signal be connected with door; Each described second makes the annexation of corresponding two bits signal and two input ends switch with described first change-over switch corresponding to door under the Q of described first d type flip flop holds the control of the switching signal exported, and makes the logical value 1 of two digits signal be input to corresponding described second be input to the second input end of corresponding described second and door with the first input end of door, logical value 0 by the switching of described first change-over switch.
The input end of described mathematical logic processing unit is combined to form by each described second and the input end of door.
Further improvement is, described calibration circuit also comprises a data selector, an input end of described data selector connects the Q end of described second d type flip flop, another input end of described data selector connects supply voltage, the output terminal of described data selector is connected to the S end of described rest-set flip-flop, and described enable signal is connected to the control end of described data selector.
Further improvement is, changes the sampling time that described non-volatility memorizer exports data, and search out the calibration that described maximum reading speed realizes the read data speed of described non-volatility memorizer by the frequency changing described read data clock signal.
For solving the problems of the technologies described above, the calibration steps of non-volatility memorizer read data speed provided by the invention, comprises the steps:
Step one, in described non-volatility memorizer, write described first data and described second data.
Step 2, described enable signal are set to logical zero to be made described rest-set flip-flop initialize thus holds output logic 0 at Q.
Step 3, described enable signal are set to logical one makes described calibration circuit start working.
Step 4, under the control of the described read data clock signal of given frequency, described calibration circuit carries out calibration operation: the input end of described mathematical logic processing unit connects described non-volatility memorizer by described change-over switch group and reads described first data and described second data from described non-volatility memorizer successively, by described read data clock signal change described non-volatility memorizer reading address and by the reading speed of non-volatility memorizer described in the periodic Control of the described read data clock signal of adjustment; The Q of described first d type flip flop holds the rising edge negate in described read data clock signal and described change-over switch group is produced and switches and the annexation of the input end of described mathematical logic processing unit and the output terminal of described non-volatility memorizer is switched successively under two states.
The output valve that step 5, the Q reading described rest-set flip-flop hold, when the output valve that the Q of described rest-set flip-flop holds remains logical zero, the reading speed of described non-volatility memorizer is normal value, when the output valve set that the Q of described rest-set flip-flop holds is logical one, the reading speed of described non-volatility memorizer is outlier.
Step 6, the output valve of holding according to the Q of read described rest-set flip-flop adjust the frequency values of described read data clock signal and turn back to step 3 and carry out recalibrating until search out described reading speed maximal value; The method adjusting the frequency values of described read data clock signal is: when the reading speed of described non-volatility memorizer is normal value, increases the frequency of described read data clock signal; When the reading speed of described non-volatility memorizer is outlier, reduce the frequency of described read data clock signal.
The problem that the present invention can avoid asynchronous circuit metastable state to bring:
The situation that Time Created (setup) is inadequate may be there is in the input end of the present invention's second d type flip flop and D end, but in side circuit, the data of single-bit are after second d type flip flop and rest-set flip-flop two-stage trigger, and metastable state and impact thereof can be eliminated substantially.
Circuit of the present invention is relatively independent, starts working by enable signal is enable, and the output signal of second d type flip flop of possible generating metastable is not used in the control circui of other parts, even if metastable state situation occurs, can not cause other circuit cisco unity malfunction; Treat that circuit of the present invention is again enable, circuit of the present invention can be reworked.
Calibration circuit area of the present invention is little, and simple to operate.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the signal graph of existing non-volatility memorizer read data method of testing;
Fig. 2 is embodiment of the present invention calibration circuit figure;
Fig. 3 is present pre-ferred embodiments calibration circuit figure;
Fig. 4 is the address production electric circuit figure of embodiment of the present invention non-volatility memorizer;
Fig. 5 is the schematic diagram of rest-set flip-flop.
Embodiment
As shown in Figure 2, be embodiment of the present invention calibration circuit figure; The calibration circuit of embodiment of the present invention non-volatility memorizer read data speed comprises: two d type flip flops, 1 and 2, rest-set flip-flop 3 and a data Logical processing unit 4.
Two described d type flip flops 1 with 2 clock end be all connected read data clock signal ACLK, the Q end of first d type flip flop 1 in two described d type flip flops is connected to D end by a phase inverter 6, the S end that D end connects the output terminal of described mathematical logic processing unit 4, Q end is connected to described rest-set flip-flop 3 of second d type flip flop 2.Goodly be chosen as, described read data clock signal ACLK is produced by BIST or other logical circuit outside.
The input end of described mathematical logic processing unit 4 switches switches set 5 by one and connects non-volatility memorizer and data DOUT for reading calibration from described non-volatility memorizer, by described read data clock signal ACLK change described non-volatility memorizer reading address and by the reading speed of non-volatility memorizer described in the periodic Control of the described read data clock signal of adjustment.As shown in Figure 4, the address production electric circuit figure of embodiment of the present invention non-volatility memorizer, under the control of described read data clock signal ACLK, address generator 11 produces address signal ADDR [N-1:0], described non-volatility memorizer 10 exports corresponding data DOUT [K-1:0] according to address signal ADDR [N-1:0], address signal ADDR [N-1:0] is input in totalizer 12 and carries out adding 1 and be then input in address generator 11, by the cumulative realization of address signal ADDR [N-1:0] to the reading of the data of a sector address.
The Q of described first d type flip flop 1 holds output switching signal swap and is connected to the control end of described change-over switch group 5.
The data of described calibration comprise the first data and the second data, and everybody of described first data and described second data is anti-phase mutually.The Q of described first d type flip flop 1 holds the rising edge negate at described read data clock signal ACLK and described change-over switch group 5 is produced and switches, described change-over switch group 5 makes the annexation of the input end of described mathematical logic processing unit 4 and the output terminal of described non-volatility memorizer switch under two states, described mathematical logic processing unit 4 reads described first data in a first state, and described mathematical logic processing unit 4 reads described second data in a second state; When described read data clock signal ACLK frequency is less than the maximum reading speed of described non-volatility memorizer, the output terminal of the described mathematical logic processing unit 4 under the first state described and under described the second state all keeps output logic 1; When described read data clock signal ACLK frequency is greater than the maximum reading speed of non-volatility memorizer, the output terminal output logic 0 of the described mathematical logic processing unit 4 under the first state described and under described the second state.
In the embodiment of the present invention, change by the frequency changing described read data clock signal the sampling time that described non-volatility memorizer exports data, and search out the calibration that described maximum reading speed realizes the read data speed of described non-volatility memorizer.Wherein, the normal read data speed of described non-volatility memorizer is corresponded to when described read data clock signal ACLK frequency is less than the maximum reading speed of described non-volatility memorizer; The improper read data speed of described non-volatility memorizer is corresponded to when described read data clock signal ACLK frequency is greater than the maximum reading speed of non-volatility memorizer.
Goodly to be chosen as, described calibration circuit also comprises a data selector 7, an input end i.e. 1 end of described data selector 7 connects the Q end of described second d type flip flop 2, another input end i.e. 0 end of described data selector 7 connects supply voltage VDD, the output terminal of described data selector 7 is connected to the S end of described rest-set flip-flop 3, described enable signal testen is connected to the control end of described data selector 7, by the control of described enable signal testen, the S of described rest-set flip-flop 3 is held to select to be connected with in two input ends of described data selector 7.
The R end of described rest-set flip-flop 3 connects enable signal testen, and when described enable signal testen is logical zero, the S end of described rest-set flip-flop 3 connects supply voltage VDD, Q end and exports initial value logical zero.
When described enable signal testen is logical one, described calibration circuit starts, described mathematical logic processing unit 4 reads described first data and described second data successively, the S end of described rest-set flip-flop 3 is connected with the Q end of described second d type flip flop 2, within the scope of described normal reading speed, the S end of described rest-set flip-flop 3 is logical one, Q holds logical value to remain logical zero; Within the scope of described improper reading speed, the S end of described rest-set flip-flop 3 is logical zero, Q holds set to be logical one.
As shown in Figure 5, be the schematic diagram of rest-set flip-flop 3.As shown in table 1, be the menu of rest-set flip-flop 3.
Table 1
| R | S | Q |
| 0 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 1 | Constant |
| 0 | 0 | Indefinite |
The problem that the embodiment of the present invention can avoid asynchronous circuit metastable state to bring:
The situation that Time Created (setup) is inadequate may be there is in the input end of the embodiment of the present invention second d type flip flop 2 and D end, but in side circuit, the data of single-bit are after second d type flip flop 2 and rest-set flip-flop 3 two-stage trigger, and metastable state and impact thereof can be eliminated substantially.
Embodiment of the present invention circuit is relatively independent, start working by enable signal testen is enable, the output signal of second d type flip flop 2 of possible generating metastable is not used in the control circui of other parts, even if metastable state situation occurs, can not cause other circuit cisco unity malfunction; Treat that embodiment of the present invention circuit is again enable, embodiment of the present invention circuit can be reworked.
Embodiment of the present invention calibration circuit area is little, and simple to operate.
The calibration steps of embodiment of the present invention non-volatility memorizer read data speed, comprises the steps:
Step one, in described non-volatility memorizer, write described first data and described second data.
Step 2, described enable signal are set to logical zero to be made described rest-set flip-flop initialize thus holds output logic 0 at Q.
Step 3, described enable signal are set to logical one makes described calibration circuit start working.Namely now the S end of described rest-set flip-flop 3 is connected with the Q end of described second d type flip flop 2.
Step 4, under the control of the described read data clock signal ACLK of given frequency, described calibration circuit carries out calibration operation: the input end of described mathematical logic processing unit 4 connects described non-volatility memorizer by described change-over switch group 5 and reads described first data and described second data from described non-volatility memorizer successively, by described read data clock signal ACLK change described non-volatility memorizer reading address and by the reading speed of non-volatility memorizer described in the periodic Control of the described read data clock signal of adjustment; The Q of described first d type flip flop 1 holds the rising edge negate at described read data clock signal ACLK and described change-over switch group 5 is produced and switches and the annexation of the input end of described mathematical logic processing unit 4 and the output terminal of described non-volatility memorizer is switched successively under two states.
The output valve that step 5, the Q reading described rest-set flip-flop 3 hold, when the output valve that the Q of described rest-set flip-flop 3 holds remains logical zero, the reading speed of described non-volatility memorizer is normal value, when the output valve set that the Q of described rest-set flip-flop holds is logical one, the reading speed of described non-volatility memorizer is outlier.
Step 6, the output valve of holding according to the Q of read described rest-set flip-flop 3 adjust the frequency values of described read data clock signal ACLK and turn back to step 3 and carry out recalibrating until search out described reading speed maximal value; The method adjusting the frequency values of described read data clock signal ACLK is: when the reading speed of described non-volatility memorizer is normal value, reduces the cycle of described read data clock signal ACLK; When the reading speed of described non-volatility memorizer is outlier, increase the cycle of described read data clock signal ACLK.
As shown in Figure 3, be present pre-ferred embodiments calibration circuit figure; Present pre-ferred embodiments described in Fig. 3 and the difference part of the embodiment shown in Fig. 2 are: described mathematical logic processing unit 4 comprise one first with door 8, multiple second with door 9, described change-over switch group 5 is made up of multiple first change-over switch 5a.
Described first with the output terminal of door 8 output terminal as described mathematical logic processing unit 4, described first with the quantity of the input end of door 8, described second identical with the quantity of described first change-over switch 5a with the quantity of door 9, each described second with the output terminal of door 9 be connected respectively to described first with an input end of door 8.Described in Fig. 3, first uses A with door 8
0represent, the quantity of its input end is k/2; Each described second uses A with door 9 successively according to sorting
1to A
k/2represent.K represents the figure place of input data DOUT, and from data DOUT [0] to DOUT [k-1], adjacent two are one group and are connected to each described second in order in turn with on two input ends of door 9.
Each described second hold the in-phase signal of getting input signal to be input to described second with the first input end of door 9 and I1 holds the inversion signal getting input signal to be input to described second and door 9 with door 9, second input end and I2.
Each described second to be connected with two bits signal respectively by a described first change-over switch 5a with two input ends of door 9 and anti-phase each other with each described second two digits signal be connected with door 9; Such as, when k gets 8, described first data and described second data can be taken as aaH and 55H respectively, aaH and 55H respective adjacent two anti-phase each other, and the data of each identical bits of aaH and 55H are just in time anti-phase, input data can reach maximum upset.Each described second makes the annexation of corresponding two bits signal and two input ends switch with the described first change-over switch 5a corresponding to door 9 under the Q of described first d type flip flop 1 holds the control of the switching signal swap exported, and makes the logical value 1 of two digits signal be input to corresponding described second be input to the second input end of corresponding described second and door 9 with the first input end of door 9, logical value 0 by the switching of described first change-over switch 5a.
The input end of described mathematical logic processing unit 4 is combined to form by each described second and the input end of door 9.
As seen from Figure 3, when being in the scope of the maximum reading speed being less than described non-volatility memorizer when described read data clock signal ACLK frequency, the output terminal of the described mathematical logic processing unit 4 under the first state described and under described the second state all keeps output logic 1; When being in the scope of the maximum reading speed being less than described non-volatility memorizer when described read data clock signal ACLK frequency, due to read error, one is had at least to export 0 in each described second and door 9 of described mathematical logic processing unit 4, described like this first is 0 with the output of door 8, it is 0 that the S of described rest-set flip-flop 3 is held, thus makes the set of described rest-set flip-flop 3.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (5)
1. a calibration circuit for non-volatility memorizer read data speed, is characterized in that, calibration circuit comprises: two d type flip flops, a rest-set flip-flop and data Logical processing units;
The clock end of two described d type flip flops all connects read data clock signal, the Q end of first d type flip flop in two described d type flip flops is connected to D end by a phase inverter, the S end that D end connects the output terminal of described mathematical logic processing unit, Q end is connected to described rest-set flip-flop of second d type flip flop;
The data of the input end of described mathematical logic processing unit by a switching switches set connection non-volatility memorizer and for reading calibration from described non-volatility memorizer, the reading address of described non-volatility memorizer is changed by described read data clock signal, and by the reading speed of non-volatility memorizer described in the periodic Control of the described read data clock signal of adjustment;
The Q end of described first d type flip flop is also connected to the control end of described change-over switch group;
The data of described calibration comprise the first data and the second data, and everybody of described first data and described second data is anti-phase mutually; The Q of described first d type flip flop holds the rising edge negate in described read data clock signal and described change-over switch group is produced and switches, described change-over switch group makes the annexation of the input end of described mathematical logic processing unit and the output terminal of described non-volatility memorizer switch under two states, described mathematical logic processing unit reads described first data in a first state, and described mathematical logic processing unit reads described second data in a second state; When described read data clock signal frequency is less than the maximum reading speed of described non-volatility memorizer, the output terminal of the described mathematical logic processing unit under the first state described and under described the second state keeps output logic 1, when described read data clock signal frequency is greater than the maximum reading speed of described non-volatility memorizer, the output terminal output logic 0 of the described mathematical logic processing unit under the first state described and under described the second state;
The R end of described rest-set flip-flop connects enable signal, and when described enable signal is logical zero, the S end of described rest-set flip-flop connects supply voltage, Q end exports initial logic 0;
When described enable signal is logical one, described calibration circuit starts, described mathematical logic processing unit reads described first data and described second data successively, when in the scope that described read data clock signal frequency is in the maximum reading speed being less than described non-volatility memorizer, the S end of described rest-set flip-flop is logical one, Q holds logical value to remain logical zero; When in the scope that described read data clock signal frequency is in the maximum reading speed being greater than described non-volatility memorizer, the S end of described rest-set flip-flop is logical zero, Q holds set to be logical one.
2. the calibration circuit of non-volatility memorizer read data speed as claimed in claim 1, is characterized in that: described mathematical logic processing unit comprise one first with door, multiple second and door, described change-over switch group is made up of multiple first change-over switch;
Described first with the output terminal of the door output terminal as described mathematical logic processing unit, described first with the quantity of the input end of door, described second identical with the quantity of described first change-over switch with the quantity of door, each described second with the output terminal of door be connected respectively to described first with an input end of door;
Each described second comprises two input ends with door, and the in-phase signal that first input end gets input signal is input to the described second inversion signal getting input signal with door, the second input end and is input to described second and door;
Each described second to be connected with the two bits signal that described non-volatility memorizer exports respectively by described first change-over switch with two input ends of door and anti-phase each other with each described second two digits signal be connected with door; Each described second makes the annexation of corresponding two bits signal and two input ends switch with described first change-over switch corresponding to door under the Q of described first d type flip flop holds the control of the switching signal exported, and makes the logical value 1 of two digits signal be input to corresponding described second be input to the second input end of corresponding described second and door with the first input end of door, logical value 0 by the switching of described first change-over switch;
The input end of described mathematical logic processing unit is combined to form by each described second and the input end of door.
3. the calibration circuit of non-volatility memorizer read data speed as claimed in claim 1 or 2, it is characterized in that: described calibration circuit also comprises a data selector, an input end of described data selector connects the Q end of described second d type flip flop, another input end of described data selector connects supply voltage, the output terminal of described data selector is connected to the S end of described rest-set flip-flop, and described enable signal is connected to the control end of described data selector.
4. the calibration circuit of non-volatility memorizer read data speed as claimed in claim 1, it is characterized in that: change by the frequency changing described read data clock signal the sampling time that described non-volatility memorizer exports data, and search out the calibration that described maximum reading speed realizes the read data speed of described non-volatility memorizer.
5. use the calibration steps of the calibration circuit of non-volatility memorizer read data speed as claimed in claim 1, it is characterized in that, comprise the steps:
Step one, in described non-volatility memorizer, write described first data and described second data;
Step 2, described enable signal are set to logical zero to be made described rest-set flip-flop initialize thus holds output logic 0 at Q;
Step 3, described enable signal are set to logical one makes described calibration circuit start working;
Step 4, under the control of the described read data clock signal of given frequency, described calibration circuit carries out calibration operation: the input end of described mathematical logic processing unit connects described non-volatility memorizer by described change-over switch group and reads described first data and described second data from described non-volatility memorizer successively, by described read data clock signal change described non-volatility memorizer reading address and by the reading speed of non-volatility memorizer described in the periodic Control of the described read data clock signal of adjustment; The Q of described first d type flip flop holds the rising edge negate in described read data clock signal and described change-over switch group is produced and switches and the annexation of the input end of described mathematical logic processing unit and the output terminal of described non-volatility memorizer is switched successively under two states;
The output valve that step 5, the Q reading described rest-set flip-flop hold, when the output valve that the Q of described rest-set flip-flop holds remains logical zero, the reading speed of described non-volatility memorizer is normal value, when the output valve set that the Q of described rest-set flip-flop holds is logical one, the reading speed of described non-volatility memorizer is outlier;
Step 6, the output valve of holding according to the Q of read described rest-set flip-flop adjust the frequency values of described read data clock signal and turn back to step 3 and carry out recalibrating until search out described reading speed maximal value; The method adjusting the frequency values of described read data clock signal is: when the reading speed of described non-volatility memorizer is normal value, increases the frequency of described read data clock signal; When the reading speed of described non-volatility memorizer is outlier, reduce the frequency of described read data clock signal.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108597470A (en) * | 2018-05-08 | 2018-09-28 | 深圳市华星光电技术有限公司 | Display device drive system and method and display device |
| CN111696617A (en) * | 2020-05-28 | 2020-09-22 | 上海华虹宏力半导体制造有限公司 | Non-volatile memory read data speed test circuit and test method |
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| CN103871444A (en) * | 2012-12-14 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Reading time slots generation circuit of non-volatile memory |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5557232A (en) * | 1993-08-13 | 1996-09-17 | Nec Corporation | Semiconductor integrated circuit device having a control circuit for setting the test mode |
| JP2002075000A (en) * | 2000-08-30 | 2002-03-15 | Nec Corp | Semiconductor integrated circuit and its operating method |
| CN103871444A (en) * | 2012-12-14 | 2014-06-18 | 上海华虹宏力半导体制造有限公司 | Reading time slots generation circuit of non-volatile memory |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108597470A (en) * | 2018-05-08 | 2018-09-28 | 深圳市华星光电技术有限公司 | Display device drive system and method and display device |
| CN111696617A (en) * | 2020-05-28 | 2020-09-22 | 上海华虹宏力半导体制造有限公司 | Non-volatile memory read data speed test circuit and test method |
| CN111696617B (en) * | 2020-05-28 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Nonvolatile memory reading speed test circuit and test method |
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| CN104575620B (en) | 2017-08-08 |
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