CN111696617B - Nonvolatile memory reading speed test circuit and test method - Google Patents
Nonvolatile memory reading speed test circuit and test method Download PDFInfo
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- CN111696617B CN111696617B CN202010465009.5A CN202010465009A CN111696617B CN 111696617 B CN111696617 B CN 111696617B CN 202010465009 A CN202010465009 A CN 202010465009A CN 111696617 B CN111696617 B CN 111696617B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
Abstract
The application relates to the technical field of semiconductor integrated circuit design and test, in particular to a nonvolatile memory read data speed test circuit and a test method. The testing circuit comprises a reading signal path, wherein the output end of the reading signal path is connected with the reading end of the nonvolatile memory; the read signal path can output a read signal to the read signal input end according to the test clock signal; an address path including a first address unit for outputting a time-sequence balanced address signal and a time-sequence balanced selector for selecting and outputting an output signal of the first address unit; the comparison output path is connected with the output end of the non-volatile memory, and is used for comparing the output data of the output end of the non-volatile memory with preset comparison data and outputting a comparison result, so that the problem that deviation occurs in measurement and calculation of the time TAA of the data read by the non-volatile memory in the related technology can be solved, and the accuracy of the TAA test can be improved.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuit design and test, in particular to a nonvolatile memory data reading speed test circuit and a nonvolatile memory data reading speed test method.
Background
The memory is the main medium for data storage in the computer, and the read-write speed of the memory greatly influences the working speed of the computer. In particular, in recent years, with the rapid development of internet technology such as cloud computing, the demand for memory read/write speed has been increasing.
For a nonvolatile memory, the typical measurement method of the reading speed is as follows: by continuously adjusting the period of the externally applied clock of the memory reading operation, the critical clock period which can be accurately read by the memory is taken as the time for reading data of the nonvolatile memory.
However, this method causes a problem of difficulty in balancing between signals, which results in that the final read non-critical clock cycle includes a measurement deviation, and once the critical clock cycle including the measurement deviation is taken as the time of reading data, the measurement deviation of the time of reading data is caused.
Disclosure of Invention
The application provides a non-volatile memory read data speed test circuit and a test method, which can solve the problem that the measurement and calculation of the time of the non-volatile memory read data in the related technology has deviation.
As a first aspect of the present application, there is provided a nonvolatile memory read data speed test circuit, the nonvolatile memory including a read signal input terminal, an address signal input terminal, and an output terminal, the nonvolatile memory read data speed test circuit comprising:
the output end of the read signal path is connected with the read end of the nonvolatile memory; in a test mode, the read signal path is capable of outputting a read signal to the read signal input terminal according to a test clock signal;
an address path including a first address unit for outputting a time-sequence balanced address signal and a time-sequence balanced selector for selecting and outputting an output signal of the first address unit;
and the comparison output path is connected with the output end of the nonvolatile memory, and is used for comparing the output data of the output end of the nonvolatile memory with preset comparison data and outputting a comparison result.
Optionally, the first address unit includes a first address register, a first address logic operator, and an address latch;
the first address register outputs a current address to the first address logic operator when receiving a current rising edge of the test clock signal;
the current address is transmitted to the address latch through the first address logic operator and is latched in the address latch; the address latch outputs a current address to the timing balance selector at a subsequent rising edge of the test clock signal.
Optionally, the address path further includes a second address unit for outputting an address signal that is not time-sequence balanced;
the time sequence balance selector is used for selecting between output signals of the first address unit or output signals of the second address unit and outputting corresponding output signals.
Optionally, the second address unit includes a second address register and a second address logic operator;
the second address register outputs a current address to a second address logic operator when receiving the current rising edge of the test clock signal;
the current address is transmitted to the time sequence balance selector through the second address logic operator.
Optionally, the address path further includes: a first test mode selector;
the first test mode selector is used for selecting and outputting an output signal of the time sequence balance selector.
Optionally, the read signal path includes: a read signal register and a read signal logic operator;
and the read signal register outputs a read signal to the read signal logic operator when receiving the rising edge of the test clock signal.
Optionally, the read signal path further comprises: and the second test mode selector is used for selecting and outputting the output signal of the read signal logic operator.
Optionally, the comparison output path includes: an output latch, a comparator, and a comparison result register;
the input end of the output latch is a comparison end of the comparison output path, and the clock end of the output latch is connected with the test clock signal;
the comparator is provided with comparison data in advance, the input end of the comparator is connected with the output end of the output latch and is used for comparing the output data of the output latch with preset comparison data and outputting a comparison result, and the comparison result register is used for registering the comparison result.
As a second aspect of the present application, there is provided a nonvolatile memory read data speed testing method, which is based on the nonvolatile memory read data speed testing circuit according to the first aspect of the present application, and at least includes the following steps:
providing a test clock signal having a particular period;
transmitting a current rising edge of the test clock signal;
after delay, the read signal input end of the nonvolatile memory receives the current rising edge pulse output by the read signal path;
transmitting a subsequent rising edge located after the current rising edge;
after delay, the read signal input end of the nonvolatile memory receives the rising edge pulse output by the read signal path; the address signal input end of the non-volatile memory receives the current address output by the address path;
under the action of the subsequent rising edge pulse of the read signal, the nonvolatile memory outputs corresponding output data to a comparison end of the comparison output path according to the current address of the address signal;
the comparison output path compares the output data output by the non-volatile memory with preset comparison data and outputs a comparison result;
and determining a critical period capable of ensuring the consistency of the comparison result by continuously shortening the period of the test clock signal.
Optionally, from the current rising edge of the test clock signal being sent to the rising edge of at least one of the test clock signals being passed during the following rising edge of the current rising edge being sent.
The technical scheme of the application at least comprises the following advantages: under the effect of the test clock signal, the read signal path generates rising edge pulses of the read signal, and the rising edge pulses of the read signal can enable the nonvolatile memory to output data to the comparison output path according to the address in the received address signal when the rising edge pulses of the read signal occur; under the action of a test clock signal, the comparison output path compares the received output data with preset comparison data, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable the comparison result to be between the reading error and the reading accuracy is determined, and the critical period is used as the time for reading data of the nonvolatile memory, so that the accuracy of the TAA test can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a data rate test circuit for a nonvolatile memory according to an embodiment of the present application;
FIG. 2 is a timing diagram of read signals and address signals in an embodiment of the application;
FIG. 3 is a schematic diagram of another non-volatile memory read data rate test circuit according to an embodiment of the present application;
FIG. 4 is a timing diagram of read signals, first address register output signals, and address signals according to an embodiment of the present application;
FIG. 5 is a schematic diagram of another method for testing the read data speed of a nonvolatile memory according to an embodiment of the present application;
FIG. 6 is a timing diagram of signals in an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a READ data rate test circuit for a nonvolatile memory according to an embodiment of the present application is shown, wherein the nonvolatile memory NVM includes a READ signal input terminal READ, an address signal input terminal ADDR and an output terminal DOUT; the read data rate test circuit suitable for the nonvolatile memory NVM includes:
a READ signal path 11, wherein an output end of the READ signal path 11 is connected with a READ signal input end READ of the nonvolatile memory NVM; in test mode, the READ signal path 11 is capable of outputting a READ signal to the READ signal input READ in accordance with the test clock signal CLK. The read signal includes alternately occurring rising edge pulses and falling edge pulses, and the rising edge pulses of the read signal can excite the nonvolatile memory NVM to perform a read operation.
An address path 12, an output terminal of the address path 12 is connected to an address signal input terminal ADDR of the nonvolatile memory NVM, the address path 12 includes a first address unit 121 for outputting a time-balanced address signal, and a time-balanced selector 123 for selecting and outputting an output signal of the first address unit 121. The address signal includes a plurality of data addresses, and the time-sequence-balanced address signal refers to the time when the address signal starts to reach the address signal input terminal ADDR of the nonvolatile memory NVM, which is the same as the time when the rising edge pulse of the read signal can trigger the nonvolatile memory NVM to perform the read operation.
As shown in fig. 2, the address signal includes an address A0, an address A1 and an address A2, after a first rising edge of the test clock signal CLK, a first delay time T1 passes, a first rising edge pulse of the READ signal starts to reach a READ signal input terminal READ of the nonvolatile memory, after a third rising edge of the test clock signal CLK, a second delay time T2 passes, i.e., a time Q1, a first address A0 of the address signal starts to reach an address signal input terminal ADDR of the nonvolatile memory, and a second rising edge pulse of the READ signal starts to reach a READ signal input terminal READ of the nonvolatile memory at a time Q1, the address signal shown in fig. 2 is a time-balanced address signal, and a time when the READ signal rising edge pulse starts to reach the address signal input terminal ADDR of the nonvolatile memory is the same as a time when the READ signal rising edge pulse can trigger the READ operation of the nonvolatile memory, and the time is a time Q1.
And a comparison output path 13, wherein the comparison end of the comparison output path 13 is connected with the output end DOUT of the nonvolatile memory NVM, and is used for comparing the output data of the output end DOUT of the nonvolatile memory NVM with preset comparison data and outputting a comparison result from the output end TDO of the comparison output path 13. If the output data and the comparison data are consistent, the reading is correct, and if the output data and the comparison data are inconsistent, the reading is wrong.
In summary, under the effect of the test clock signal, the read signal path generates a rising edge pulse of the read signal, and the rising edge pulse of the read signal can enable the nonvolatile memory NVM to output data to the comparison output path according to the address in the received address signal when the rising edge pulse of the read signal occurs; under the action of a test clock signal, the comparison output path compares the received output data with preset comparison data, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable the comparison result to be between the reading error and the reading accuracy is determined, and the critical period is used as the time for reading the data of the nonvolatile memory NVM, so that the accuracy of the TAA test can be improved.
Referring to fig. 3, another non-volatile memory read data speed test circuit according to an embodiment of the present application is shown, where the address path further includes a second address unit 122 for outputting address signals that are not time-balanced on the basis of fig. 1; the control terminal of the timing balance selector 123 is connected to a TAA mode control signal taa_mode, and the timing balance selector 123 selects between the output signal of the first address unit 121 or the output signal of the second address unit 122 according to the TAA mode control signal taa_mode and outputs a corresponding output signal.
Because the nonvolatile memory NVM is tested in the test mode, other tests are performed in addition to the TAA test; for other testing processes, the time-balanced address signals affect the testing structure, so the time-balanced selector 123 is controlled to select the second address unit 122 of the address signals which are not time-balanced, and the time-balanced selector 123 is controlled to select the first address unit 121 of the address signals which are time-balanced when the TAA test is required.
As shown in fig. 3, the first address unit 121 includes a first address register reg1_ad, a first address logic operator log1_ad, and an address latch reg_pl_ad. The output terminal of the first address register reg1_ad is connected to the input terminal of the first address logic operator Log1_ad, the output terminal of the first address logic operator Log1_ad is connected to the input terminal of the address latch reg_pl_ad, and the output terminal of the address latch reg_pl_ad is connected to an input terminal of the timing balance selector 123. The first address register reg1_ad, the first address logic operator log1_ad and the address latch reg_pl_ad cooperate to perform a timing balance function on the address signals, so that the first address unit 121 outputs the timing balanced address signals.
As shown in fig. 4, the address signals include an address A0, an address A1, an address A2, and an address A3. The first address register reg1_ad outputs the current address to the first address logic operator Log1_ad upon receiving the current rising edge of the test clock signal CLK. The current address is transmitted to the address latch REG_pl_ad through the first address logic operator and is latched in the address latch REG_pl_ad; the address latch reg_pl_ad outputs a current address to the timing balance selector at a subsequent rising edge of the test clock signal CLK. The test clock signal includes alternately generated rising and falling edges, with the latter rising edge being the rising edge of the test clock signal generated after the instant at which the current rising edge occurs.
The second address unit 122 includes a second address register reg2_ad and a second address logic operator Log2_ad; the clock terminal of the second address register reg2_ad is connected to the test clock signal CLK, the output terminal is connected to the input terminal of the second address logic operator Log2_ad, and the output terminal of the second address logic operator Log2_ad is connected to the other input terminal of the timing balance selector 123. The second address register reg2_ad outputs the current address to the second address logic operator Log2_ad when receiving the current rising edge of the test clock signal CLK; the current address is transferred to the timing balance selector 123 through the second address logic operator Log2 ad.
The address path 12 further includes: a first test mode selector 124; an input terminal of the first test mode selector 124 is connected to an output terminal of the timing balance selector 123, and a control terminal is connected to a test mode control signal test_mode, for selecting and outputting an output signal of the timing balance selector 123 according to the test mode control signal test_mode.
The read signal path 12 includes: a read signal register reg_re, a read signal logic operator log_re, and a second test mode selector 111; the clock end of the READ signal register reg_re is connected with the test clock signal CLK, the output end is connected with the READ signal logic operator log_re, the output end of the READ signal logic operator log_re is connected with an output end of the second test mode selector 111, the control end of the second test mode selector 111 is connected with the test mode control signal test_mode, when the rising edge of the test clock signal CLK is received, the READ signal register reg_re outputs a READ signal to the READ signal logic operator log_re, the READ signal logic operator log_re outputs a signal to the second test mode selector 111, and the second test mode selector 111 controls the READ signal to be output to the READ signal input end READ of the nonvolatile memory NVM according to the test mode control signal test_mode.
The alignment output path 13 includes: an output latch reg1_co, a comparator COMPARE, and a comparison result register reg2_co; the input end of the output latch reg1_co is the comparison end of the comparison output path 13, and is used for being connected with the output end DOUT of the nonvolatile memory NVM, the clock end of the output latch reg1_co is connected with the test clock signal CLK, the output end of the output latch reg1_co is connected with the input end of the comparator COMPARE, the output end of the comparator COMPARE is connected with the input end of the comparison result register reg2_co, and the output end of the comparison result register reg2_co is the output end TDO of the comparison output path 13.
The comparator COMPARE is preset with comparison data for comparing the output data of the output latch reg1_co with preset comparison data and outputting a comparison result, and the comparison result register reg2_co is used for registering the comparison result.
In summary, under the effect of the test clock signal, the read signal path generates a rising edge pulse of the read signal, and the rising edge pulse of the read signal can enable the nonvolatile memory NVM to output data to the comparison output path according to the address in the received address signal when the rising edge pulse of the read signal occurs; under the action of a test clock signal, the comparison output path compares the received output data with preset comparison data, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable the comparison result to be between the reading error and the reading accuracy is determined, and the critical period is used as the time for reading the data of the nonvolatile memory NVM, so that the accuracy of the TAA test can be improved.
Referring to fig. 5, another method for testing the read data speed of the nonvolatile memory according to an embodiment of the present application is shown, and the method is based on the nonvolatile memory read data speed testing circuit shown in any one of fig. 1 and fig. 3, as shown in fig. 6, and at least includes the following steps:
step 501: a test clock signal CLK having a specific period is provided.
Step 502: at time Q2, the current rising edge C1 of the test clock signal CLK is sent.
Step 503: the READ signal path sends the current rising edge pulse R1 according to the current rising edge C1, and after the first delay time T1, namely at the moment Q3, the READ signal input end READ of the nonvolatile memory receives the READ signal path and outputs the current READ signal.
The first address register reg1_ad in the address path currently generates the current address A0 along the rising edge C1, and the address latch of the address path latches the current address A0 waiting for the following rising edge C2.
Step 504: at time Q4, when a subsequent rising edge C2 following the current rising edge C1 is transmitted, the subsequent rising edge C2 is illustratively located at a second rising edge after the current rising edge C1.
Step 505: the READ signal path sends the following rising edge pulse R2 according to the following rising edge C2, and after the first delay time T1, i.e. at the time Q1, the READ signal input terminal READ of the nonvolatile memory receives the READ signal path and outputs the following rising edge pulse R2. The first delay time T1 is a time from when the following rising edge C2 is sent to when the non-volatile memory receives the following rising edge pulse R2.
The address latch of the address path releases the current address A0 latched therein according to the following rising edge C2, and receives the current address AO output by the address path after the second delay time T1, i.e., at the time Q1, and after the first delay time T2, i.e., at the time Q1, the address signal input terminal ADDR of the nonvolatile memory. The second delay time T2 is a time from when the rising edge C2 is sent out to when the nonvolatile memory receives the current address AO.
The first delay time T1 is equal to the second delay time T2.
Step 506: under the action of the following rising edge pulse R2 of the read signal, the nonvolatile memory outputs corresponding output Data0 to the comparison end of the comparison output path at the moment Q5 according to the current address A0. It should be noted that, the time TAA for reading Data is represented as a time interval between the time when the nonvolatile memory receives the following rising edge pulse R2 of the read signal and the current address A0, and the time when the corresponding output Data0 is outputted, that is, a time interval from the time Q1 to the time Q5.
Step 507: the comparison output path compares the output Data0 output by the nonvolatile memory with preset comparison Data and outputs a comparison result.
The operation starts after the set time T4 has elapsed since the output Data0 is received by the output latch reg1_co, and the output latch reg1_co outputs the output Data0 latched therein by the rising edge of the next test clock signal after the elapse of T4, that is, the rising edge C3 received by the output latch reg1_co. It should be explained that since there is a certain delay, i.e., the third delay time T3, in the transmission of the test clock signal to the clock terminal of the output latch reg1_co, the rising edge C3 received by the output latch reg1_co is delayed by the third delay time T3 from the occurrence of the rising edge C3.
Step 508: and determining a critical period capable of ensuring the consistency of the comparison result by continuously shortening the period of the test clock signal.
Under the control of TAA mode control signal TAA_mode, the test circuit automatically scans and compares the full address data, and gradually shortens the period of an external test clock signal until the critical period of consistent comparison results can be ensured.
That is, critical period = taa+t1-t3+t4;
since the first delay time T1 and the second delay time T2 are equal through the timing balance, the time TAA for reading data can be calculated with high accuracy by the critical period, the first delay time T1, the third delay time T3, and the set time T4.
If the first delay time T1, which is passed by the time when the nonvolatile memory receives the read signal, is the same as the third delay time T3, which is passed by the time when the output latch reg1_co receives the test clock signal CLK, the time TAA for reading the data is the difference between the critical period and the set time T4, so that the measurement deviation can be removed when the time TAA for reading the data is measured according to the critical period, and the measurement accuracy of the TAA is ensured. It should be explained that when the clock terminal of the output latch reg1_co and the READ signal input terminal READ of the nonvolatile memory reach the timing balance, the first delay time T1 is the same as the third delay time T3. Alternatively, the clock terminal of the output latch reg1_co and the READ signal input terminal READ of the nonvolatile memory are brought into timing balance by setting the number of device stages and the device type in the clock path to the clock terminal of the output latch reg1_co and the READ signal input terminal READ of the nonvolatile memory to be the same.
It should be explained that, as shown in fig. 6, the address signal includes an address A0, an address A1, an address A2, and an address A3, and the output signal includes output Data0 and output Data1. In the above embodiment, taking the output Data0 according to the address A0 as an example, the process of reading the corresponding Data according to the address by the nonvolatile memory under the effect of the rising edge pulse of the read signal according to other addresses is the same as that described above, and the description thereof is omitted herein.
In summary, under the effect of the test clock signal, the read signal path generates a rising edge pulse of the read signal, and the rising edge pulse of the read signal can enable the nonvolatile memory NVM to output data to the comparison output path according to the address in the received address signal when the rising edge pulse of the read signal occurs; under the action of a test clock signal, the comparison output path compares the received output data with preset comparison data, if the output data is consistent with the comparison data, the reading is correct, and if the output data is inconsistent with the comparison data, the reading is wrong; by continuously shortening the period of the test clock signal, a critical period which can enable the comparison result to be between the reading error and the reading accuracy is determined, and the critical period is used as the time for reading the data of the nonvolatile memory NVM, so that the accuracy of the TAA test can be improved.
Claims (9)
1. A nonvolatile memory read data rate test circuit, the nonvolatile memory including a read signal input, an address signal input, and an output, the nonvolatile memory read data rate test circuit comprising:
the output end of the read signal path is connected with the read end of the nonvolatile memory; the read signal path can output a read signal to the read signal input end according to the test clock signal;
an address path including a first address unit for outputting a time-sequence balanced address signal and a time-sequence balanced selector for selecting and outputting an output signal of the first address unit;
the comparison output path is connected with the output end of the non-volatile memory, and is used for comparing output data of the output end of the non-volatile memory with preset comparison data and outputting a comparison result;
the first address unit comprises a first address register, a first address logic operator and an address latch;
the first address register outputs a current address to the first address logic operator when receiving a current rising edge of the test clock signal;
the current address is transmitted to the address latch through the first address logic operator and is latched in the address latch; the address latch outputs a current address to the timing balance selector at a subsequent rising edge of the test clock signal.
2. The nonvolatile memory read data rate test circuit of claim 1 wherein said address path further comprises a second address unit for outputting address signals that are not time-balanced;
the time sequence balance selector is used for selecting between output signals of the first address unit or output signals of the second address unit and outputting corresponding output signals.
3. The nonvolatile memory read data rate test circuit of claim 2 wherein said second address unit comprises a second address register and a second address logic operator;
the second address register outputs a current address to a second address logic operator when receiving the current rising edge of the test clock signal;
the current address is transmitted to the time sequence balance selector through the second address logic operator.
4. The nonvolatile memory read data rate test circuit of claim 1 wherein said address path further comprises: a first test mode selector;
the first test mode selector is used for selecting and outputting an output signal of the time sequence balance selector.
5. The nonvolatile memory read data rate test circuit of claim 1 wherein the read signal path comprises: a read signal register and a read signal logic operator;
and the read signal register outputs a read signal to the read signal logic operator when receiving the rising edge of the test clock signal.
6. The nonvolatile memory read data rate test circuit of claim 5 wherein the read signal path further comprises: and the second test mode selector is used for selecting and outputting the output signal of the read signal logic operator.
7. The nonvolatile memory read data rate test circuit of claim 1 wherein said comparison output path comprises: an output latch, a comparator, and a comparison result register;
the input end of the output latch is a comparison end of the comparison output path, and the clock end of the output latch is connected with the test clock signal;
the comparator is provided with comparison data in advance, the input end of the comparator is connected with the output end of the output latch and is used for comparing the output data of the output latch with preset comparison data and outputting a comparison result, and the comparison result register is used for registering the comparison result.
8. A method for testing the data reading speed of a nonvolatile memory, which is based on the circuit for testing the data reading speed of the nonvolatile memory according to any one of claims 1 to 7, and comprises the following steps:
providing a test clock signal having a period;
transmitting a current rising edge of the test clock signal;
after delay, the read signal input end of the nonvolatile memory receives the current rising edge pulse output by the read signal path;
transmitting a subsequent rising edge located after the current rising edge;
after delay, the read signal input end of the nonvolatile memory receives the rising edge pulse output by the read signal path; the address signal input end of the non-volatile memory receives the current address output by the address path;
under the action of the subsequent rising edge pulse of the read signal, the nonvolatile memory outputs corresponding output data to a comparison end of the comparison output path according to the current address of the address signal;
the comparison output path compares the output data output by the non-volatile memory with preset comparison data and outputs a comparison result;
and determining a critical period capable of ensuring the consistency of the comparison result by continuously shortening the period of the test clock signal.
9. The method of claim 8, wherein at least one rising edge of the test clock signal is passed during a period from a current rising edge of the test clock signal being sent to a subsequent rising edge of the current rising edge being sent.
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