CN103366824A - Non-volatile memory reading speed test circuit - Google Patents
Non-volatile memory reading speed test circuit Download PDFInfo
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- CN103366824A CN103366824A CN2012100929485A CN201210092948A CN103366824A CN 103366824 A CN103366824 A CN 103366824A CN 2012100929485 A CN2012100929485 A CN 2012100929485A CN 201210092948 A CN201210092948 A CN 201210092948A CN 103366824 A CN103366824 A CN 103366824A
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Abstract
The invention discloses a test circuit for testing a non-volatile memory. The test circuit comprises an address generation circuit for generating an address scanning signal of the non-volatile memory under the driving of an external input clock and continuously reading the non-volatile memory, a bit selection circuit for selecting a certain bit data signal from data signals Dm-D0 output by the non-volatile memory as a reference, forming a square wave signal and testing the reading speed of the non-volatile memory, and a programmable frequency divider for performing frequency division on the square wave signals formed by the data signal selected by the bit selection circuit according to a set frequency division ratio and outputting a low-frequency signal. According to the test circuit, the time delay error of each control circuit in the test circuit is eliminated; the reading speed of the non-volatile memory can be accurately tested; the test precision is high; the speed differences of data bits can be compared by controlling the selection of data.
Description
Technical field
The present invention relates to SIC (semiconductor integrated circuit) and make the field, particularly relate to a kind of non-volatility memorizer NVM (Non-Volatile Memory) reading speed test circuit.
Background technology
Present non-volatility memorizer reading speed test circuit adopts structure shown in Figure 1, address production electric circuit externally produces the reference address An～A0 of non-volatility memorizer under the driving of clock (by pin PAD input), the output data Dm～D0 of the reference data that presets and nonvolatile memory is compared by comparator circuit, and draws comparative result.Therefore this test circuit has introduced test error owing to introduced the delayed impact of comparator circuit.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of non-volatility memorizer reading speed test circuit, can accurately test the reading speed of non-volatility memorizer, and can not introduce the delay equal error of test circuit.
For solving the problems of the technologies described above, non-volatility memorizer reading speed test circuit of the present invention comprises:
One address production electric circuit, externally the address scan signal of generation non-volatility memorizer under the driving of input clock reads non-volatility memorizer continuously;
Select circuit for one, data-signal Dm～D0 that described non-volatility memorizer is exported selects certain a data signal as benchmark, and forms square-wave signal, the reading speed of test non-volatility memorizer;
One programmable frequency divider, the square-wave signal that the data-signal of selecting circuit to select to institute's rheme forms carries out frequency division according to the frequency dividing ratio of setting, and then exports with low frequency signal;
According to identical every address date, the opposite form of neighbor address data step-by-step carries out the data pre-storage storage, according to the address saltus step outputting data signals Dm～D0 of described address scan signal in the described non-volatility memorizer.
Adopt non-volatility memorizer reading speed test circuit of the present invention, the saltus step speed of address scan signal is directly proportional with outside input clock frequency, and the saltus step speed of described address scan signal and frequency dividing ratio (K) all are that system sets in advance, if therefore can be correct read non-volatility memorizer, the frequency of the low frequency signal waveform of programmable frequency divider output learns in advance, thus the reading speed that can test non-volatility memorizer by the saltus step speed of control address scan signal.
The present invention has got rid of the delay time error of each control circuit in the test circuit, can realize the accurate test of non-volatility memorizer reading speed, and measuring accuracy is high; And by the selection of control data bit, can compare the speed difference of each data bit.
Test mode of the present invention is simple, and according to the frequency of outside input clock, the observation output signal frequency just can draw the non-volatility memorizer reading speed.
Circuit structure of the present invention is simple, is easy to realize that cost is low.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 is existing non-volatility memorizer reading speed test circuit figure;
Fig. 2 is non-volatility memorizer reading speed test circuit one embodiment schematic diagram of the present invention.
Embodiment
In conjunction with shown in Figure 2, in one embodiment of this invention, describe as an example of the wide FLASH as 16 bits of outputs data bits example.Described non-volatility memorizer reading speed test circuit comprises: an address production electric circuit, select circuit, a programmable frequency divider for one.According to identical every address date, the opposite form of neighbor address data step-by-step carries out the data pre-storage storage, according to the address saltus step outputting data signals Dm～D0 of described address scan signal in the described non-volatility memorizer.Such as address 0 storage 0xAAAA, address 1 storage 0x5555, by that analogy.
Described address production electric circuit produces the address scan signal of non-volatility memorizer under the driving of the outside input clock (clock) of being inputted by input pin PAD2, read continuously non-volatility memorizer.For example add 1 with simple address and realize address scan.
The data-signal Dm of non-volatility memorizer output～D0 selects circuit to select through institute's rheme, for example selects D0 as benchmark, and forms square-wave signal as the input signal of programmable frequency divider, the reading speed of test non-volatility memorizer.
Described programmable frequency divider carries out frequency division according to the frequency dividing ratio of setting to input signal, thereby exports through output pin PAD1 with the low frequency signal process.
The saltus step speed of described address scan signal determines that by the outside input clock frequency v from input pin PAD2 input the frequency dividing ratio k of described programmable frequency divider sets in advance; If therefore non-volatility memorizer can accurately read, the low frequency signal frequency of being exported by output pin PAD1 is determined by function f (v, k): f (v, k)=v/ (2 * k).
Raising can be measured the maximum reading speed of non-volatility memorizer by the frequency of the outside input clock of input pin PAD2 input; Select circuit to select bit data signals different among the data-signal Dm～D0 of non-volatility memorizer output as the data-signal of programmable frequency divider input by institute's rheme, repeat to test the speed difference that can draw between each data bit signal.
Non-volatility memorizer reading speed test circuit structure of the present invention can with build-in self-test (BIST) combination of the existing non-volatility memorizer that generally adopts, realize effectively control test.Wherein, address production electric circuit is produced by BIST; The primary data of non-volatility memorizer is finished by the BIST operation; The position selects circuit and frequency dividing ratio k to realize in the BIST circuit; Input pin PAD2 and output pin PAD1 can multiplexing BIST port.
Below through the specific embodiment and the embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. a non-volatility memorizer reading speed test circuit is characterized in that, comprising:
One address production electric circuit, externally the address scan signal of generation non-volatility memorizer under the driving of input clock reads non-volatility memorizer continuously;
Select circuit for one, data-signal Dm～D0 that described non-volatility memorizer is exported selects certain a data signal as benchmark, and forms square-wave signal, the reading speed of test non-volatility memorizer;
One programmable frequency divider, the square-wave signal that the data-signal of selecting circuit to select to institute's rheme forms carries out frequency division according to the frequency dividing ratio of setting, and then exports with low frequency signal;
According to identical every address date, the opposite form of neighbor address data step-by-step carries out the data pre-storage storage, according to the address saltus step outputting data signals Dm～D0 of described address scan signal in the described non-volatility memorizer.
2. circuit as claimed in claim 1, it is characterized in that: the saltus step speed of described address scan signal determines that by outside input clock frequency v the frequency dividing ratio k of described programmable frequency divider sets in advance; The low frequency signal frequency of this programmable frequency divider output is determined by function f (v, k).
3. circuit as claimed in claim 1, it is characterized in that: the frequency that improves outside input clock can be measured the maximum reading speed of non-volatility memorizer.
4. circuit as claimed in claim 1, it is characterized in that: select circuit to select bit data signals different among the data-signal Dm～D0 of non-volatility memorizer output as the signal of programmable frequency divider input by institute's rheme, repeat to test the speed difference that can draw between each data bit signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210092948.5A CN103366824B (en) | 2012-03-31 | 2012-03-31 | Non-volatility memorizer reading speed test circuit |
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| CN201210092948.5A CN103366824B (en) | 2012-03-31 | 2012-03-31 | Non-volatility memorizer reading speed test circuit |
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| CN103366824A true CN103366824A (en) | 2013-10-23 |
| CN103366824B CN103366824B (en) | 2016-02-10 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106297893A (en) * | 2016-08-01 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | The clock circuit of memorizer measuring circuit and method for designing thereof |
| CN111696617A (en) * | 2020-05-28 | 2020-09-22 | 上海华虹宏力半导体制造有限公司 | Non-volatile memory read data speed test circuit and test method |
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| US48856A (en) * | 1865-07-18 | Sash-fastener | ||
| US20090044062A1 (en) * | 2004-06-11 | 2009-02-12 | Seung-Man Shin | Method of testing a memory module and hub of the memory module |
| US20090207678A1 (en) * | 2008-02-20 | 2009-08-20 | Chih-Wei Chen | Memory writing interference test system and method thereof |
| CN101937721A (en) * | 2010-08-04 | 2011-01-05 | 武汉天喻信息产业股份有限公司 | Method for testing memory device |
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2012
- 2012-03-31 CN CN201210092948.5A patent/CN103366824B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US48856A (en) * | 1865-07-18 | Sash-fastener | ||
| US20090044062A1 (en) * | 2004-06-11 | 2009-02-12 | Seung-Man Shin | Method of testing a memory module and hub of the memory module |
| US20090207678A1 (en) * | 2008-02-20 | 2009-08-20 | Chih-Wei Chen | Memory writing interference test system and method thereof |
| CN101937721A (en) * | 2010-08-04 | 2011-01-05 | 武汉天喻信息产业股份有限公司 | Method for testing memory device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106297893A (en) * | 2016-08-01 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | The clock circuit of memorizer measuring circuit and method for designing thereof |
| CN106297893B (en) * | 2016-08-01 | 2019-04-09 | 上海华虹宏力半导体制造有限公司 | The clock circuit and its design method of memory measuring circuit |
| CN111696617A (en) * | 2020-05-28 | 2020-09-22 | 上海华虹宏力半导体制造有限公司 | Non-volatile memory read data speed test circuit and test method |
| CN111696617B (en) * | 2020-05-28 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Nonvolatile memory reading speed test circuit and test method |
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| CN103366824B (en) | 2016-02-10 |
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