CN107622785B - Method and system for measuring data reading time of embedded memory - Google Patents

Method and system for measuring data reading time of embedded memory Download PDF

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CN107622785B
CN107622785B CN201610560548.0A CN201610560548A CN107622785B CN 107622785 B CN107622785 B CN 107622785B CN 201610560548 A CN201610560548 A CN 201610560548A CN 107622785 B CN107622785 B CN 107622785B
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data
memory
locked loop
phase
built
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CN107622785A (en
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彭增发
郑坚斌
张帅奇
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展讯通信(上海)有限公司
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Abstract

The invention provides a method and a system for measuring data reading time of an embedded memory. The method comprises the following steps: the built-in automatic test controller receives a reset signal sent by an external test machine, sends an initial frequency adjustment configuration bit to a phase-locked loop and sends reference data to the data comparator; the phase-locked loop generates a phase-locked loop clock signal; the clock frequency divider generates a clock signal for the memory operation and a clock signal for the data latch operation; the data latch receives the initial read data of the memory, and outputs the initial read data of the memory to the data comparator; the data comparator compares the reference data with the initial read data, and if the reference data is consistent with the initial read data, a test passing signal is sent to an external test machine; the external test machine sends a new reset signal; the foregoing process is repeated until the reference data and the read data of the memory are not consistent, the data read time of the memory being half of the period of the latest phase-locked loop clock signal. The invention can reduce the area of the chip and the cost of the chip.

Description

Method and system for measuring data reading time of embedded memory

Technical Field

The invention relates to the technical field of embedded memories, in particular to a method and a system for measuring data reading time of an embedded memory.

Background

The method for measuring the data reading time of the embedded memory by the existing built-in measuring circuit comprises the following steps: the test machine presets a test mode, starts a time sequence test mode, the internal of the chip writes data into all or some memory cells corresponding to the addresses of the selected embedded memory, then reads the memory cells with the written data, and changes the selectable bits of the time delay circuit through the external machine, so as to adjust the internal time delay circuit, control the time of the clock entering the memory and the time of the data latch capturing the data output of the memory, and the time period from the rising edge of the memory clock to the time of the latch capturing the correct data of the memory is the data reading time of the embedded memory.

In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:

although the method for measuring the data reading time of the embedded memory by the built-in delay circuit can achieve higher accuracy, once the number of the measured memory instances is large (usually, the number of the embedded memories in a system on a chip is as small as hundreds, and as large as thousands), the consumed chip area is large because one or more delay circuits are required to be arranged around each measured memory instance.

Disclosure of Invention

The method and the system for measuring the data reading time of the embedded memory can reduce the area of the chip and reduce the cost of the chip.

In a first aspect, the present invention provides a system for measuring data reading time of an embedded memory, including: a built-in automatic test controller, a phase locked loop, a clock divider, a data latch, and a data comparator, wherein,

the built-in automatic test controller is used for receiving a reset signal sent by an external test machine, generating an initial frequency adjustment configuration bit, sending the initial frequency adjustment configuration bit to the phase-locked loop and sending the generated reference data to the data comparator;

the phase-locked loop is used for generating a phase-locked loop clock signal used by the built-in automatic test controller and the clock frequency divider;

the clock frequency divider is used for generating a clock signal for the work of the memory and a clock signal for the work of the data latch according to a phase-locked loop clock signal, and when the clock signal for the work of the memory is a rising edge, the memory obtains initial read data;

the data latch is used for receiving initial read data of the memory and a working signal of the data latch, locking the initial read data of the memory when a clock signal for working the data latch is a rising edge, outputting the initial read data of the memory, and then sending the initial read data to the data comparator;

the data comparator is used for comparing the reference data with the initial read data of the memory, and if the reference data and the initial read data are consistent, sending a test passing signal to an external test machine and the built-in automatic test controller;

the built-in automatic test controller is further configured to receive a test pass signal sent by the data comparator, adjust the initial frequency adjustment configuration bit, and send the adjusted initial frequency adjustment configuration bit to the phase-locked loop again, where the phase-locked loop, the clock divider, the data latch, and the data comparator are further configured to repeatedly perform the above actions until the reference data and the read data of the memory are inconsistent, and at this time, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop.

Optionally, the data comparator is further configured to send a test failure signal to the external test machine and the built-in automatic test controller when a result of comparing the reference data with the initial read data of the memory is inconsistent;

the built-in automatic test controller is also used for receiving a test failure signal sent by the data comparator, adjusting the initial frequency adjustment configuration bit and then sending the adjusted initial frequency adjustment configuration bit to the phase-locked loop again;

the phase-locked loop, the clock frequency divider, the data latch and the data comparator are further configured to repeatedly perform the above actions until the reference data and the read data of the memory are consistent, and at this time, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop.

Optionally, when there are multiple memories inside the chip to be tested, the built-in automatic test controller, the phase-locked loop, the clock divider, the data latch, and the data comparator are shared by the multiple memories.

In a second aspect, the present invention provides a method for measuring data reading time of an embedded memory, including:

the built-in automatic test controller receives a reset signal sent by an external test machine, generates an initial frequency adjustment configuration bit, sends the initial frequency adjustment configuration bit to a phase-locked loop and sends generated reference data to a data comparator;

the phase-locked loop generates a phase-locked loop clock signal used by the built-in automatic test controller and the clock frequency divider;

the clock frequency divider generates a clock signal for the work of the memory and a clock signal for the work of the data latch according to a clock signal of the phase-locked loop, and when the clock signal for the work of the memory is a rising edge, the memory obtains initial read data;

the data latch receives initial read data of the memory and a working signal of the data latch, locks the initial read data of the memory when a clock signal for working the data latch is a rising edge, outputs the initial read data of the memory, and then sends the initial read data to the data comparator;

the data comparator compares the reference data with the initial read data of the memory, and if the reference data and the initial read data are consistent, a test passing signal is sent to an external test machine and a built-in automatic test controller;

the built-in automatic test controller receives a test passing signal sent by the data comparator, adjusts the initial frequency adjustment configuration bit and then sends the adjusted signal to the phase-locked loop, and the phase-locked loop, the clock frequency divider, the data latch and the data comparator repeat the cycle process until the reference data and the read data of the memory are inconsistent, and at the moment, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop.

Optionally, the method further comprises:

if the result of comparing the reference data with the initial read data of the memory by the data comparator is inconsistent, sending a test failure signal to an external test machine and a built-in automatic test controller;

the built-in automatic test controller receives a test failure signal sent by the data comparator, adjusts the initial frequency adjustment configuration bit and then sends the adjusted initial frequency adjustment configuration bit to the phase-locked loop again;

and repeating the cycle process by the phase-locked loop, the clock frequency divider, the data latch and the data comparator until the reference data is consistent with the read data of the memory, wherein the data reading time of the memory is half of the clock signal period of the latest phase-locked loop.

Optionally, when there are multiple memories inside the chip to be tested, the built-in automatic test controller, the phase-locked loop, the clock divider, the data latch, and the data comparator are shared by the multiple memories.

According to the method and the system for measuring the data reading time of the embedded memory, provided by the embodiment of the invention, the built-in automatic test controller receives a reset signal sent by an external test machine, sends an initial frequency adjustment configuration bit to a phase-locked loop, and sends reference data to a data comparator; the phase-locked loop generates a phase-locked loop clock signal; the clock frequency divider generates a clock signal for the memory operation and a clock signal for the data latch operation; the data latch receives the initial read data of the memory, and outputs the initial read data of the memory to the data comparator; the data comparator compares the reference data with the initial read data, and if the reference data is consistent with the initial read data, the data comparator sends a test passing signal to an external test machine and the built-in automatic test controller; the built-in automatic test controller receives a test passing signal sent by the data comparator, adjusts the initial frequency adjustment configuration bit and then sends the adjusted signal to the phase-locked loop, and the phase-locked loop, the clock frequency divider, the data latch and the data comparator repeat the cycle process until the reference data and the read data of the memory are inconsistent, and at the moment, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop. Compared with the prior art, the invention improves the precision of measuring the data reading time of the embedded memory by the built-in automatic test system, simultaneously cancels the time delay circuit which is arranged at the periphery of the memory and is used for testing the data reading time of the memory by fully utilizing the phase-locked loop of the test chip, and shares the built-in automatic test controller, the phase-locked loop, the clock frequency divider, the data latch and the data comparator with a plurality of memories, thereby reducing the area of the chip and the cost of the chip.

Drawings

FIG. 1 is a flowchart illustrating a method for measuring data read time of an embedded memory according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating an operation of a clock divider generating a clock signal according to an embodiment of the present invention;

FIG. 3 is a block diagram illustrating a system for measuring data read time of an embedded memory according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The invention provides a method for measuring data reading time of an embedded memory, as shown in fig. 1 and fig. 3, the method comprises the following steps:

s11, the built-in automatic test controller receives a RESET signal (RESET) sent by an external test machine, generates an initial frequency adjustment configuration bit (Opt [ X:0]), sends the initial frequency adjustment configuration bit (Opt [ X:0]) to a phase-locked loop, and sends the generated reference DATA (REF _ DATA) to a DATA comparator;

optionally, the built-in automatic test controller also receives a clock signal (EX _ CLK) and an enable signal (BIST _ EN) sent by an external test machine, and receives a comparison result signal (Pass/Fail Flag) generated by the data comparator; generating an (Opt [ X:0]) signal to adjust the output clock frequency of the phase-locked loop and to generate a phase-locked loop enable signal (PLL _ EN); generating a chip selection signal (CEB), a write enable signal (WEB) and a read enable signal (REB), an address input bus (ADDR) and a data input bus (DI) of the memory, and controlling the write and read operations of the memory; generating a Reset Signal (RST) and an enable signal (CLK _ EN) of the clock divider; reference DATA (REF _ DATA) for DATA comparison and a DATA comparator enable signal (COMP _ EN) are generated.

S12, generating a phase-locked loop clock signal (PLL _ CLK) for the built-in automatic test controller and the clock frequency divider;

the phase-locked loop also receives a RESET signal (RESET) from an external test machine, a phase-locked loop enabling signal and a frequency adjustment configuration bit (Opt [ X:0]) which are sent by the built-in automatic test controller. S13, the clock frequency divider generates a clock signal (CKM) for the memory operation and a clock signal (CK _ LAT) for the data latch operation according to the phase-locked loop clock signal (PLL _ CLK), and when the clock signal (CKM) for the memory operation is a rising edge, the memory obtains initial read Data (DO);

the clock distributor also receives an enable signal (CLK _ EN) and a Reset Signal (RST) generated by the built-in automatic test controller.

Specifically, the clock signal generated by the clock divider operates as shown in fig. 2, when the clock signal (CKM) for the memory operation is a rising edge, the memory acquires the initial read Data (DO), and when the clock signal (CK _ LAT) for the data latch operation is a rising edge, the initial read Data (DO) of the memory is locked, and the read time of the memory is half of the time difference between the rising edge of CKM and the rising edge of CK _ LAT, i.e., half of the period of PLL _ CLK.

S14, the DATA latch receives the initial read DATA (DO) of the memory and the signal (CK _ LAT) of the DATA latch operation, when the clock signal (CK _ LAT) for the DATA latch operation is a rising edge, the initial read DATA (DO) of the memory is locked, and the initial read DATA (MEM _ DATA) of the memory is output and then sent to the DATA comparator;

s15, the DATA comparator compares the reference DATA (REF _ DATA) with the initial read DATA (MEM _ DATA) of the memory, and if the REF _ DATA and the initial read DATA (MEM _ DATA) are consistent, a test passing signal (Pass flag) is sent to an external test machine and a built-in automatic test controller;

the data comparator also receives a data comparator enable signal (COMP _ EN) sent by the built-in automatic test controller.

And S16, after receiving the test passing signal sent by the DATA comparator, the built-in automatic test controller adjusts (Opt [ X:0]) the initial frequency adjustment configuration bit and then sends the adjusted initial frequency adjustment configuration bit to the phase-locked loop, and the phase-locked loop, the clock frequency divider, the DATA latch and the DATA comparator repeat the cycle process until the reference DATA (REF _ DATA) and the read DATA (MEM _ DATA) of the memory are inconsistent, wherein the DATA reading time of the memory is half of the period of the latest phase-locked loop clock signal (PLL _ CLK).

Optionally, if the result of comparing the reference DATA (REF _ DATA) with the initial read DATA (MEM _ DATA) of the memory by the DATA comparator is inconsistent, sending a test Fail signal (Fail flag) to the external test machine and the built-in automatic test controller;

after receiving the test failure signal sent by the data comparator, the built-in automatic test controller adjusts the initial frequency adjustment configuration bit (Opt [ X:0]) and then sends the adjusted initial frequency adjustment configuration bit to the phase-locked loop again;

the phase locked loop, the clock divider, the DATA latch and the DATA comparator repeat the above cycle until the reference DATA (REF _ DATA) and the read DATA (MEM _ DATA) of the memory coincide, at which time the DATA read time of the memory is half of the period of the latest phase locked loop clock signal (PLL _ CLK).

Optionally, when a plurality of memories are arranged in the chip to be tested, the built-in automatic test controller, the phase-locked loop, the clock divider, the data latch and the data comparator are shared by the plurality of memories.

Because the output clock frequency of the phase-locked loop has a large adjustable range (generally, the frequency can be adjusted within the range from hundreds of MHz to several GHz, and the adjustable step length of each frequency is dozens of MHz), the method for measuring the data reading time of the embedded memory provided by the embodiment of the invention can be adopted, and the precision of the data reading time of the memory obtained by measurement can reach the level of 10 ps.

The method for measuring the data reading time of the embedded memory provided by the embodiment of the invention comprises the steps that a built-in automatic test controller receives a reset signal sent by an external test machine, sends an initial frequency adjustment configuration bit to a phase-locked loop and sends reference data to a data comparator; the phase-locked loop generates a phase-locked loop clock signal; the clock frequency divider generates a clock signal for the memory operation and a clock signal for the data latch operation; the data latch receives the initial read data of the memory, and outputs the initial read data of the memory to the data comparator; the data comparator compares the reference data with the initial read data, and if the reference data is consistent with the initial read data, the data comparator sends a test passing signal to an external test machine and the built-in automatic test controller; the built-in automatic test controller receives a test passing signal sent by the data comparator, adjusts the initial frequency adjustment configuration bit and then sends the adjusted signal to the phase-locked loop, and the phase-locked loop, the clock frequency divider, the data latch and the data comparator repeat the cycle process until the reference data and the read data of the memory are inconsistent, and at the moment, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop. Compared with the prior art, the invention improves the precision of measuring the data reading time of the embedded memory by the built-in automatic test system, simultaneously cancels the time delay circuit which is arranged at the periphery of the memory and is used for testing the data reading time of the memory by fully utilizing the phase-locked loop of the test chip, and shares the built-in automatic test controller, the phase-locked loop, the clock frequency divider, the data latch and the data comparator with a plurality of memories, thereby reducing the area of the chip and the cost of the chip.

An embodiment of the present invention further provides a system for measuring data reading time of an embedded memory, as shown in fig. 3, the system includes:

a built-in automatic test controller 11, a phase locked loop 12, a clock divider 13, a data latch 14 and a data comparator 15, wherein,

the built-in automatic test controller 11 is configured to receive a RESET signal (RESET) sent by an external test machine, generate an initial frequency adjustment configuration bit (Opt [ X:0]), send the initial frequency adjustment configuration bit (Opt [ X:0]) to a phase-locked loop, and send generated reference DATA (REF _ DATA) to the DATA comparator 15;

the phase-locked loop 12 is used for generating a phase-locked loop clock signal (PLL _ CLK) used by the built-in automatic test controller 11 and the clock frequency divider 13;

the clock divider 13 is used for generating a clock signal (CKM) for the memory operation and a clock signal (CK _ LAT) for the data latch 14 operation according to a phase-locked loop clock signal (PLL _ CLK), and when the clock signal (CKM) for the memory operation is a rising edge, the memory obtains initial read Data (DO);

the DATA latch 14 is configured to receive initial read DATA (DO) of the memory and a signal (CK _ LAT) of operation of the DATA latch 14, lock the initial read DATA (DO) of the memory when the clock signal (CK _ LAT) for operation of the DATA latch 14 is a rising edge, output the initial read DATA (MEM _ DATA) of the memory, and send the initial read DATA (MEM _ DATA) to the DATA comparator 15;

the DATA comparator 15 is used for comparing the reference DATA (REF _ DATA) with the initial read DATA (MEM _ DATA) of the memory, and if the REF _ DATA and the initial read DATA (MEM _ DATA) are consistent, sending a test passing signal (Pass flag) to an external test machine and the built-in automatic test controller 11; the built-in automatic test controller 11 is further configured to adjust (Opt [ X:0]) the initial frequency adjustment configuration bit after receiving a test Pass signal (Pass flag) sent by the DATA comparator, and then send the adjusted initial frequency adjustment configuration bit to the phase-locked loop 12 again, where the phase-locked loop 12, the clock divider 13, the DATA latch 14, and the DATA comparator 15 are further configured to repeat the aforementioned operations until the reference DATA (REF _ DATA) and the read DATA (MEM _ DATA) of the memory are inconsistent, and the DATA read time of the memory is half of the period of the latest phase-locked loop clock signal (PLL _ CLK).

Optionally, the DATA comparator 15 is further configured to send a test Fail signal (Fail flag) to the external test machine and the built-in automatic test controller 11 when the reference DATA (REF _ DATA) and the initial read DATA (MEM _ DATA) of the memory are inconsistent;

the built-in automatic test controller 11 is further configured to adjust the initial frequency adjustment configuration bits (Opt [ X:0]) and then send the adjusted initial frequency adjustment configuration bits to the phase-locked loop 12 again after receiving a test failure signal (Fail flag) sent by the data comparator;

the phase locked loop 12, the clock divider 13, the DATA latch 14 and the DATA comparator 15 are further configured to repeatedly perform the above-mentioned actions until the reference DATA (REF _ DATA) and the read DATA (MEM _ DATA) of the memory coincide, at which time the DATA read time of the memory is half of the period of the latest phase locked loop clock signal (PLL _ CLK).

Alternatively, when there are a plurality of memories inside the chip to be tested, the built-in automatic test controller 11, the phase locked loop 12, the clock divider 13, the data latch 14, and the data comparator 15 are common to the plurality of memories.

In the system for measuring the data reading time of the embedded memory provided by the embodiment of the invention, the built-in automatic test controller receives a reset signal sent by an external test machine, sends an initial frequency adjustment configuration bit to a phase-locked loop and sends reference data to the data comparator; the phase-locked loop generates a phase-locked loop clock signal; the clock frequency divider generates a clock signal for the memory operation and a clock signal for the data latch operation; the data latch receives the initial read data of the memory, and outputs the initial read data of the memory to the data comparator; the data comparator compares the reference data with the initial read data, and if the reference data is consistent with the initial read data, the data comparator sends a test passing signal to an external test machine and the built-in automatic test controller; the built-in automatic test controller receives a test passing signal sent by the data comparator, adjusts the initial frequency adjustment configuration bit and then sends the adjusted signal to the phase-locked loop, and the phase-locked loop, the clock frequency divider, the data latch and the data comparator repeat the cycle process until the reference data and the read data of the memory are inconsistent, and at the moment, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop. Compared with the prior art, the invention improves the precision of measuring the data reading time of the embedded memory by the built-in automatic test system, simultaneously cancels the time delay circuit which is arranged at the periphery of the memory and is used for testing the data reading time of the memory by fully utilizing the phase-locked loop of the test chip, and shares the built-in automatic test controller, the phase-locked loop, the clock frequency divider, the data latch and the data comparator with a plurality of memories, thereby reducing the area of the chip and the cost of the chip.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (4)

1. A system for measuring data read time of an embedded memory, comprising: a built-in automatic test controller, a phase locked loop, a clock divider, a data latch, and a data comparator, wherein,
the built-in automatic test controller is used for receiving a reset signal sent by an external test machine, generating an initial frequency adjustment configuration bit, sending the initial frequency adjustment configuration bit to the phase-locked loop and sending the generated reference data to the data comparator;
the phase-locked loop is used for generating a phase-locked loop clock signal used by the built-in automatic test controller and the clock frequency divider;
the clock frequency divider is used for generating a clock signal for the work of the memory and a clock signal for the work of the data latch according to a phase-locked loop clock signal, and when the clock signal for the work of the memory is a rising edge, the memory obtains initial read data;
the data latch is used for receiving initial read data of the memory and a working signal of the data latch, locking the initial read data of the memory when a clock signal for working the data latch is a rising edge, outputting the initial read data of the memory, and then sending the initial read data to the data comparator;
the data comparator is used for comparing the reference data with the initial read data of the memory, and if the reference data and the initial read data are consistent, sending a test passing signal to an external test machine and the built-in automatic test controller; the built-in automatic test controller is further configured to receive a test pass signal sent by the data comparator, adjust the initial frequency adjustment configuration bit, and send the adjusted initial frequency adjustment configuration bit to the phase-locked loop again, and the phase-locked loop, the clock divider, the data latch, and the data comparator are further configured to repeatedly execute the above actions until the reference data and the read data of the memory are inconsistent, where data reading time of the memory is half of a clock signal period of the latest phase-locked loop at this time;
the data comparator is also used for sending a test failure signal to an external test machine and the built-in automatic test controller when the comparison result of the reference data and the initial read data of the memory is inconsistent;
the built-in automatic test controller is also used for receiving a test failure signal sent by the data comparator, adjusting the initial frequency adjustment configuration bit and then sending the adjusted initial frequency adjustment configuration bit to the phase-locked loop again;
the phase-locked loop, the clock frequency divider, the data latch and the data comparator are further configured to repeatedly perform the above actions until the reference data and the read data of the memory are consistent, and at this time, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop.
2. The system of claim 1, wherein when there are multiple memories inside the chip to be tested, the built-in automatic test controller, the phase locked loop, the clock divider, the data latch, and the data comparator are common to the multiple memories.
3. A method for measuring data reading time of an embedded memory is characterized by comprising the following steps:
the built-in automatic test controller receives a reset signal sent by an external test machine, generates an initial frequency adjustment configuration bit, sends the initial frequency adjustment configuration bit to a phase-locked loop and sends generated reference data to a data comparator;
the phase-locked loop generates a phase-locked loop clock signal used by the built-in automatic test controller and the clock frequency divider;
the clock frequency divider generates a clock signal for the work of the memory and a clock signal for the work of the data latch according to a clock signal of the phase-locked loop, and when the clock signal for the work of the memory is a rising edge, the memory obtains initial read data;
the data latch receives initial read data of the memory and a working signal of the data latch, locks the initial read data of the memory when a clock signal for working the data latch is a rising edge, outputs the initial read data of the memory, and then sends the initial read data to the data comparator;
the data comparator compares the reference data with the initial read data of the memory, and if the reference data and the initial read data are consistent, a test passing signal is sent to an external test machine and a built-in automatic test controller; the built-in automatic test controller receives a test passing signal sent by the data comparator, adjusts the initial frequency adjustment configuration bit and then sends the adjusted signal to the phase-locked loop, and the phase-locked loop, the clock frequency divider, the data latch and the data comparator repeat the cycle process until the reference data and the read data of the memory are inconsistent, and at the moment, the data reading time of the memory is half of the clock signal period of the latest phase-locked loop;
if the result of comparing the reference data with the initial read data of the memory by the data comparator is inconsistent, sending a test failure signal to an external test machine and a built-in automatic test controller; the built-in automatic test controller receives a test failure signal sent by the data comparator, adjusts the initial frequency adjustment configuration bit and then sends the adjusted initial frequency adjustment configuration bit to the phase-locked loop again;
and repeating the cycle process by the phase-locked loop, the clock frequency divider, the data latch and the data comparator until the reference data is consistent with the read data of the memory, wherein the data reading time of the memory is half of the clock signal period of the latest phase-locked loop.
4. The method of claim 3, wherein when there are multiple memories inside the chip to be tested, the built-in automatic test controller, the phase locked loop, the clock divider, the data latch, and the data comparator are common to the multiple memories.
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