KR100920179B1 - Memory controller - Google Patents

Abstract

PURPOSE: A memory controller is provided to be stably operated till frequency of 166MHz by automatically controlling a skew between an external memory and a memory controller. CONSTITUTION: A memory controller includes a mode register block(10), a frequency/clock skew generating block(20), a clock frequency generating block(30), a read clock signal generating block(50), a write clock signal generating block(60), a data generating block(40), a test SDRAM signal generation/write read data comparing block(80), and an SDRAM signal selecting block(70). The mode register block sets an operation mode of an SDRAM memory controller. The frequency/clock skew generating block generates a clock frequency, a read clock skew, and a write clock skew according to setting of the mode register block. The clock frequency generating block receives a clock signal and a clock frequency, and generates a first clock signal and a second clock signal. The read clock signal generating block receives the first clock signal and the read clock skew, and generates a read clock signal. The write clock signal generating block receives the second clock signal and the write clock skew, and generates a write clock signal. The data generating block generates a write data by a write selecting signal or generates a read data after receiving the read clock signal. The SDRAM signal selecting block receives an SDRAM signal, a test SDRAM signal, and a comparing end signal, and selects a final SDRAM signal.

Description

Memory Controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a memory controller for automatically adjusting a skew between an external memory and a memory controller unit (MCU).

As the speed of the system bus, which refers to the passage between the RAM and the CPU of the computer, increases to over 100 MHz, the clock skew between the external memory and the memory controller unit is controlled. It is necessary to operate stably.

1 is a diagram illustrating a memory controller of the related art. In FIG. 1, the SRAM Controller 100 and the SDRAM 200 are represented, and the clock signal CLK is provided separately from the data path. The HCLK clock is used to write (WRITE) and read (READ) data between the memory controller 100 and the SDRAM 200.

The SDRAM CONTROL SIGNAL BLOCK 110 shown in FIG. 1 generates a signal used for the SDRAM operation, and generates signals such as CAS, RAS, WE, and ADDR of the SDRAM. These signals are OUTPUT signals that are passed to the external SDRAM memory (not shown) through the memory controller external port (not shown), and the SDLK clock signal CLK, which is made by the HCLK clock signal, is passed through the delay signal generation block (DELAY GENERATION block) 130. Synchronized by (HCLK_D).

The write / read data generation block 120 shown in FIG. 1 sends the write data WDATA to the SDRAM data signal DQ 220 by the write select signal WRITE. A block used to make the read signal DQ_D received from the SDRAM data signal DQ 220 into read data RDATA.

Here, the write data WDATA is transmitted to the SDRAM data signal DQ 220, and is synchronized by the SDRAM clock signal CLK 230, and the read data RDATE is the read signal DQ_D as the delay signal generation block 130. Are synchronized by the HCLK clock signal HCLK_D delayed by

As a result, the SDRAM control signal, the write data, and the read data are all controlled by the clock signal HCLK. In a high performance memory controller above 100MHz, it is very difficult to write and read by one clock at the same time, which can be impossible in some cases.

FIG. 2 is an SDRAM READ timing diagram by the memory controller of FIG. 1.

As shown in Fig. 2A, the SDRAM read data DQ is generated by the SDRAM clock signal CLK made by the timing delay of the clock signal HCLK. In general SDRAM, the time from CLK rising edge (marked by arrow in CLK) to DQ data is about 5 ~ 7ns, and read data DQ makes DQ_D data through wire time delay.

Referring back to FIG. 1, the data DQ and the clock HCLK_D generate the read data RDATA through the flip-flop F / F of the write / read data generation block 120. However, not only a model that accurately predicts the timing delay can be produced, but also a large variation may occur depending on the process, and it is very difficult to make HCLK_D securing a data setup margin as shown in B of FIG. 2.

In case the timing of the clock HCLK_D does not match due to an unexpected parameter such as a process, the METAL OPTION is set as shown in the delay signal generation block 130 of FIG. 1. It is a method to secure accurate timing through Metal Revision, but the TTM (Time To Market) by Metal Revision becomes long and additional process cost is required.

In addition, since the read clock and the write clock are the same, the write clock is modified due to the SDRAM read timing adjustment by the above method. This causes a problem in the SDRAM data write operation.

Therefore, a special device that can control the skew between the synchronous memory and the memory controller such as SDRAM is required.

In order to solve the above problems, the present invention has developed a device that can control the SDRAM write / read clocks of the conventional memory controller without reprocessing, eliminating the reprocessing using metal options, and chip It is to provide a device that automatically adjusts the skew between the external memory and the memory controller to reduce the loss in production. In addition, the present invention provides a memory controller that stably operates up to a frequency of 166 MHz by automatically adjusting the skew between the external memory and the memory controller.

Memory controller according to the present invention for solving the above problems,

A mode register block for setting an operation mode of the SDRAM memory controller; A frequency & clock skew generation block for generating a clock frequency Sek_C_M, a read clock skew Sek_C_R, and a write clock skew Sek_C_W according to the setting of the mode register block; A clock frequency generation block receiving a clock signal HCLK and the clock frequency Sek_C_M to generate a first clock signal HCLK_1 and a second clock signal HCLK_2; A read clock signal generation block configured to receive the first clock signal HCLK_1 and a read clock skew Sek_C_R to generate a read clock signal HCLK_R; A write clock signal generation block configured to receive the second clock signal HCLK_2 and a write clock skew Sek_C_W to generate a write clock signal HCLK_W; A data generation block generating write data by a write select signal WRITE, or generating read data by receiving the read clock signal HCLK_R; Test SDRAM signal generation & write read data receiving the clock frequency Sek_C_M, read clock skew Sek_C_R, and write clock skew Sek_C_W to generate write data, a test SDRAM signal, and a compare end signal. Comparison block; And an SDRAM signal selection block receiving the SDRAM signal, the test SDRAM signal, and the comparison end signal to select the final SDRAM signal, wherein the comparison end signal generated in the test SDRAM signal generation & write read data comparison block By changing the clock frequency (Sek_C_M), read clock skew (Sek_C_R), and write clock skew (Sek_C_W) generated in the frequency & clock skew generation block, the SDRAM is tested to find a suitable clock.

Here, in the mode register block, modes are classified into first to fourth modes (00, 01, 10, and 11), the first mode uses a phase locked loop clock generator (PLL), and the second mode is A prescaler clock divider is used, and the third mode uses the clock frequency as an external clock frequency and automatically adjusts only the clock skew, and the fourth mode uses a clock frequency and a clock skew specified by the user. It features.

In addition, the frequency & clock skew generation block,

A selection generation block for sequentially changing the clock frequency, write clock skew, and read clock skew by the comparison end signal; a signal output from the selection generation block, a final SDRAM signal, and a user-specified clock; And a multiplexer that receives the frequency and clock skew to select the appropriate clock frequency, read clock skew, and write clock skew.

In addition, the clock frequency generation block,

A phase locked loop clock generator PLL that receives a clock frequency Sek_C_M and a clock signal HCLK, a prescaler clock divider that receives a clock frequency Sek_C_M and a clock signal HCLK, and the phase locked And a multiplexer configured to receive a signal output from a loop clock generator (PLL) and a prescaler clock divider to generate a clock frequency.

In addition, the data generation block,

A buffer for generating write data WDATA by the write select signal WRITE and transmitting it to an external SDRAM data signal DQ, and receiving and reading a read clock signal HCLK_R and a signal DQ_D received from the SDRAM data signal DQ. And flip-flops (F / F) for generating data.

The read clock signal generation block may further include a delay cell for artificially generating a delayed clock skew, a read clock skew Sek_C_R, and first clock signals HCLK_1 delayed by the delay cell. And a multiplexer for selecting a suitable first clock signal to generate a read clock signal HCLK_R.

The write clock signal generation block may further include a delay cell for artificially generating a delayed clock skew, a write clock skew Sek_C_W, and second clock signals HCLK_2 delayed by the delay cell. And a multiplexer for selecting a suitable second clock signal to generate the write clock signal HCLK_W.

In addition, the test SDRAM signal generation & write read data comparison block,

A test result storage memory for storing the clock frequency Sek_C_M, the read clock skew Sek_C_R, and the write clock skew Sek_C_W, an SDRAM signal generation block for transferring write data and a test SDRAM signal to the SDRAM, read data and the Write read data comparison block that compares write data and transmits a compare end signal to the SDRAM signal generation block and the frequency & clock skew generation block, and finally a suitable clock frequency (Sek_C_M) and read clock skew (Sek_C_R). And a frequency and clock skew determination block for determining the write clock skew Sek_C_W.

The memory controller according to the present invention as described above may be used to adjust the clock skew between the memory controller chip and the external synchronous memory when designing a memory controller that supports synchronous memory such as SDRAM outside the chip.

In the conventional case, when the clock skew is not correct, a desired chip may be produced through a reprocessing process using a metal option, etc. However, according to the memory controller according to the present invention, the setup margin of the clock skew is set by register setting without reprocessing. There is an effect that can be secured, and through this, it is possible to operate stably up to a maximum frequency of 166MHz SDRAM.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; First, it should be noted that the same components or parts in the drawings represent the same reference numerals as much as possible. In describing the present invention, detailed descriptions of related well-known functions or configurations are omitted in order not to obscure the gist of the present invention.

3 is a diagram illustrating a memory controller according to the present invention, FIG. 4 is a diagram illustrating a mode in a mode register block of a memory controller according to the present invention, and FIG. 5 is a frequency & clock skew generation block of a memory controller according to the present invention. 6 shows a clock frequency generation block of the memory controller according to the present invention, FIG. 7 shows a data generation block of the memory controller according to the present invention, and FIG. 9 is a block diagram illustrating a read clock signal generation block of a memory controller. FIG. 9 is a diagram illustrating a write clock signal generation block of a memory controller according to the present invention. FIG. 10 is a block diagram illustrating an SDRAM signal selection block of a memory controller according to the present invention. FIG. 11 illustrates a test SDRAM signal generation & write read data comparison block of a memory controller according to the present invention. FIG. 12 illustrates a frequency and a clock. FIG. 13 is a diagram illustrating a process of finally determining a read clock skew Sek_C_R and a write clock skew Sek_C_W in a queue determination block. FIG. 13 is a diagram illustrating a write timing diagram of a memory controller according to the present invention. A read timing diagram of a memory controller according to the invention is shown.

It is very difficult to accurately match the clock skew between the external memory and the memory controller. You need to find a clock that satisfies both the read and write data, and this must be taken into account as the skew varies with frequency.

Referring to FIG. 3, the read and write clocks of the memory are divided into signals of the read clock signal HCLK_R and the write clock signal HCLK_W to enable the write and read clocks to operate independently. In addition, a clock frequency generation block 30 is used to adjust the frequency.

Looking at the overview of the operation, when the operation mode is set to the normal mode in the mode register block (10), the frequency & clock skew generation block (Frequency & Clock Skew Declaration Block) 20 The algorithm generates a clock frequency Sek_C_M, a write clock skew Sek_C_W, and a read clock skew Sek_C_R.

The clock frequency generation block 30 may receive the clock signal HCLK and the clock frequency Sek_C_M and adjust the frequency from a low frequency to a high frequency. Here, the low frequency typically means a range of 1 to 10 MHz, and the high frequency is 133 MHz or 166 MHz as a high frequency of a general SDRAM. The same applies to the following.

The clock signal generated by the clock frequency generation block 30 is a read clock generation block 50 and a write clock generation block 60. The first clock signal HCLK_1, Each enters the second clock signal HCLK_2.

The write clock signal generation block 60 receives the second clock signal HCLK_2 and the write clock skew Sek_C_W signal to generate the write clock signal HCLK_W with the clock skew adjusted, and finally the write clock signal HCLK_W Used as a memory write clock.

The read clock signal generation block 50 receives the first clock signal HCLK_1 and the read clock skew Sek_C_R signal to generate the read clock signal HCLK_R with the clock skew adjusted. Finally, the read clock signal HCLK_R Used as a read clock in memory.

Eventually, the compare end signal (Compare Done) of the test SDRAM signal generation & write read data comparison block (Test SDRAM Signal Generation & WDATA, RDATA Comparison) 80 is used to view the clock frequency generated by the frequency & clock skew generation block 20. By changing the (Sek_C_M), write clock skew (Sek_C_W), and read clock skew (Sek_C_R) signals, the SDRAM is tested to find an optimal clock.

4 illustrates a mode register block of the memory controller of FIG. 3.

In the mode register block 10, a mode is classified into first to fourth modes (00, 01, 10, and 11 modes), and the first mode (00 mode) (hereinafter, '00') is a phase. A fixed loop clock generator (PLL) is used, the second mode (01 mode) (hereinafter '01') uses a prescaler clock divider, and the third mode (10 mode) (hereinafter '10'). ) Uses the clock frequency as an external clock frequency and automatically adjusts only the clock skew, and the fourth mode (11 modes) (hereinafter '11') uses a clock frequency and a clock skew specified by the user.

The mode register block 10 may automatically calculate the value set in the SDRAM controller by setting the operation mode to '00' or '01'. The difference between '00' and '01' is whether the clock frequency uses a PLL or a prescaler. The PLL is a block that changes the current clock to high frequencies, and the Prescaler is a block that changes the current clock to low frequencies.

If the clock supplied to the SDRAM controller is high frequency, the clock skew can be found by converting to low frequency using the Prescaler. If the clock is low frequency, the clock skew can be found by converting to high frequency using the PLL. When the mode is set to '10', the clock frequency uses the external clock frequency as it is and decides whether to use automatic clock skew adjustment. Finally, if the mode is set to '11', the user can set the clock frequency and clock skew, and the clock frequency and clock skew are determined by the user defined input signal.

FIG. 5 shows details of the frequency & clock skew generation block of FIG. 3.

The frequency & clock skew generation block 20 includes a selection generation block 21 for sequentially changing a clock frequency, a write clock skew, and a read clock skew by a compare end signal, and the selection generation. Select the appropriate clock frequency, read clock skew, and write clock skew by receiving the signal (Test Selection), the final SDRAM signal (Final Selection), and the user-defined input signal (User Defined Selection) output from block 21 It is configured to include a multiplexer (23).

The mode register block 10 does not automatically calculate the values that can be set in the SDRAM controller. Instead, the mode register block 10 sets user defined signals that allow the user to set clock frequency and clock skew. This register determines whether to set skew. Create & Write Test SDRAM Signal The compare end signal (Compare Done) generated by the data compare block 80 indicates completion of data write and read test through the SDRAM. ", The Sek_C_M, Sek_C_W, and Sek_C_R signals are changed by the selection generation block 21. The "Final Selection" signal is a signal generated in the test SDRAM signal generation & write read data comparison block 80, and refers to the Sek_C_M, Sek_C_W, and Sek_C_R signals that are finally determined after all verification is completed.

User Defined Selection is an input signal from the SDRAM controller that allows the user to set the clock frequency and clock skew arbitrarily, set it to a low frequency for testing, or use it for debugging.

6 illustrates the clock frequency generation block in detail.

As shown in FIG. 6, the clock frequency generation block 30 includes a phase locked loop clock generator (PLL) 31 that receives a clock frequency Sek_C_M and a clock signal HCLK, and a clock frequency Sek_C_M. A prescaler clock divider 32 that receives a clock signal HCLK, and a signal frequency generated by receiving signals output from the phase locked loop clock generator PLL and the prescaler clock divider to generate a clock frequency The flexure 33 is comprised.

The clock frequency signal Sek_C_M generated by the frequency & clock skew generation block 20 enters a phase locked loop clock generator (PLL) 31 and a prescaler clock divider 32 to change the clock frequency. If the phase locked loop clock generator (PLL) 31 and the prescaler clock divider 32 are not built in, or if the frequency is used as HCLK, the signal of the mode register 10 is set to '10' or '11'. ', The multiplexer 33 can bypass the clock signal HCLK.

Here, the phase locked loop clock generator (PLL) changes the current clock to a high frequency, and the prescaler clock divider 32 changes the current clock to a low frequency.

7 shows the data generation block in detail.

As shown in FIG. 7, the data generation block 40 includes a buffer 41 for generating write data WDATA from the write select signal WRITE and transmitting the write data WDATA to an external SDRAM data signal DQ, and a read clock signal. And a flip-flop (F / F) 42 which receives the HCLK_R and the signal DQ_D received from the SDRAM data signal DQ and generates read data.

That is, in the data generation block 40, the SDRAM write data WDATA_buf signal is generated by the WDATA and WRITE signals, and enters the external SDRAM as the DQ signal. The RDATA signal is generated by the SDRAM read data DQ_D and the HCLK_R signal. As a result, the data generation block shown in FIG. 7 is configured to use both read and write SDRAM data signals DQ.

8 shows a read clock signal generation block in detail.

As shown in FIG. 8, the read clock signal generation block 50 includes a delay cell 51 that artificially generates a delayed clock skew, a read clock skew Sek_C_R, and a delay cell 51. And after receiving the first clock signals HCLK_1 delayed by the multiplexer 52, the multiplexer 52 selects a suitable first clock signal and generates a read clock signal HCLK_R.

The multiplexer 52 input using the delay cell 51 can be increased or decreased in accordance with the accuracy demand of the user.

9 shows a write clock signal generation block in detail.

As illustrated in FIG. 9, the write clock signal generation block 60 includes a delay cell 61 for artificially generating a delayed clock skew, a write clock skew Sek_C_W, and a delay cell 61. After receiving the delayed second clock signal (HCLK_2), it comprises a multiplexer 62 to select the appropriate second clock signal to generate a write clock signal (HCLK_W). Like the read clock signal generation block, the input of the multiplexer 62 using the delay cell 61 can be increased or decreased in accordance with the accuracy request of the user.

10 shows the SDRAM signal selection block in detail.

The SDRAM signal selection block 70 is a block for selecting an SDRAM signal. SDRAM signal is a signal such as CAS, RAS, WE, ADDR, etc. In Figure 10, the SDRAM signal is a signal for actual operation, the test SDRAM signal (Test SDRAM Signal) is a signal used in the test to adjust the clock skew. . If a test test is performed to find the clock skew, the test SDRAM signal is output as the final signal by the final selection signal, and the SDRAM signal is output as the final signal when the clock skew test is completed.

11 illustrates a test SDRAM signal generation & write read data comparison block in detail.

As illustrated in FIG. 11, the test SDRAM signal generation & write read data comparison block 80 stores a test result for storing a clock frequency Sek_C_M, a read clock skew Sek_C_R, and a write clock skew Sek_C_W. A memory 81, an SDRAM signal generation block 82 for transferring write data and a test SDRAM signal to the SDRAM, and a compare end signal (Compare Done) by comparing read data with the write data; Determining the frequency and clock skew that determine the write read data comparison block 83 that is sent to the frequency & clock skew generation block, and finally determine the appropriate clock frequency (Sek_C_M), read clock skew (Sek_C_R), and write clock skew (Sek_C_W). Block 84.

The Mode Register, Sek_C_M, Sek_C_W, and Sek_C_R signals are received and stored in the test result storage memory (Memory For Test Result) 81. Thereafter, the SDRAM signal generation block 82 sends write data and a test SDRAM signal to the SDRAM. Next, the SDRAM signal generation block 82 sends an SDRAM write request signal, receives read data from the write data comparison block 83, compares the write data, and confirms whether the value is correct. After comparing the ring, a comparison end signal (Compare Done) and a comparison result signal (Compare Result) are sent to the SDRAM signal generation block 82. This result is transferred to the test result storage memory 81 and stored. The write read data comparison block 83 sends a compare end signal to the frequency & clock skew generation block 20 to generate new Sek_C_M, Sek_C_W, and Sek_C_R signals. Here, the write data generated by the SDRAM signal generation block 82 may not be repeated by using a random data generation unit.

The above values are repeated to finally determine the Sek_C_M, Sek_C_W, and Sek_C_R signals in the frequency and clock skew decision block 84.

FIG. 12 illustrates a process of finally determining read clock skew (Sek_C_R) and write clock skew (Sek_C_W) in the frequency and clock skew determination block. The test SDRAM signal generation & write read data comparison block of FIG. The method of finding the write clock skew (Sek_C_W) and the read clock skew (Sek_C_R) in the frequency and clock skew decision block 84 is shown.

First, the clock frequency signal Sek_C_M is changed from 1 MHz to 166 MHz, and the write clock skew Sek_C_W signal is changed to 0, 1, 2,... According to each clock frequency signal Sek_C_M. Change it. In each case, the read clock skew Sek_C_R is changed. Finally, the intermediate values of the write clock skew (Sek_C_W) and the read clock skew (Sek_C_R) signals when the SDRAM write read test is successful at all frequencies are used to determine the optimal setup and hold margins.

13 is a diagram illustrating a write timing diagram of a memory controller according to the present invention.

Compared to the timing diagram of the conventional memory controller (see FIG. 2), the difference is that four types of selectable output clock signals of the clock generation block are produced, HCLK_W1, HCLK_W2, HCLK_W3, and HCLK_W4, among which DQ DATA can be sampled. It is possible to select the correct signal using a delay cell. If you want to control clock timing more precisely, it is also possible to increase the output clock signal to four or more and freely adjust each clock interval.

14 is a diagram illustrating a read timing diagram of a memory controller according to the present invention.

Compared with the timing diagram of the conventional memory controller (see FIG. 2), the difference is that four types of selectable output clock signals of the clock generation block are made, HCLK_1, HCLK_2, HCLK_3, and HCLK_4, among which DQ_D DATA can be sampled. It is possible to select the correct signal using a multiplexer. If you want to control clock timing more precisely, it is also possible to increase the output clock signal to four or more and freely adjust each clock interval.

As described above with reference to the drawings illustrating a memory controller according to the present invention, the present invention is not limited by the embodiments and drawings disclosed herein, it is various within the technical scope of the present invention by those skilled in the art Of course, modifications can be made.

1 is a view showing a memory controller according to the prior art;

FIG. 2 is a timing diagram of the memory controller of FIG. 1;

3 is a view showing a memory controller according to the present invention;

4 is a diagram of modes in a mode register block of a memory controller in accordance with the present invention;

5 illustrates a frequency & clock skew generation block of a memory controller according to the present invention;

6 is a diagram illustrating a clock frequency generation block of a memory controller according to the present invention;

7 is a diagram illustrating a data generation block of a memory controller according to the present invention;

8 is a block diagram illustrating a read clock signal generation block of the memory controller according to the present invention;

9 is a block diagram illustrating a write clock signal generation block of the memory controller according to the present invention;

10 is a block diagram illustrating an SDRAM signal selection block of a memory controller according to the present invention;

11 is a block diagram illustrating a test SDRAM signal generation & write read data comparison block of a memory controller according to the present invention;

FIG. 12 illustrates a process of finally determining a read clock skew Sek_C_R and a write clock skew Sek_C_W in a frequency and clock skew determination block.

13 is a diagram illustrating a write timing diagram of a memory controller according to the present invention;

14 is a diagram illustrating a read timing diagram of a memory controller according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: Mode register block

20: Frequency & Clock Skew Declaration Block

30: Clock Frequency Generation Block

40: Data Generation Block

50: Read Clock Generation Block

60: Write Clock Generation Block

70: SDRAM Signal Selection Block

80: Test SDRAM Signal Generation & Write Data Comparison Block (Test SDRAM Signal Generation & WDATA, RDATA Comparison)

Claims (9)

A mode register block for setting an operation mode of the SDRAM memory controller; A frequency & clock skew generation block for generating a clock frequency Sek_C_M, a read clock skew Sek_C_R, and a write clock skew Sek_C_W according to the setting of the mode register block; A clock frequency generation block receiving a clock signal HCLK and the clock frequency Sek_C_M to generate a first clock signal HCLK_1 and a second clock signal HCLK_2; A read clock signal generation block configured to receive the first clock signal HCLK_1 and a read clock skew Sek_C_R to generate a read clock signal HCLK_R; A write clock signal generation block configured to receive the second clock signal HCLK_2 and a write clock skew Sek_C_W to generate a write clock signal HCLK_W; A data generation block generating write data by a write select signal WRITE, or generating read data by receiving the read clock signal HCLK_R; Test SDRAM signal generation & write read data receiving the clock frequency Sek_C_M, read clock skew Sek_C_R, and write clock skew Sek_C_W to generate write data, a test SDRAM signal, and a compare end signal. Comparison block; And, An SDRAM signal selection block receiving the SDRAM signal, the test SDRAM signal, and the comparison end signal to select the final SDRAM signal, The clock frequency Sek_C_M, the read clock skew Sek_C_R, and the write clock skew generated in the frequency & clock skew generation block are generated by the compare end signal generated in the test SDRAM signal generation & write read data comparison block. Sek_C_W) A memory controller that tests the SDRAM and finds a suitable clock by changing Sek_C_W). The method according to claim 1, In the mode register block, modes are classified into first to fourth modes (00, 01, 10, and 11), the first mode uses a phase locked loop clock generator (PLL), and the second mode is a prescaler ( prescaler) using a clock divider, the third mode uses the clock frequency as an external clock frequency and automatically adjusts the clock skew, and the fourth mode uses a clock frequency and a clock skew specified by the user. Memory controller. The method according to claim 1, The frequency & clock skew generation block, A selection generation block for sequentially changing the clock frequency, write clock skew, and read clock skew by the comparison end signal; A multiplexer that receives the signal output from the selection generation block, the final SDRAM signal, and a clock frequency and clock skew specified by the user to select an appropriate clock frequency, read clock skew, and write clock skew. Memory controller comprising a. The method according to claim 1, The clock frequency generation block, A phase locked loop clock generator (PLL) for receiving the clock frequency Sek_C_M and the clock signal HCLK, A prescaler clock divider for receiving the clock frequency Sek_C_M and the clock signal HCLK, A multiplexer which receives a signal output from the phase locked loop clock generator (PLL) and a prescaler clock divider to generate a clock frequency. Memory controller comprising a. The method according to claim 1, The data generation block, A buffer for generating write data WDATA by the write select signal WRITE and transmitting the write data WDATA to an external SDRAM data signal DQ; Flip-flop (F / F) for receiving read clock signal HCLK_R and signal DQ_D received from SDRAM data signal DQ to generate read data Memory controller comprising a. The method according to claim 1, The read clock signal generation block, A delay cell that artificially generates a delayed clock skew, And a multiplexer for receiving the read clock skew Sek_C_R and the first clock signal HCLK_1 delayed by the delay cell, and then selecting a suitable first clock signal to generate the read clock signal HCLK_R. A memory controller characterized by the above. The method according to claim 1, The write clock signal generation block, A delay cell that artificially generates a delayed clock skew, And a multiplexer configured to generate a write clock signal HCLK_W by receiving a write clock skew Sek_C_W and second clock signals HCLK_2 delayed by the delay cell, and then selecting a suitable second clock signal. Memory controller, characterized in that. The method according to claim 1, The test SDRAM signal generation & write read data comparison block, A test result storage memory for storing a clock frequency Sek_C_M, a read clock skew Sek_C_R, and a write clock skew Sek_C_W; An SDRAM signal generation block for transferring write data and a test SDRAM signal to the SDRAM; A write read data comparison block for comparing a read data with the write data and transmitting a compare end signal to the SDRAM signal generation block and the frequency & clock skew generation block; And a frequency and clock skew determination block for finally determining a suitable clock frequency (Sek_C_M), read clock skew (Sek_C_R), and write clock skew (Sek_C_W). The method according to claim 8, And write data generated by the SDRAM signal generation block (82) so that the same value is not repeated using a random data generation unit.

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