CN111370040B - Memory read data test circuit structure and design method thereof - Google Patents
Memory read data test circuit structure and design method thereof Download PDFInfo
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- CN111370040B CN111370040B CN202010190043.6A CN202010190043A CN111370040B CN 111370040 B CN111370040 B CN 111370040B CN 202010190043 A CN202010190043 A CN 202010190043A CN 111370040 B CN111370040 B CN 111370040B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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Abstract
The application relates to the technical field of semiconductor integrated circuits, in particular to a memory read data test circuit structure and a design method thereof. The structure comprises: a read signal path including a clock gating unit and a first combinational logic circuit unit; the clock end of the clock gating unit is connected with a synchronous clock signal; an address path including an address register unit, a logic control circuit unit, an address latch unit, and a second combinational logic circuit unit; the clock end of the address register unit is connected with the synchronous clock signal, the data output end of the address register unit is connected with the input end of the logic control circuit unit, the output end of the logic control circuit unit is connected with the data input end of the address latch unit, and the clock end of the address latch unit is connected with the synchronous clock signal. The synchronous clock is adopted by the read signal generating step, the address signal generating step and the address latching step, so that the problem that the high-precision time sequence balance is complex and difficult to ensure in the related technology can be solved.
Description
Technical Field
The application relates to the technical field of semiconductor integrated circuits, in particular to a memory read data test circuit structure and a design method thereof.
Background
The memory is the main medium for data storage in the computer, and the read-write speed of the memory greatly influences the working speed of the computer. In recent years, with the rapid development of internet technologies such as cloud computing, the requirement for the read-write speed of a memory is also increasing; and the memory data reading circuit is used for reading the data stored in the memory cells corresponding to the specific addresses according to the reading signals.
When reading data at a specific address according to a read signal, the time of the read signal transmitted on the read signal path reaching a memory is required to be consistent with the time of the address signal transmitted on the address path, namely, the time is balanced; once the time sequence deviation exists in the signals transmitted on the two paths, the time precision of the data reading of the memory is directly affected, and the time precision of the data reading is related to the working speed (namely the reading and writing speed) of the memory, for example, if the time precision of the data reading can be improved by 3ns, the working speed of the 50MHz frequency of the memory can be improved by about 15 percent.
However, in the memory read data test circuit in the related art, since the read signal path and the address path have more logic gates, signals of the read signal path and the address path need to be respectively processed by the logic control circuit after being generated, when the read signal and the address signal are time-sequence balanced, the stages of gates on the two paths need to be ensured to be the same, and the load hung by each logic gate output is the same, so that the time-sequence balance to ensure high precision is complex and difficult.
Disclosure of Invention
The application provides a memory read data test circuit structure and a design method thereof, which can solve the problems of complex and difficult time sequence balance ensuring high precision in the related technology.
In one aspect, an embodiment of the present application provides a memory read data test circuit structure, including:
the output end of the reading signal path is connected with the reading end of the memory; the read signal path includes a clock gating cell and a first combinational logic circuit cell; the clock end of the clock gating unit is connected with a synchronous clock signal; a read signal output from a gate output terminal of the clock gate unit is input to a read terminal of the memory through the first combinational logic circuit unit;
an address path, wherein the output end of the address path is connected with the address end of the memory; the address path comprises an address register unit, a logic control circuit unit, an address latch unit and a second combinational logic circuit unit; the clock end of the address register unit is connected with the synchronous clock signal, the data output end of the address register unit is connected with the input end of the logic control circuit unit, the output end of the logic control circuit unit is connected with the data input end of the address latch unit, and the clock end of the address latch unit is connected with the synchronous clock signal; an address signal output from an output terminal of the address latch unit is input to an address terminal of the memory through the second combinational logic circuit unit.
Optionally, the number, the type and the connection relation of the devices in the first combinational logic circuit unit are the same as the number, the type and the connection relation of the devices in the second combinational logic circuit unit.
Optionally, the first combinational logic circuit unit includes a first multi-way switch, a second multi-way switch, a first inverter and a second inverter;
the input end of the first multi-way switch is connected with the gate control output end of the clock gate control unit, the output end of the first multi-way switch is connected with one input end of the second multi-way switch, the output end of the second multi-way switch is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the reading end of the memory.
Optionally, the second combinational logic circuit unit includes a third multi-way switch, a fourth multi-way switch, a third inverter and a fourth inverter;
the input end of the third multi-way switch is connected with the output end of the address latch unit, the output end of the third multi-way switch is connected with one input end of the fourth multi-way switch, the output end of the fourth multi-way switch is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is connected with the address end of the memory.
Optionally, the difference between the first delay traversed by the read signal in the read signal path and the second delay traversed by the address signal in the address path is less than 1ns.
As a second aspect of the present application, there is provided a method of designing a memory read data test circuit structure, comprising:
providing a read signal path, and inputting a read signal to a read end of the memory; the read signal is sequentially output after passing through a read signal generation step and a combinational logic operation step in the read signal path;
providing an address path, and inputting an address signal to an address end of a memory;
the address signal is output after sequentially passing through an address signal generating step, a logic control step, an address latching step and a combined logic operation step in the address path;
the read signal generating step, the address signal generating step and the address latching step adopt synchronous clocks.
Optionally, the logic operation steps of the read signal passing through the read signal path are the same as the combinational logic operation steps of the address signal passing through the address path.
Optionally, a difference between a first delay traversed by the read signal in the read signal path and a second delay traversed by the address signal in the address path is less than 1ns.
The technical scheme of the application at least comprises the following advantages: the clock gating unit and the address latch receiving the synchronous clock signals can balance the time sequence deviation of the output signals of the two paths, and simultaneously avoid a complex time sequence balance process, so that the time deviation of establishing the address is reduced, and the time for establishing effective access of the memory is shortened.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a diagram of a memory read data circuit provided in the related art;
FIG. 2 is a timing diagram of a memory read data circuit structure provided by the related art;
FIG. 3 is a diagram of a memory read data test circuit according to the present application.
100. The application comprises a read signal path of the application, 110, a clock gating unit, 120, a first combinational logic circuit unit, 200, an address path of the application, 210, a second combinational logic circuit unit, 100A, a read signal path of the related art, 101A, a third combinational logic circuit unit, 102A, a read signal register, 200A, an address path of the related art, 201A, a fourth combinational logic circuit unit, 202A, and an address register.
Detailed Description
The following description of the embodiments of the present application will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Referring to fig. 1, a memory read data circuit structure provided for the related art includes a read signal path 100A and an address path 200A. The output end of the read signal path 100A is connected to the read end read of the memory NVM, and is used for inputting a read signal to the memory NVM; the output terminal of the address path 200A is connected to the address terminal AD of the memory NVM, for inputting address signals to the memory NVM.
Wherein the read signal path 100A comprises a read signal register 102A and a third combinational logic circuit cell 101A, and the address path 200A comprises an address register 202A and a fourth combinational logic circuit cell 201A; the read signal register 102A is used for registering a read signal, the address register 202A is used for registering an address signal, the synchronous clock signal CLK is respectively connected with the clock end of the read signal register 102A and the clock end of the address register 202A, the data output end of the read signal register 102A is connected with the third combinational logic circuit unit 101A, and the output end of the third combinational logic circuit unit 101A is connected with the read end read of the memory NVM; the data output terminal of the address register 202A is connected to the fourth combinational logic circuit unit 201A, and the output terminal of the fourth combinational logic circuit unit 201A is connected to the address terminal AD of the memory NVM. When the clock terminal of the read signal register 102A and the clock terminal of the address register 202A simultaneously receive the synchronous clock signal CLK, the data output terminal of the read signal register 102A and the data output terminal of the address register 202A can simultaneously output the read signal temporarily registered in the read signal register 102A and the address signal temporarily registered in the address register 202A to the third and fourth combination logic circuit units 101A and 201A, respectively.
When the circuit works, the generated time sequence is shown in fig. 2, wherein A is an address signal, READ is a READ signal, CLK is a synchronous clock signal, DOUT is an output signal when the memory NVM READs data, tar is a time deviation for establishing an address, taa is a time difference between when the memory NVM receives the READ signal and when the memory NVM starts to READ data, namely, the time for establishing effective access of the memory NVM; among other things, taa plays a decisive role in the read speed of the memory NVM.
However, for the third combinational logic circuit unit 101A and the fourth combinational logic circuit unit 201A, the timing balance needs to ensure that the stages of gates on the third combinational logic circuit unit 101A and the fourth combinational logic circuit unit 201A are the same, and the load hung by each logic gate output is the same; because the third combinational logic circuit unit 101A and the fourth combinational logic circuit unit 201A have more logic gates, the balancing is troublesome, the time sequence balancing circuit is more time-consuming, and errors are easy to occur, so that the address establishment time deviation Tar is larger, and the accuracy of the read data time is affected.
An embodiment of a first aspect of the present application provides a memory read data test circuit structure, including: read signal path 100 and address path 200.
The output end of the read signal path 100 is connected to the read end read of the memory NVM, and is used for inputting a read signal to the memory NVM; the read signal path 100 includes a clock gating cell 110 and a first combinational logic circuit cell 120; the clock end of the clock gating unit 110 is connected with a synchronous clock signal CLK; the read signal outputted from the gate output terminal CLKG of the clock gating unit 110 is inputted to the read terminal read of the memory NVM through the first combinational logic circuit unit 120. Wherein the output of the first combinational logic circuit cell 120 at any instant depends only on the input at that instant, independent of the original state of the circuit cell.
The output end of the address path 200 is connected with the address end AD of the memory NVM and is used for inputting address signals to the memory NVM; the address path 200 includes an address register unit addr_reg, a LOGIC control circuit unit LOGIC3, an address latch unit add_pl, and a second combinational LOGIC circuit unit 210. The address register unit addr_reg is used for temporarily registering address information, the clock end of the address register unit addr_reg is connected with the synchronous clock signal CLK, the data output end of the address register unit addr_reg is connected with the input end of the LOGIC control circuit unit LOGIC3, the output end of the LOGIC control circuit unit LOGIC3 is connected with the data input end of the address latch unit add_pl, and the clock end of the address latch unit add_pl is connected with the synchronous clock signal CLK; an address signal output from the output terminal of the address latch unit add_pl is input to the address terminal AD of the memory NVM through the second combinational logic circuit unit 210.
The clock gating unit 110 and the address latch receiving the synchronous clock signal CLK can balance the timing deviation of the two path output signals, and avoid a complex timing balance process, so that the time deviation Tar of establishing the address is reduced, and the time Taa for establishing the effective access of the memory NVM is shortened.
On the basis of the above-described embodiment, the number, type, and connection relationship of the devices in the first combinational logic circuit unit 120 are the same as those of the devices in the second combinational logic circuit unit 210. Referring to fig. 3, the first combinational logic circuit unit 120 includes a first multiplexing switch MUX1, a second multiplexing switch MUX2, a first inverter INV1, and a second inverter INV2.
The input end of the first multi-way switch MUX1 is connected to the gate output end CLKG of the clock gate unit 110, the output end of the first multi-way switch MUX1 is connected to an input end of the second multi-way switch MUX2, the output end of the second multi-way switch MUX2 is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is connected to the read end read of the memory NVM.
The second combinational logic circuit unit 210 includes a third multiplexing switch MUX3, a fourth multiplexing switch MUX4, a third inverter INV3, and a fourth inverter INV4;
the input end of the third multi-way switch MUX3 is connected to the output end of the address latch unit add_pl, the output end of the third multi-way switch MUX3 is connected to an input end of the fourth multi-way switch MUX4, the output end of the fourth multi-way switch MUX4 is connected to the input end of the third inverter INV3, the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, and the output end of the fourth inverter INV4 is connected to the address end AD of the memory NVM.
By the number, type and connection relationship of the devices in the first combinational logic circuit unit 120 being the same as the number, type and connection relationship of the devices in the second combinational logic circuit unit 210, the delays generated by the signals in the first combinational logic circuit unit 120 and the second combinational logic circuit unit 210 will also tend to be equal.
By the embodiment of the application, under the action of the synchronous clock signal CLK, the first delay generated in the process from generating the read signal to the read end reaching the memory NVM through the read signal path 100 and the second delay generated in the process from generating the address signal to the address end AD reaching the memory NVM through the address path 200 can be caused; the difference between the first delay and the second delay is within 1ns.
An embodiment of a second aspect of the present application provides a method for designing a memory read data test circuit structure, including:
providing a read signal path 100, inputting a read signal to a read end read of the memory NVM; the read signal is sequentially output after passing through a read signal generating step and a combinational logic operation step in the read signal path 100;
providing an address path 200, inputting an address signal to an address terminal AD of a memory NVM;
the address signal is sequentially output after passing through an address signal generating step, a logic control step, an address latching step and a combinational logic operation step in the address path 200;
the read signal generating step, the address signal generating step and the address latching step adopt synchronous clocks.
With the above embodiment, the logical operation steps that the read signal passes through in the read signal path 100 are the same as the combined logical operation steps that the address signal passes through in the address path 200.
The difference between the first delay that the read signal passes in the read signal path 100 and the second delay that the address signal passes in the address path 200 is less than 1ns.
In this embodiment, the read signal generating step, the address signal generating step and the address latching step adopt synchronous clocks, so that the time deviation of the output signals of the two paths can be balanced, and meanwhile, a complex time sequence balancing process is avoided, so that the time deviation Tar of establishing the address is reduced, and the time Taa for establishing the effective access of the memory NVM is shortened.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the application.
Claims (6)
1. A memory read data test circuit structure, the memory read data test circuit structure comprising:
the output end of the reading signal path is connected with the reading end of the memory; the read signal path includes a clock gating cell and a first combinational logic circuit cell; the clock end of the clock gating unit is connected with a synchronous clock signal; a read signal output from a gate output terminal of the clock gate unit is input to a read terminal of the memory through the first combinational logic circuit unit;
an address path, wherein the output end of the address path is connected with the address end of the memory; the address path comprises an address register unit, a logic control circuit unit, an address latch unit and a second combinational logic circuit unit; the clock end of the address register unit is connected with the synchronous clock signal, the data output end of the address register unit is connected with the input end of the logic control circuit unit, the output end of the logic control circuit unit is connected with the data input end of the address latch unit, and the clock end of the address latch unit is connected with the synchronous clock signal; an address signal output from an output terminal of the address latch unit is input to an address terminal of the memory through the second combinational logic circuit unit;
the first combinational logic circuit unit comprises a first multi-way switch, a second multi-way switch, a first inverter and a second inverter;
the input end of the first multi-way switch is connected with the gate control output end of the clock gate control unit, the output end of the first multi-way switch is connected with one input end of the second multi-way switch, the output end of the second multi-way switch is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is connected with the reading end of the memory;
the second combinational logic circuit unit comprises a third multi-way switch, a fourth multi-way switch, a third inverter and a fourth inverter;
the input end of the third multi-way switch is connected with the output end of the address latch unit, the output end of the third multi-way switch is connected with one input end of the fourth multi-way switch, the output end of the fourth multi-way switch is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the fourth inverter, and the output end of the fourth inverter is connected with the address end of the memory.
2. The memory read data test circuit structure of claim 1, wherein the number, type and connection relationship of the devices in the first combinational logic circuit unit are the same as the number, type and connection relationship of the devices in the second combinational logic circuit unit.
3. The memory read data test circuit arrangement of claim 1, wherein a difference between a first delay traversed by a read signal in the read signal path and a second delay traversed by an address signal in the address path is less than 1ns.
4. A method of designing a memory read data test circuit structure, characterized in that the method of designing a memory read data test circuit structure uses the memory read data test circuit structure as claimed in any one of claims 1 to 3, comprising the steps of:
providing a read signal path, and inputting a read signal to a read end of the memory; the read signal is output after passing through a read signal generating step and a combinational logic operation step in sequence in the read signal path;
providing an address path, and inputting an address signal to an address end of a memory;
the address signal is output after sequentially passing through an address signal generating step, a logic control step, an address latching step and a combined logic operation step in the address path;
the read signal generating step, the address signal generating step and the address latching step adopt synchronous clocks.
5. The method of designing a memory read data test circuit structure of claim 4, wherein the step of combining logic operations performed by the read signal in the read signal path is the same as the step of combining logic operations performed by the address signal in the address path.
6. The method of designing a memory read data test circuit structure of claim 4, wherein a difference between a first delay that the read signal passes in the read signal path and a second delay that the address signal passes in the address path is less than 1ns.
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| CN103219037A (en) * | 2013-04-22 | 2013-07-24 | 中国科学院半导体研究所 | In-chip memory with multi-port read-write |
| CN106297893A (en) * | 2016-08-01 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | The clock circuit of memorizer measuring circuit and method for designing thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103219037A (en) * | 2013-04-22 | 2013-07-24 | 中国科学院半导体研究所 | In-chip memory with multi-port read-write |
| CN106297893A (en) * | 2016-08-01 | 2017-01-04 | 上海华虹宏力半导体制造有限公司 | The clock circuit of memorizer measuring circuit and method for designing thereof |
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