CN213459060U - Memory and memory test system - Google Patents
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- CN213459060U CN213459060U CN202022446104.9U CN202022446104U CN213459060U CN 213459060 U CN213459060 U CN 213459060U CN 202022446104 U CN202022446104 U CN 202022446104U CN 213459060 U CN213459060 U CN 213459060U
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Abstract
The embodiment of the utility model provides a memory and memory test system, wherein, the memory includes: an input circuit adapted to receive an external clock signal and output a first test clock signal; the test path selection circuit is connected with the input circuit and is suitable for outputting a second test clock signal according to the read clock command; output circuit, with test path selection circuit connection, be suitable for to convert second test clock signal into third test clock signal and export the memory outside, the embodiment of the utility model provides a time delay through each chip that quantization clock signal input was tested to the actual output that acquires the chip delays, has improved the accuracy of multicore piece parallel test.
Description
Technical Field
The utility model relates to a semiconductor chip tests the field, in particular to memory and memory test system.
Background
The semiconductor chip test aims to screen out the semiconductor chips with the product performance not meeting the expected performance. There are many factors that cause the performance of the semiconductor chip to be unqualified, for example, the semiconductor chip may generate a process error during the manufacturing process, so that the output delay of the formed semiconductor chip does not meet the expected performance.
Semiconductor chip testing is generally performed by multi-chip parallel testing, in which a chip test card simultaneously tests hundreds to thousands of chips on one wafer, in order to save test time.
In order to save testing resources, the chips for parallel testing adopt the same clock signal, and different time delays exist when the clock signal is input into each chip to be tested, so that the output delay of the chips obtained by testing cannot represent the actual output delay of the chips, and the problem of inaccurate result of the multi-chip parallel testing is caused.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a memory and memory test system, the time delay through each chip that the input of quantization clock signal is tested to the actual output that acquires the chip is delayed, has improved the accuracy of the parallel test of multicore piece.
In order to solve the above technical problem, an embodiment of the present invention provides a memory, including: an input circuit adapted to receive an external clock signal and output a first test clock signal; the test path selection circuit is connected with the input circuit and is suitable for outputting a second test clock signal according to the read clock command; and the output circuit is connected with the test path selection circuit and is suitable for converting the second test clock signal into a third test clock signal and outputting the third test clock signal to the outside of the memory.
The direct output circuit is formed by the input circuit, the test path selection circuit and the output circuit, and the third test clock signal is output through the direct output circuit directly based on the external clock signal, so that the time delay of the external signal input to the memory is obtained, the error caused by different time delays when the clock signal is input to each tested chip is avoided, and the accuracy of the multi-chip parallel test is improved.
In addition, the input circuit also outputs a first normal clock signal, and the frequency and the phase of the first normal clock signal are the same as those of the first test clock signal.
In addition, the memory also comprises a memory block, and the first normal clock signal is suitable for a clock source for reading and writing the memory block.
In addition, the first test clock signal has the same frequency as the external clock signal.
In addition, when the read clock command is low, the second test clock signal output by the test path selection circuit is at a low level; when the read clock command is high, the second test clock signal output by the test path selection circuit has the same frequency as the first test clock signal.
In addition, the memory further comprises a test mode module, and the test mode module outputs a read clock command.
The embodiment of the utility model provides a still provide a memory test system, include: a plurality of the memories, wherein the memories are numbered from 1 to N in sequence, and N is an integer greater than or equal to 2; and the test card outputs address information, command information, a zeroth test clock signal and chip selection information to the memories with the numbers from 1 to N and receives data information of the memories with the numbers from 1 to N.
In addition, the test card is provided with N chip selection output ends for outputting chip selection information and N data receiving ends for receiving data information, and the N chip selection output ends and the N data receiving ends are connected with the memories with the numbers from 1 to N in a one-to-one corresponding mode.
In addition, the memories numbered 1 to N share address information, command information, and a zeroth test clock signal output from the test card.
In addition, the zeroth test clock signal of the test card is sent to the input circuit of the memory, and the third test clock signal of the memory is sent to the data receiving end corresponding to the test card.
The memories with the numbers of 1 to N are tested in parallel through the same test card, the memories with the numbers of 1 to N comprise the direct output circuit, and a third test clock signal is output based on a zeroth test clock signal provided by the test card, so that the time delay of inputting the zeroth clock signal into the memories is obtained, errors caused by different time delays when the zeroth test clock signal is input into each tested chip are avoided, and the accuracy of multi-chip parallel testing through the test card is improved.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to scale unless specifically noted.
Fig. 1 is a schematic diagram of a memory according to a first embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a memory according to a first embodiment of the present invention;
fig. 3 is a schematic structural diagram of a memory test system according to a second embodiment of the present invention;
fig. 4 is a schematic flow chart of a memory testing method according to a third embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating clock skew in a multi-chip parallel test.
Detailed Description
At present, semiconductor chip testing is generally performed by multi-chip parallel testing, in order to save testing time, in the multi-chip parallel testing, a chip testing card simultaneously tests hundreds of chips on a wafer. In order to save testing resources, the chips for parallel testing adopt the same clock signal, and different time delays exist when the clock signal is input into each chip to be tested, so that the output delay of the chips obtained by testing cannot represent the actual output delay of the chips, and the problem of inaccurate result of the multi-chip parallel testing is caused. Referring to fig. 5, the clock terminal CLK of the test card reaches the clock terminal CLK of the Chip1 with a delay, for example, 0.5ns, and the clock terminal CLK of the test card reaches the clock terminal CLK of the Chip2 with a delay, for example, 0.9 ns. The delay of the clock terminal CLK of the test card reaching the clock terminal CLK of the Chip1 is defaulted to 0, the deviation between 0.5ns and 0.9ns is the clock deviation value of the Chip2 during parallel test, and the clock deviation value is 0.9 ns-0.5 ns-0.4 ns.
In order to solve the above problem, a first embodiment of the present invention provides a memory, including: an input circuit adapted to receive an external clock signal and output a first test clock signal; the test path selection circuit is connected with the input circuit and is suitable for outputting a second test clock signal according to the read clock command; and the output circuit is connected with the test path selection circuit and is suitable for converting the second test clock signal into a third test clock signal and outputting the third test clock signal to the outside of the memory.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the embodiments of the present invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present invention, and the embodiments may be combined with each other and cited without contradiction.
Fig. 1 is a schematic diagram of a memory according to a first embodiment of the present invention, and fig. 2 is a schematic diagram of a circuit structure of a memory according to a first embodiment of the present invention, which is specifically described below.
Referring to fig. 1, a memory 100 includes:
an input circuit 101 is adapted to receive an external clock signal OutClk and output a first test clock signal TestClk 1. The external clock signal OutClk is a clock signal provided to the memory 100 by an external device, and is a normal operating signal or a test signal of the memory 100. The first test clock signal TestClk1 is a clock signal input to the test path selection circuit 102, and specifically, the first test clock signal TestClk1 has the same frequency as the external clock signal OutClk.
The delay of first test clock signal TestClk1 and external clock signal OutClk is characterized by input circuit delay information.
The test path selection circuit 102, coupled to the input circuit 101, is adapted to output a second test clock signal TestClk2 according to the read clock command ReadClkout. The second test clock signal TestClk2 is the clock signal of the input-output circuit 103.
In this embodiment, the memory 100 further includes a test mode module 104, and the test mode module 104 is configured to output a read clock command ReadClkout. Specifically, the memory 100 outputs a read clock command ReadClkout to turn on the test path selection circuit 102 based on the received command information.
The read clock command readclk is a start signal of the test path selection circuit 102, the test path selection circuit 102 outputs the second test clock signal TestClk2 according to the first test clock signal TestClk1 when the read clock command readclk is at a high level, and the second test clock signal TestClk2 output by the test path selection circuit 102 is at a low level when the read clock command readclk is at a low level. Specifically, when the read clock command ReadClkout is at a high level, the second test clock signal TestClk2 has the same frequency as the first test clock signal TestClk 1.
The delay of the second test clock signal TestClk2 from the first test clock signal TestClk1 is characterized by test path selection circuit delay information.
And an output circuit 103 connected to the test path selecting circuit 102 and adapted to convert the second test clock signal TestClk2 into a third test clock signal TestClk3 and output it to the outside of the memory 100. The third test clock signal TestClk3, i.e., the output clock signal of the memory 100, is output to the outside of the memory 100.
The delay of the third test clock signal TestClk3 and the second test clock signal TestClk2 is characterized by output circuit delay information.
The input circuit 101, the test path selection circuit 102, and the output circuit 103 serve as a first data path, and directly output the received external clock signal OutClk. The input circuit delay information, the test path selection circuit delay information, and the output circuit delay information together form the test path delay information of the memory 100.
In this embodiment, the memory 100 further includes a memory block 105, the memory block 105 is a memory cell of the memory 100 for storing data, and the input circuit 101 further outputs a first normal clock signal Clk, which is a clock source suitable for reading and writing the memory block 105. Specifically, the frequency and phase of the first normal clock signal Clk are the same as the frequency and phase of the first test clock signal TestClk 1.
Referring to fig. 1 and 4, the memory block 105 operates based on the first normal clock signal Clk, the memory 100 performs a read operation based on the received command information CMD, reads data from the memory block 105, the data is output to the test card 200 through the TDQ terminal of the memory, and the test card acquires main data path delay information of the memory 100 by issuing a zeroth test clock signal TestClk0 to the memory 100 and receiving an interval time of the read data, wherein the input circuit delay information, the time of performing a read/write operation on the memory block, and the output circuit delay information together constitute the main path delay information of the memory 100.
Specifically, test card 200 supplies test clock signal TestClk0 and command information CMD to memory 100, input circuit 101 issues first normal clock signal Clk based on test clock signal TestClk0, memory block 105 reads data based on first normal clock signal Clk, and memory 100 passes data read from memory block 105 back to test card 200 through output terminal TDQ. I.e., test card 200, input circuit 101, memory block 105, as a second data path for obtaining main path delay information for memory 100.
In one example, referring to fig. 2, the input circuit 101 includes a receiving circuit 111, the receiving circuit 111 is used for generating a first test clock signal TestClk1 and a first normal clock signal Clk according to an external clock signal OutClk, the first test clock signal TestClk1 and the external clock signal OutClk are the same frequency, and the first test clock signal TestClk1 and the first normal clock signal Clk are the same frequency and in phase.
In one example, referring to fig. 2, the test path selecting circuit 102 includes an and gate structure 112, two inputs of the and gate structure 112 are respectively used for receiving the read clock command ReadClkout and the first test clock signal TestClk1, when the read clock command ReadClkout is at a high level, the test path selecting circuit 102 outputs the second test clock signal TestClk2 according to the first test clock signal TestClk1, the second test clock signal TestClk2 has the same frequency as the first test clock signal TestClk1, and when the read clock command ReadClkout is at a low level, the second test clock signal TestClk2 output by the test path selecting circuit 102 is at a low level.
In one example, referring to fig. 2, the output circuit 103 includes a transmitting circuit 113, and the transmitting circuit 113 is configured to convert the second test clock signal TestClk2 into a third test clock signal TestClk3 and output the third test clock signal TestClk3 to the outside of the memory 100. That is, the input circuit 101, the test path selection circuit 102, and the output circuit 103 serve as a first data path, and directly output the received external clock signal OutClk.
The memory block 105 operates based on the first normal clock signal Clk, the memory 100 performs a read operation based on the command information CMD, data is read from the memory block 105, and the test card acquires the main data path delay information of the memory 100 by an interval of time of issuing a clock signal to the memory area and receiving the read data.
The test path delay information and the main path delay information of the memory 100 are acquired based on the input circuit delay information, the output circuit delay information, the test path selection circuit delay information, and the time of performing the read-write operation on the memory block of the memory 100. Wherein the input circuit delay information, the test path selection circuit delay information, and the output circuit delay information together constitute the test path delay information of the memory 100; the input circuit delay information, the time to read and write the memory block, and the output circuit delay information collectively constitute the main path delay information for memory 100.
Compared with the related art, the direct output circuit is formed by the input circuit, the test path selection circuit and the output circuit, and the third test clock signal is output through the direct output circuit directly based on the external clock signal so as to obtain the time delay when the external signal is input into the memory, avoid the error caused by different time delays when the clock signal is input into each tested chip, and improve the accuracy of the multi-chip parallel test.
It should be noted that, all the modules involved in this embodiment are logic modules, and in practical application, one logic unit may be one physical unit, may also be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, the unit which is not closely related to the solution of the technical problem proposed by the present invention is not introduced in the present embodiment, but this does not indicate that there are no other units in the present embodiment.
The utility model discloses second embodiment relates to a memory test system.
Fig. 3 is a schematic structural diagram of a memory test system according to a second embodiment of the present invention, and the memory test system according to this embodiment will be described in detail below with reference to the accompanying drawings, and the same or corresponding portions as those in the first embodiment will not be described in detail below.
Referring to fig. 3, the memory test system includes: a plurality of memories provided as the above first embodiment, the memories are numbered 1 to N in sequence, where N is an integer greater than or equal to 2, for example, memory 1(Chip1, 201), memory 2(Chip2, 202) … … memory N (Chip N, 203); the test card 200 outputs address information Adress, command information CMD, a zeroth test clock signal TestClk0, and a chip select signal to the memories numbered 1 to N, and receives data information of the memories numbered 1 to N.
Specifically, the memory sharing test cards numbered 1 to N share the address information Adress, the command information CMD, and the zeroth test clock signal TestClk0 output from the test card 200.
The test card 200 has N chip select output terminals outputting chip select information and N data receiving terminals receiving data information, and is connected to the memories numbered 1 to N in a one-to-one correspondence.
Specifically, the test card establishes a data transmission loop with the memory 1(Chip1, 201) through the first Chip select output terminal CS1 and the first data receiving terminal TDQ1, data information of the memory 1(Chip1, 201) is fed back to the test card 200 through the first data receiving terminal TDQ1, and the test card 200 and the memory 1(Chip1, 201) form a data transmission closed loop through the first Chip select output terminal CS1 and the first data receiving terminal TDQ1, that is, data transmission between the memory numbered from 1 to N and the test card 200 is not affected.
Specifically, the zeroth test clock signal TestClk0 of the test card 200 is supplied to the input circuit 101 of the memory, and the memory supplies the third test clock signal TestClk3 and the data stored in the memory block 105 to the corresponding data receiving terminal of the test card 200. The zeroth test clock signal TestClk0 is an external clock signal OutClk input to the memory, and the zeroth test clock signal TestClk0 is a normal operation signal and a test signal of the memory 100; acquiring test path delay information of the memory according to a third test clock signal TestClk3 fed back by the memory, and acquiring main path delay information of the memory according to data stored in a storage block 105 fed back by the memory; acquiring a clock offset value corresponding to each memory according to Nth main path delay information and Nth test path delay information fed back by the acquired memories numbered from 1 to N, wherein the clock offset value of the memory numbered N is the Nth test path delay information-first test path delay information; the actual delay of the nth main path of the memory numbered N is the nth main path delay information-clock offset value.
Compared with the prior art, the memories with the numbers of 1 to N are tested in parallel through the same test card, the memories with the numbers of 1 to N comprise the direct output circuit, and the third test clock signal is output based on the zeroth test clock signal provided by the test card, so that the time delay of inputting the zeroth clock signal into the memories is obtained, the error caused by different time delays when the zeroth test clock signal is input into each tested chip is avoided, and the accuracy of multi-chip parallel test through the test card is improved.
It should be noted that, all the modules involved in this embodiment are logic modules, and in practical application, one logic unit may be one physical unit, may also be a part of one physical unit, and may also be implemented by a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, the unit which is not closely related to the solution of the technical problem proposed by the present invention is not introduced in the present embodiment, but this does not indicate that there are no other units in the present embodiment.
Since the first embodiment corresponds to the present embodiment, the present embodiment can be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment.
The third embodiment of the present invention relates to a memory test method.
The memory test method comprises the following steps: the test card outputs address information, command information, a zeroth test clock signal and chip selection information to the memories sequentially numbered from 1 to N and receives data information of the memories numbered from 1 to N, wherein N is an integer greater than or equal to 2; the data information output by each memory comprises main path delay information and test path delay information, the test card sequentially numbers the main path delay information of the memories with receiving numbers from 1 to N as first main path delay information to Nth main path delay information, and the test card sequentially numbers the test path delay information of the memories with receiving numbers from 1 to N as first test path delay information to Nth test path delay information; sequentially defining the actual delay of the first main path to the actual delay of the Nth main path, wherein the actual delays of the main paths of the memories with the numbers of 1 to N are corresponding; the first main path actual delay is equal to the first main path delay information, the difference value between the Mth test path delay information and the first test path delay information is equal to the clock offset value, the Mth main path actual delay is equal to the Mth main path delay information minus the clock offset value, and M is an integer greater than 1 and less than or equal to N.
Fig. 4 is a schematic flow chart of a memory testing method according to a third embodiment of the present invention, and the memory testing method according to this embodiment will be described in detail below with reference to the accompanying drawings, and details of the same or corresponding parts as those in the first embodiment and the second embodiment will not be repeated below.
Referring to fig. 4, the memory test method includes:
Specifically, referring to fig. 3, the test card 200 outputs address information Adress, command information CMD, a zeroth test clock signal TestClk0, and chip select information to memories sequentially numbered 1 to N, where N is an integer greater than or equal to 2.
The test card 200 has N chip select output terminals outputting chip select information and N data receiving terminals receiving data information, and is connected to the memories numbered 1 to N in a one-to-one correspondence.
The memories numbered 1 through N share address information Adress, command information CMD, and a zeroth test clock signal TestClk0 output from the test card 200, wherein the zeroth test clock signal TestClk0 is an external clock signal input to the memories.
Specifically, in conjunction with FIG. 3, the test card 200 receives data information for memories numbered 1 through N. The data information output by each memory comprises main path delay information and test path delay information, the test card sequentially numbers the main path delay information of the memories with receiving numbers from 1 to N as first main path delay information to Nth main path delay information, and the test card sequentially numbers the test path delay information of the memories with receiving numbers from 1 to N as first test path delay information to Nth test path delay information.
In conjunction with fig. 1, memory 100 includes: an input circuit 101 receiving the zeroth test clock signal TestClk0 and outputting a first test clock signal TestClk1 and a first normal clock signal Clk, a delay of the first test clock signal TestClk1 with respect to the zeroth test clock signal TestClk0 being input circuit delay information; a test path selection circuit 102 connected to the input circuit 101 and adapted to output a second test clock signal TestClk2 according to the read clock command ReadClkout, a delay of the second test clock signal TestClk2 with respect to the first test clock signal TestClk1 being test path selection circuit delay information; an output circuit 103 connected to the test path selecting circuit 102 and adapted to convert the second test clock signal TestClk2 into a third test clock signal TestClk3 and output the third test clock signal TestClk3 as output circuit delay information with respect to a delay of the second test clock signal TestClk 2;
specifically, the input circuit 101 receives the zeroth test clock signal TestClk0 and outputs the first test clock signal TestClk1, and the input circuit 101 is further configured to output the normal clock signal Clk according to the zeroth test clock signal TestClk 0. The delay of the first test clock signal TestClk1 and the zeroth test clock signal TestClk0 is characterized by input circuit delay information.
The test path selection circuit 102 is adapted to output the second test clock signal TestClk2 according to the read clock command ReadClkout. The delay of the second test clock signal TestClk2 from the first test clock signal TestClk1 is characterized by test path selection circuit delay information.
In this embodiment, the memory 100 further includes a test mode module 104, the test mode module receives the command information CMD, and the test mode module 104 further outputs a read clock command ReadClkout. Specifically, the memory 100 outputs a read clock command ReadClkout to turn on the test path selection circuit 102 based on the received command information CMD. The test path selection circuit 102 outputs the second test clock signal TestClk2 according to the first test clock signal TestClk1 when the read clock command readclk is high-level, and the second test clock signal TestClk2 output by the test path selection circuit 102 is low-level when the read clock command readclk is low-level.
And an output circuit 103 adapted to convert the second test clock signal TestClk2 into a third test clock signal TestClk3 to be output to the outside of the memory 100. The delay of the third test clock signal TestClk3 and the second test clock signal TestClk2 is characterized by output circuit delay information.
In this embodiment, the test path delay information includes input circuit delay information, test path selection circuit delay information, and output circuit delay information.
The memory 100 further comprises a memory block 105, the first normal clock signal Clk being adapted to a clock source for reading from and writing to the memory block 105. Specifically, the frequency and phase of the first normal clock signal Clk are the same as the frequency and phase of the first test clock signal TestClk 1.
The memory block 105 operates based on the first normal clock signal Clk, the memory 100 performs a read operation based on the command information CMD, data is read from the memory block 105, and the test card acquires the main data path delay information of the memory 100 by an interval of time of issuing a clock signal to the memory area and receiving the read data.
Specifically, test card 200 supplies test clock signal TestClk0 and command information CMD to memory 100, input circuit 101 issues first normal clock signal Clk based on test clock signal TestClk0, memory block 105 reads data based on first normal clock signal Clk, and memory 100 transmits data read from memory block 105 back to test card 200 through TDQ. I.e., test card 200, input circuit 101, memory block 105, as a second data path for obtaining main path delay information for memory 100.
In this embodiment, the main path delay information includes input circuit delay information, time to perform read and write operations on the memory block, and output circuit delay information.
Specifically, the first main path actual delay is equal to the first main path delay information, and correspondingly, the nth main path actual delay is equal to the nth main path delay information.
And recording that the difference value of the Mth test path delay information and the first test path delay information is equal to the clock offset value, the actual delay of the Mth main path is equal to the difference value of the Mth main path delay information minus the clock offset value, and M is an integer which is greater than 1 and less than or equal to N.
Specifically, for the memory N (ChipN, 203), the difference between the nth test path delay information and the first test path delay information of the memory N (ChipN, 203) is equal to the clock skew value, and the nth main path actual delay is equal to the nth main path delay information minus the clock skew value.
The data information fed back by the memory comprises the data information shown in table 1 and table 2:
TABLE 1
TABLE 2
| Main path delay information | Test path delay information | Deviation value of clock | |
| Memory 1(Chip1, 201) | Z1 | C1 | / |
| Memory 2(Chip2, 202) | Z2 | C2 | C2—C1 |
| …… | …… | …… | …… |
| Memory N (ChipN, 203) | ZN | CN | CN—C1 |
Acquiring clock deviation values corresponding to the memories according to the acquired test path delay information fed back by the memories with the labels of 1 to N respectively; for example, the clock skew value of the memory with the number N is the first test path delay information, i.e., t ═ CN—C1。
Acquiring the actual main path delay corresponding to each memory according to the acquired main path delay information respectively fed back by the memories with the labels of 1 to N; for example, the actual delay of the main path of memory numbered N is the main path delay information-clock skew value, i.e., TN＝ZN—t。
For example, referring to FIG. 3 as an example, chip number 1 has a zeroth test clock signal delay D010.2ns, input circuit delay information D120.4ns delay information D4 for test path selection circuit20.3ns, and output circuit delay information D321 st test path delay information C of chip number 1 of 0.5ns11.4 ns; taking N equal to 2 as an example, chip number 2 has a delay D0 of the zeroth test clock signal20.5ns, input circuit delay information D120.5ns delay information D4 for test path selection circuit20.2ns, and output circuit delay information D320.4ns, i.e., 2 nd test path delay information C of chip number 211.6ns, then the memory numbered 2The clock skew value t is 0.2 ns; if the acquired 2 nd main path delay information Z of the chip with the number of 2 is acquired215ns, then chip number 2 main path actual delay T2＝14.8ns。
Compared with the prior art, the test card provides a zeroth test clock signal for the memory, the main path delay information and the test path delay information fed back by the memory acquire the main path actual delay of the memory based on the main path delay information, the difference value between the Mth test path delay information and the first test path delay information is recorded as a clock deviation value, and the main path actual delay is acquired based on the main path delay information and the clock deviation value, so that errors caused by different time delays when the clock signal is input into each tested chip are avoided, and the accuracy of the multi-chip parallel test is improved.
The above steps are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the steps include the same logical relationship, which is within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the flow or to introduce insignificant design, but not to change the core design of the flow.
Since the first and second embodiments correspond to the present embodiment, the present embodiment can be implemented in cooperation with the first and second embodiments. The related technical details mentioned in the first embodiment and the second embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment and the second embodiment can also be achieved in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment and the second embodiment.
It will be understood by those skilled in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A memory, comprising:
an input circuit adapted to receive an external clock signal and output a first test clock signal;
the test path selection circuit is connected with the input circuit and is suitable for outputting a second test clock signal according to the read clock command;
and the output circuit is connected with the test path selection circuit and is suitable for converting the second test clock signal into a third test clock signal and outputting the third test clock signal to the outside of the memory.
2. The memory of claim 1, wherein the input circuit further outputs a first normal clock signal, the first normal clock signal having the same frequency and phase as the first test clock signal.
3. The memory of claim 2, further comprising a memory block, wherein the first normal clock signal is adapted to a clock source for performing read and write operations on the memory block.
4. The memory of claim 1, wherein the first test clock signal is at the same frequency as the external clock signal.
5. The memory of claim 1, wherein when the read clock command is low, the second test clock signal output by the test path selection circuit is low; when the read clock command is high, the second test clock signal output by the test path selection circuit has the same frequency as the first test clock signal.
6. The memory of claim 1, further comprising a test mode module that outputs the read clock command.
7. A memory test system, comprising:
a plurality of memories according to any one of claims 1 to 6, numbered sequentially from 1 to N, where N is an integer greater than or equal to 2;
and the test card outputs address information, command information, a zeroth test clock signal and chip selection information to the memories with the numbers from 1 to N and receives data information of the memories with the numbers from 1 to N.
8. The memory test system of claim 7, wherein the test card has N chip select outputs for outputting the chip select information and N data receivers for receiving the data information, and is connected to the memories numbered 1 to N in a one-to-one correspondence.
9. The memory test system of claim 8, wherein the memories numbered 1 through N share the address information, the command information, and the zeroth test clock signal output by the test card.
10. The memory test system of claim 9, wherein the zeroth test clock signal of the test card is provided to the input circuit of the memory, and the third test clock signal of the memory is provided to the data receiving terminal corresponding to the test card.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022446104.9U CN213459060U (en) | 2020-10-27 | 2020-10-27 | Memory and memory test system |
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| WO2022088848A1 (en) * | 2020-10-27 | 2022-05-05 | 长鑫存储技术有限公司 | Memory, memory testing system, and memory testing method |
| US11817166B2 (en) | 2020-10-27 | 2023-11-14 | Changxin Memory Technologies, Inc. | Memory, memory test system, and memory test method |
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