CN110083492A - A kind of circuit critical registers triplication redundancy reinforcement means and device - Google Patents
A kind of circuit critical registers triplication redundancy reinforcement means and device Download PDFInfo
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Abstract
The present invention provides a kind of circuit critical registers triplication redundancy reinforcement means and devices, belong to register technique field.The described method includes: determine corresponding first time delay of each timing path in circuit, and each timing path is corresponding first when the maximum of Yanzhong be determined as critical path, remaining is non-critical path；Determine that each non-critical path carries out corresponding second time delay after triplication redundancy reinforcing；By the second time delay of each non-critical path, the first time delay corresponding with critical path is compared respectively, and the non-critical path by the second time delay no more than corresponding first time delay of critical path is determined as path to be reinforced；It treats the register reinforced on path and carries out triplication redundancy reinforcing.This method is realized simple and effective, eliminate traditional triplication redundancy reinforcement means adverse effect caused by system performance, circuit reliability is improved, and will be controlled in the zone of reasonableness for not influencing system performance because reinforcing the overhead generated, is of very high actual application value.
Description
Technical field
The present invention relates to register reinforcement technique fields, specifically provide a kind of circuit critical registers triplication redundancy reinforcing
Method and device.
Background technique
Single-particle inversion (SEU) is to lead to circuit memory cell due to space particle radiation there is a phenomenon where bit flippings.
Specific integrated circuit (ASIC) and field programmable gate array (FPGA) are due to containing a large amount of storage units, thus in some electricity
As being particularly susceptible to the interference of SEU, the operation to spacecraft when too aerial applications in the case that magnetic, radiation environment are relatively severe
It causes to seriously affect.
In order to reduce influence of the SEU effect to circuit, fault-tolerance is improved, some storage units in circuit can such as be deposited
Device is reinforced.Reinforcement means has very much, if circuit is copied into two parts by replication theme, passes through CWSP (code word state
Preserving element) upper one correctly output is kept, hardware spending is about twice of primary circuit；Triplication redundancy
(TMR) circuit is copied into three parts, correctly output is selected by majority voting device, hardware spending is about three times of primary circuit.
To reduce circuit hardware expense, saving circuit area, local triplication redundancy reinforcement means, existing part triplication redundancy are generallyd use
The usually first weight and functional dependence using in the life span of register, conditional branching of reinforcement means is chosen as measurement standard
The register big to systematic influence is reinforced as critical registers.
Existing part triplication redundancy reinforcement means, which often will lead to, introduces additional delay in critical path, lead to the fortune of circuit
The decline of scanning frequency degree.
Summary of the invention
Aiming at the problems existing in the prior art, the embodiment of the invention provides a kind of circuit critical registers triplication redundancies
Reinforcement means and device, this method realization is simple and effective, eliminates traditional triplication redundancy reinforcement means caused by system performance
Adverse effect, is a kind of reinforcement means in view of hardware spending and circuit delay, improves circuit reliability, and will be because adding
Admittedly the overhead generated controls in the zone of reasonableness for not influencing system performance, it is of very high actual application value.
The technical solution of the invention is as follows:
A kind of circuit critical registers triplication redundancy reinforcement means, comprising:
Determine corresponding first time delay of each timing path in circuit, and each timing path is corresponding first when Yanzhong
It is maximum be determined as critical path, remaining is non-critical path；
Determine that each non-critical path carries out corresponding second time delay after triplication redundancy reinforcing；
By the second time delay of each each non-critical path, the first time delay corresponding with the critical path compares respectively
Compared with the non-critical path by second time delay no more than corresponding first time delay of the critical path is determined as road to be reinforced
Diameter；
Triplication redundancy reinforcing is carried out wait reinforce the register on path to described.
In an alternative embodiment, in the determining circuit before corresponding first time delay of each timing path, further includes:
By circuit conversion at topological digraph, each timing path is determined according to the topological digraph.
In an alternative embodiment, it is described by circuit conversion at topological digraph, comprising:
By in circuit active trigger be mapped to the start node in topological digraph, by circuit it is all eventually trigger
Device is mapped to the terminal node in topological digraph, and each logic between the source trigger and whole trigger will be located in circuit
Unit is mapped to each intermediate node in topological digraph, by the company between the source trigger, logic unit and whole trigger
Relationship map is connect into the side in the topological digraph, signal transmission direction in circuit is mapped to the direction on the side, is obtained
The corresponding topological digraph of circuit.
It is described that each timing path is determined according to the topological digraph in an alternative embodiment, comprising:
Will using the start node as starting point, using the terminal node as terminal, using the logic unit as intermediate point, by
The side connects the access to be formed and is determined as each timing path.
In an alternative embodiment, corresponding first time delay of each timing path in the determining circuit, comprising:
It determines the corresponding source trigger of the timing path, each logic unit and whole trigger, and determines corresponding described
Source trigger, each logic unit and whole corresponding first period of the day from 11 p.m. to 1 a.m of trigger prolong；
Determine that corresponding second period of the day from 11 p.m. to 1 a.m in the corresponding each side of the timing path prolongs；
Each first period of the day from 11 p.m. to 1 a.m is prolonged the sum of to prolong with second period of the day from 11 p.m. to 1 a.m and is determined as corresponding first time delay of the timing path.
In an alternative embodiment, when corresponding second after each non-critical path progress triplication redundancy reinforcing of determination
Prolong, comprising:
It is integrated by DesignCompiler former RTL design code corresponding to the circuit, obtains the door of circuit
Grade netlist；
Triplication redundancy reinforcing is carried out to the non-critical path in the gate level netlist；
Time delay after non-critical path in the gate level netlist is carried out triplication redundancy reinforcing is as the second time delay.
A kind of circuit critical registers triplication redundancy bracing means, comprising:
First determining module, for determining corresponding first time delay of each timing path in circuit, and by each timing road
Diameter it is corresponding first when the maximum of Yanzhong be determined as critical path, remaining is non-critical path；
Second determining module, for determining corresponding second time delay after each non-critical path carries out triplication redundancy reinforcing；
Comparing unit, for by the second time delay of each each non-critical path respectively corresponding with the critical path
One time delay is compared, and the non-critical path by second time delay no more than corresponding first time delay of the critical path determines
For path to be reinforced；
Reinforcement elements, for carrying out triplication redundancy reinforcing wait reinforce the register on path to described.
In an alternative embodiment, the circuit critical registers triplication redundancy bracing means, further includes:
Conversion module, for circuit conversion at topological digraph, to be determined each timing path according to the topological digraph.
In an alternative embodiment, the conversion module is used for:
By in circuit active trigger be mapped to the start node in topological digraph, by circuit it is all eventually trigger
Device is mapped to the terminal node in topological digraph, and each logic between the source trigger and whole trigger will be located in circuit
Unit is mapped to each intermediate node in topological digraph, by the company between the source trigger, logic unit and whole trigger
Relationship map is connect into the side in the topological digraph, signal transmission direction in circuit is mapped to the direction on the side, is obtained
The corresponding topological digraph of circuit.
In an alternative embodiment, the conversion module is used for:
Will using the start node as starting point, using the terminal node as terminal, using the logic unit as intermediate point, by
The side connects the access to be formed and is determined as each timing path.
Compared with the prior art, the invention has the advantages that:
The embodiment of the invention provides a kind of circuit critical registers triplication redundancy reinforcement means, by determining critical path
Diameter, and it is true according to the relationship of delay time of the non-critical path after carrying out triplication redundancy processing and the delay time of critical path
Fixed path to be reinforced, this method are realized simple and effective, eliminate traditional triplication redundancy reinforcement means caused by system performance not
Benefit influences, and is a kind of reinforcement means in view of hardware spending and circuit delay, improves circuit reliability, and will be because reinforcing
The overhead of generation controls in the zone of reasonableness for not influencing system performance, is of very high actual application value.
Detailed description of the invention
Fig. 1 is that the embodiment of the invention provides a kind of circuit critical registers triplication redundancy reinforcement means flow charts；
Fig. 2 is critical path selection gist schematic diagram provided in an embodiment of the present invention；
Fig. 3 is the circuit diagram that a specific embodiment of the invention provides and corresponding topological digraph；
Fig. 4 is the triplication redundancy reinforcement means schematic illustration that a specific embodiment of the invention provides.
Specific embodiment
A specific embodiment of the invention is described in further details below with reference to drawings and the specific embodiments.
Referring to Fig. 1, the embodiment of the invention provides a kind of circuit critical registers triplication redundancy reinforcement means, comprising:
Step 101: determining corresponding first time delay of each timing path in circuit, and by each timing path corresponding
The maximum of a period of time Yanzhong is determined as critical path, remaining is non-critical path；
Specifically, in Design of Digital Integrated Circuit, static timing analysis is indispensable component part.It can pass through
Static timing analysis determines critical path and non-critical path；In the embodiment of the present invention, " path " can be for when one synchronous
An access in sequence circuit from a sequential logic unit after several logic units to another sequential logic unit；
In such access, intermediate logic unit seeks to " critical path " looked for interconnection line overall delay maximum one；
Circuit is made of hundreds of circulations and combinational logic gate, and the delay of circuit performance and register has direct pass
System, as shown in Fig. 2, the present invention using signal from the input D of a register reach next register input D time as
The Rule of judgment of circuit critical path；
Step 102: determining that each non-critical path carries out corresponding second time delay after triplication redundancy reinforcing；
Step 103: by the second time delay of each each non-critical path respectively corresponding with the critical path first when
Prolong and be compared, by second time delay no more than corresponding first time delay of the critical path non-critical path be determined as to
Reinforce path；
Step 104: carrying out triplication redundancy reinforcing wait reinforce the register on path to described.
Specifically, in the embodiment of the present invention, treating and reinforcing the triplication redundancy reinforcement means in path is existing conventional reinforcing side
Method, the present invention are not construed as limiting；
The embodiment of the invention provides a kind of circuit critical registers triplication redundancy reinforcement means, by determining critical path
Diameter, and it is true according to the relationship of delay time of the non-critical path after carrying out triplication redundancy processing and the delay time of critical path
Fixed path to be reinforced, this method are realized simple and effective, eliminate traditional triplication redundancy reinforcement means caused by system performance not
Benefit influences, and is a kind of reinforcement means in view of hardware spending and circuit delay, improves circuit reliability, and will be because reinforcing
The overhead of generation controls in the zone of reasonableness for not influencing system performance, is of very high actual application value.
In an alternative embodiment, in the determining circuit before corresponding first time delay of each timing path, further includes:
By circuit conversion at topological digraph, each timing path is determined according to the topological digraph.
It, both can be according to need by the way that circuit conversion is determined timing path at topological digraph, and according to topological digraph
It determines start node and terminal node, and clearly can analyze and indicate the required each timing path solved, convenient for subsequent
Work.
In an alternative embodiment, it is described by circuit conversion at topological digraph, comprising:
By in circuit active trigger be mapped to the start node in topological digraph, by circuit it is all eventually trigger
Device is mapped to the terminal node in topological digraph, and each logic between the source trigger and whole trigger will be located in circuit
Unit is mapped to each intermediate node in topological digraph, by the company between the source trigger, logic unit and whole trigger
Relationship map is connect into the side in the topological digraph, signal transmission direction in circuit is mapped to the direction on the side, is obtained
The corresponding topological digraph of circuit.
This method that actual circuit is mapped to topological diagram can accurately react each path delay of time of primary circuit, so that
Circuit structure is very clear, improves the determination efficiency of critical path.
It is described that each timing path is determined according to the topological digraph in an alternative embodiment, comprising:
Will using the start node as starting point, using the terminal node as terminal, using the logic unit as intermediate point, by
The side connects the access to be formed and is determined as each timing path.
By the way that the method for being actually converted to topological digraph to be searched to the timing path of circuit, avoid because to complicated electricity
Road carry out actual analysis and measurement and caused by omit or transient error, and facilitate subsequent calculating.
In an alternative embodiment, corresponding first time delay of each timing path in the determining circuit, comprising:
It determines the corresponding source trigger of the timing path, each logic unit and whole trigger, and determines corresponding described
Source trigger, each logic unit and whole corresponding first period of the day from 11 p.m. to 1 a.m of trigger prolong；
Determine that corresponding second period of the day from 11 p.m. to 1 a.m in the corresponding each side of the timing path prolongs；
Each first period of the day from 11 p.m. to 1 a.m is prolonged the sum of to prolong with second period of the day from 11 p.m. to 1 a.m and is determined as corresponding first time delay of the timing path.
In an alternative embodiment, when corresponding second after each non-critical path progress triplication redundancy reinforcing of determination
Prolong, comprising:
It is integrated by DesignCompiler former RTL design code corresponding to the circuit, obtains the door of circuit
Grade netlist；
Triplication redundancy reinforcing is carried out to the non-critical path in the gate level netlist；
Time delay after non-critical path in the gate level netlist is carried out triplication redundancy reinforcing is as the second time delay.
This method carries out three moulds to primary circuit in RTL (register transfer) grade by EDA (electric design automation) tool
Redundancy is reinforced, rather than the circuit of physics realization is reinforced and tested, and greatly improves the efficiency of circuit design
And operability, reduce development cost；In addition, determining that register to be reinforced can reduce subsequent development step in design level
Rapid workload shortens the hardware development period.
The embodiment of the invention also provides a kind of circuit critical registers triplication redundancy bracing means, comprising:
First determining module, for determining corresponding first time delay of each timing path in circuit, and by each timing road
Diameter it is corresponding first when the maximum of Yanzhong be determined as critical path, remaining is non-critical path；
Second determining module, for determining corresponding second time delay after each non-critical path carries out triplication redundancy reinforcing；
Comparing unit, for by the second time delay of each each non-critical path respectively corresponding with the critical path
One time delay is compared, and the non-critical path by second time delay no more than corresponding first time delay of the critical path determines
For path to be reinforced；
Reinforcement elements, for carrying out triplication redundancy reinforcing wait reinforce the register on path to described.
Further, further includes:
Conversion module, for circuit conversion at topological digraph, to be determined each timing path according to the topological digraph.
Specifically, the conversion module, is used for:
By in circuit active trigger be mapped to the start node in topological digraph, by circuit it is all eventually trigger
Device is mapped to the terminal node in topological digraph, and each logic between the source trigger and whole trigger will be located in circuit
Unit is mapped to each intermediate node in topological digraph, by the company between the source trigger, logic unit and whole trigger
Relationship map is connect into the side in the topological digraph, signal transmission direction in circuit is mapped to the direction on the side, is obtained
The corresponding topological digraph of circuit.
Specifically, the conversion module, is used for:
Will using the start node as starting point, using the terminal node as terminal, using the logic unit as intermediate point, by
The side connects the access to be formed and is determined as each timing path.
Apparatus of the present invention embodiment and embodiment of the method correspond, and specifically describe and effect is referring to embodiment of the method,
This is repeated no more.
The following are a specific embodiments of the invention:
Ginseng is seen figures 3 and 4, and the present embodiment additionally provides a kind of circuit critical registers triplication redundancy reinforcement means, specific to wrap
It includes:
(1) critical path in circuit is searched:
As shown in Figure 3a, actual circuit is made of three source triggers, a whole trigger and three combinational logic gates, will
Actual circuit is converted to corresponding topological digraph, as shown in Figure 3b.The node and directed edge of digraph have respectively represented member
Device (source trigger, whole trigger, logic gate) and the connection between them, the side of the direction representation signal transmission of each edge
Our specified triggers (or other sequential logic units) of concern are indicated to, the aggregation node in digraph, in digraph
Start node indicate that the signal that is connected with specified trigger of access only by an only combinatorial logic unit exports and trigger
Device.
Wherein, by taking AD in Fig. 3 (b) as an example, the corresponding period of the day from 11 p.m. to 1 a.m of AD prolongs the Interconnection delay equal to A1- > A2 plus A2- > A3
Unit time delay.
In digraph, " the basic topology method " of all start nodes to terminal node longest path is as follows:
Each intermediate node saves a sub- time delay value V, indicates the maximum delay (starting of all start nodes to this node
0) the V value of node is.After the V value of all fan-in nodes of a node is all calculated, the V value of this node can use following formula
It calculates
A.V=max (Bi.V+D (Bi- > A))
In formula, A indicates that this node, A.V indicate A node V value, and Bi indicates i-th in the N number of fan-in node of A node, D
(Bi- > A) indicates the weight of directed edge between A and two node of Bi.
The above process is indicated using a recursive method, dummy order is as follows:
Maxdelay(A)
{
If (A is start node) A.V=0；
else
While (fan-in the node Bi, B1~Bn of traversal A)
{
Maxdelay (Bi) // obtain Bi.V
If(Bi.V+D(Bi->A)>A.V)
A.V=Bi.V+D (Bi- > A)；// searching is maximum
}
}
This method is simple and efficient, and algorithm complexity is O (V+E), and V is the number of nodes, and E is side in network
Number.
To arbitrary sequence logic unit T, only require that Maxdelay (T) can be obtained by the longest path using T as terminal node
Diameter delay, to examine whether the signal of T meets delay constraint.If it is required that obtain whole circuit " critical path " time delay,
All sequential logic units are directed toward a virtual terminal note VT with the directed edge that a weight is 0, then seek Maxdelay (VT) i.e.
It can.
It records critical path time delay Max=Maxdelay (VT), and makes marks to the register in critical path.
(2) transmission delay of novel circuit after measurement triplication redundancy is reinforced:
The register on non-critical path is reinforced in consideration.The transmission of all not labeled registers is measured respectively
Delay, is set as T.Triplication redundancy is carried out respectively to each not labeled register, the method for realizing triplication redundancy is to pass through
The synthesis tool DesignCompiler of Synopsys integrates original design, and the gate level netlist after then modification is comprehensive is again
It is comprehensive, it is described as follows:
DC comprehensive function is to read the RTL code of design and according to temporal constraint, comprehensive RTL code to structural level,
To generate the gate level netlist after a mapping, one of them important step is comprehensive library used in specified synthesis, comprehensive
Library is generally provided by flow manufacturer, contains timing of the pin to pin in library, area, and the information such as pin type and power consumption are comprehensive
Unit defined in unit in gate level netlist i.e. library after conjunction.
The reinforcing process of triplication redundancy is actually that each trigger in design generates 2 redundancy triggers and adds
Upper voting logic, and can not reflect this point in RTL code, therefore can repair to the gate level netlist after former design synthesis
Change, trigger be changed to triplication redundancy trigger, write triplication redundancy igniter module with gate level description, then with the net of modification
Table is comprehensive again together just to can be obtained the net meter file after triplication redundancy is reinforced.It is worth noting that there are many inside the comprehensive library DC
The trigger of type, such as SDFF, EDFF, SEDFF, JK, DFF only use DFF trigger even if limiting in comprehensive script,
Several kinds are had, so to write corresponding triplication redundancy igniter module for different units (its structure is as shown in Figure 4).
Additionally due to there is three tunnel clock signals, so to write clock generating module, function is that 2 tunnels of mutual delay are generated by clk
Clock signal.
Intrinsic RTL code is integrated at the synthesis tool DesignCompiler of Synopsys first, is obtained
To the gate level netlist of circuit.Circuit in gate level netlist is actually the knot that circuit is described by the unit in the comprehensive library of exampleization
Structure, formal verification tool Formality can be used verify RTL code and it is comprehensive after gate level netlist functionally whether one
It causes.
Then gate level netlist is modified, increases net type ck [2:0] in netlist, and instantiate clkgen module, then
Trigger inside netlist is changed to triplication redundancy trigger, and modifying its clock port is { clk, ck [1:0] }, due to comprehensive library
In do not contain the two modules, at this moment there have been the module that two synthesis tools are not handled, clock generating modules in netlist
With triplication redundancy igniter module, modified netlist is not just the gate level netlist after Complete Mappings.
Finally modified netlist, clock generating module and triplication redundancy igniter module are integrated again, specifically
Comprehensive is actually the synthesis to clock generating module and triplication redundancy trigger, they are mapped as the list in comprehensive library
Member, obtained gate level netlist are the gate level netlist designed after triplication redundancy is reinforced.
Triplication redundancy carried out respectively to the register on each non-critical path by the above method, measurement triplication redundancy+
The transmission delay for the new model voted, is set as N；Postponing incrementss after reinforcing is N-T.
(3) label is all reinforces register
Using Time=Max- (N-T) as standard, all non-critical paths are judged.Assuming that a certain non-critical path
Referred to as A, path delay DelayA.It is that can reinforce by the register tagging in the path if DelayA is less than Time.
If DelayA is not less than Time, it is labeled as not reinforcing.
(4) critical registers triplication redundancy is reinforced
Only the register for having reinforcing is marked to carry out triplication redundancy consolidation process to all.Method is as described in two.
The above, a specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto, appoints
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of, all by what those familiar with the art
It is covered by the protection scope of the present invention.
Unspecified part of the present invention belongs to common sense well known to those skilled in the art.
Claims (10)
1. a kind of circuit critical registers triplication redundancy reinforcement means characterized by comprising
Determine corresponding first time delay of each timing path in circuit, and each timing path is corresponding first when Yanzhong most
Big is determined as critical path, remaining is non-critical path；
Determine that each non-critical path carries out corresponding second time delay after triplication redundancy reinforcing；
By the second time delay of each each non-critical path, the first time delay corresponding with the critical path is compared respectively, will
Second time delay is determined as path to be reinforced no more than the non-critical path of corresponding first time delay of the critical path；
Triplication redundancy reinforcing is carried out wait reinforce the register on path to described.
2. circuit critical registers triplication redundancy reinforcement means according to claim 1, which is characterized in that the determining electricity
In road before corresponding first time delay of each timing path, further includes:
By circuit conversion at topological digraph, each timing path is determined according to the topological digraph.
3. circuit critical registers triplication redundancy reinforcement means according to claim 2, which is characterized in that described by circuit
It is converted into topological digraph, comprising:
By in circuit active trigger be mapped to the start node in topological digraph, all whole triggers in circuit are reflected
The terminal node in topological digraph is penetrated into, each logic unit between the source trigger and whole trigger will be located in circuit
Each intermediate node being mapped in topological digraph closes the connection between the source trigger, logic unit and whole trigger
System is mapped to the side in the topological digraph, and signal transmission direction in circuit is mapped to the direction on the side, obtains circuit
Corresponding topology digraph.
4. circuit critical registers triplication redundancy reinforcement means according to claim 3, which is characterized in that described according to institute
It states topological digraph and determines each timing path, comprising:
Will using the start node as starting point, using the terminal node as terminal, using the logic unit as intermediate point, by described
While connecting the access to be formed is determined as each timing path.
5. circuit critical registers triplication redundancy reinforcement means according to claim 4, which is characterized in that the determining electricity
Corresponding first time delay of each timing path in road, comprising:
It determines the corresponding source trigger of the timing path, each logic unit and whole trigger, and determines the corresponding source touching
Hair device, each logic unit and whole corresponding first period of the day from 11 p.m. to 1 a.m of trigger prolong；
Determine that corresponding second period of the day from 11 p.m. to 1 a.m in the corresponding each side of the timing path prolongs；
Each first period of the day from 11 p.m. to 1 a.m is prolonged the sum of to prolong with second period of the day from 11 p.m. to 1 a.m and is determined as corresponding first time delay of the timing path.
6. circuit critical registers triplication redundancy reinforcement means according to claim 3, which is characterized in that the determination is each
Non-critical path carries out corresponding second time delay after triplication redundancy reinforcing, comprising:
It is integrated by DesignCompiler former RTL design code corresponding to the circuit, obtains the gate leve net of circuit
Table；
Triplication redundancy reinforcing is carried out to the non-critical path in the gate level netlist；
Time delay after non-critical path in the gate level netlist is carried out triplication redundancy reinforcing is as the second time delay.
7. a kind of circuit critical registers triplication redundancy bracing means characterized by comprising
First determining module, for determining corresponding first time delay of each timing path in circuit, and by each timing path pair
Answer first when the maximum of Yanzhong be determined as critical path, remaining is non-critical path；
Second determining module, for determining corresponding second time delay after each non-critical path carries out triplication redundancy reinforcing；
Comparing unit, for by the second time delay of each each non-critical path respectively corresponding with the critical path first when
Prolong and be compared, by second time delay no more than corresponding first time delay of the critical path non-critical path be determined as to
Reinforce path；
Reinforcement elements, for carrying out triplication redundancy reinforcing wait reinforce the register on path to described.
8. circuit critical registers triplication redundancy bracing means according to claim 7, which is characterized in that further include:
Conversion module, for circuit conversion at topological digraph, to be determined each timing path according to the topological digraph.
9. circuit critical registers triplication redundancy bracing means according to claim 8, which is characterized in that the modulus of conversion
Block is used for:
By in circuit active trigger be mapped to the start node in topological digraph, all whole triggers in circuit are reflected
The terminal node in topological digraph is penetrated into, each logic unit between the source trigger and whole trigger will be located in circuit
Each intermediate node being mapped in topological digraph closes the connection between the source trigger, logic unit and whole trigger
System is mapped to the side in the topological digraph, and signal transmission direction in circuit is mapped to the direction on the side, obtains circuit
Corresponding topology digraph.
10. circuit critical registers triplication redundancy bracing means according to claim 9, which is characterized in that the conversion
Module is used for:
Will using the start node as starting point, using the terminal node as terminal, using the logic unit as intermediate point, by described
While connecting the access to be formed is determined as each timing path.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111525919A (en) * | 2020-05-27 | 2020-08-11 | 上海微阱电子科技有限公司 | Redundancy structure with feedback correction |
| CN111914504A (en) * | 2020-07-17 | 2020-11-10 | 中科亿海微电子科技（苏州）有限公司 | Triple-modular redundancy method and device of application circuit |
| CN114492273A (en) * | 2022-01-18 | 2022-05-13 | 中国人民解放军国防科技大学 | Satellite load BRAM anti-radiation design method based on position constraint |
| CN116911226A (en) * | 2023-08-01 | 2023-10-20 | 上海合见工业软件集团有限公司 | Super node extraction method and system |
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| CN104778324A (en) * | 2015-04-16 | 2015-07-15 | 合肥工业大学 | Integrated circuit selective reinforcement method with aging delaying and soft error tolerance functions |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111525919A (en) * | 2020-05-27 | 2020-08-11 | 上海微阱电子科技有限公司 | Redundancy structure with feedback correction |
| CN111525919B (en) * | 2020-05-27 | 2023-09-26 | 上海微阱电子科技有限公司 | Redundant structure with feedback correction |
| CN111914504A (en) * | 2020-07-17 | 2020-11-10 | 中科亿海微电子科技（苏州）有限公司 | Triple-modular redundancy method and device of application circuit |
| CN111914504B (en) * | 2020-07-17 | 2024-03-15 | 中科亿海微电子科技（苏州）有限公司 | Triple-modular redundancy method and device for application circuit |
| CN114492273A (en) * | 2022-01-18 | 2022-05-13 | 中国人民解放军国防科技大学 | Satellite load BRAM anti-radiation design method based on position constraint |
| CN116911226A (en) * | 2023-08-01 | 2023-10-20 | 上海合见工业软件集团有限公司 | Super node extraction method and system |
| CN116911226B (en) * | 2023-08-01 | 2024-03-08 | 上海合见工业软件集团有限公司 | Super node extraction method and system |
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| CN110083492B (en) | 2023-03-07 |
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