CN111525919A - Redundancy structure with feedback correction - Google Patents
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Abstract
The invention provides a redundant structure with feedback correction. The redundancy structure comprises a redundancy module and a feedback refreshing module, wherein units to be reinforced are arranged on a plurality of redundancy paths of the redundancy module, the redundancy module is used for obtaining redundancy output signals of the corresponding units to be reinforced and carrying out majority voting on all the redundancy output signals to obtain reinforced output signals, the feedback refreshing module receives all the redundancy output signals, corresponding feedback signals are output to all the redundancy paths after detection, and when the feedback signals are abnormal in representation, the redundancy module resets one redundancy path output signal corresponding to the feedback signals to the current reinforced output signal. When the output signals of a few redundant paths are wrong, the redundant structure resets the output signals of the wrong redundant paths in time, so that the error accumulation of the output signals of the redundant paths is avoided, and the input signals of the redundant paths which are not wrong can be updated normally.
Description
Technical Field
The invention relates to the technical field of semiconductor integrated circuits, in particular to a redundant structure with feedback correction.
Background
When an integrated circuit device works in a severe environment, logic errors may occur in the circuit, which mainly include the generation of glitches in combinational logic and the occurrence of state flip in a sequential logic circuit, and further may cause errors in the overall logic function of a chip. Therefore, it is very important to develop a method capable of effectively dealing with logic errors of an integrated circuit device under a severe environment.
A common coping method is to use a triple modular redundancy structure. The basic idea is to copy the unit to be reinforced into three parts, and output the three output results after majority voting, so that the circuit can still work normally even if one unit has an error. However, this structure has a serious problem. For example, when a certain path of data in the triple modular redundancy structure has an error, the error data is latched by the data storage unit and is kept. If a second path of data in the three redundant paths has errors after a long period of time, the error result can be output after the data is voted by the majority voter.
For this reason, Liujiaqi et al in Chinese patent CN108055031A propose a triple modular redundancy structure for self-recovery and resistance to single event soft error accumulation. Compared with the traditional triple-modular redundancy structure, the circuit is additionally provided with an error detection circuit. When the error detection circuit finds that the output results of the three paths of redundant structures are inconsistent, the three triggers are reset or set according to the correct result output by the voting circuit. The method can keep the current output result of the circuit for one clock cycle when the circuit has errors, thereby avoiding the error data from being continuously kept in the trigger. The method is suitable for places where data is not frequently refreshed, such as register modules, but the reinforced structure has defects. For example, when the triple modular redundancy structure is used for a module with frequently changing internal register data, when a logic error occurs in one of the redundant paths, the triple modular redundancy structure feeds a majority voting result back to three flip-flops, so that the majority voting result is kept for one clock cycle. If the input data just changes at this time, all the three triggers are refreshed by the data of the previous beat instead of receiving the correct data of the input end, all the data of the three redundant paths are in error, and the circuit function is in error at this time.
Disclosure of Invention
The invention provides a redundant structure with feedback correction, which aims to avoid error accumulation of redundant output signals of each path in the redundant structure and simultaneously not influence data updating of signals at input ends of each redundant path.
In order to achieve the above object, an aspect of the present invention provides a redundant structure with feedback correction, including a redundant module, where the redundant module includes multiple redundant paths, each redundant path is provided with a unit to be reinforced, and the redundant module is configured to obtain redundant output signals of the corresponding units to be reinforced, and perform majority voting on all the redundant output signals to obtain reinforced output signals; and
the feedback refreshing module receives each redundant output signal, outputs corresponding feedback signals to each redundant path after detection, and indicates that the output signals of the corresponding redundant paths are in error when the feedback signals are abnormal in representation;
wherein the redundancy module resets an output signal of a redundant path corresponding to the feedback signal characterizing the anomaly to the ruggedized output signal.
Optionally, the redundancy module includes a majority voting unit, and a combinational logic unit, a selection unit, and a data storage unit that are disposed in each of the redundancy paths; the redundancy structure input signal is input from the input end of the combinational logic unit, the output end of the combinational logic unit is connected with one input end of the selection unit, the other input end of the selection unit is connected with the output end of the majority voting unit, the control end of the selection unit is connected with the corresponding output end of the feedback refreshing module to obtain the corresponding feedback signal, the output end of the selection unit is connected with one input end of the data storage unit, and the output end of each data storage unit is connected with the corresponding input ends of the majority voting unit and the feedback refreshing module; when the feedback signal is abnormal, the selection unit outputs the reinforced output signal to the data storage unit.
Optionally, the redundancy module is a triple-modular redundancy module, and the redundancy module obtains redundancy output signals of the corresponding to-be-reinforced electrical units by using three redundancy paths respectively.
Optionally, the majority voting unit has a circuit structure satisfying a first logical relationship Q-Q0 · Q1+ Q0 · Q2+ Q1 · Q2, where Q is an output signal of the majority voting unit, and Q0, Q1, and Q2 are redundant output signals of three redundant paths.
Optionally, the majority voting unit includes three two-input and gates and one three-input or gate, the input end of each two-input and gate is respectively connected to two paths of the redundant output signals, the redundant output signals connected to any two-input and gates are not identical, the output end of each two-input and gate is respectively connected to one input end of the three-input or gate, and the output end of the three-input or gate outputs the reinforced output signal.
Optionally, the feedback refreshing module includes a plurality of minority voting units, and the minority voting units satisfy a second logical relationship
Wherein P0 is the output signal of the minority voting unit, Q0, Q1 and Q2 are the redundant output signals of the three redundant paths, and Q0 is the main path input signal in the minority voting unit, and Q1 and Q2 are the slave path input signals in the minority voter.
Optionally, the input ends of the minority voting units are connected to all the redundant output signals, and the output end of each minority voting unit is connected to the control end of the selection unit in one of the redundant paths; when the minority voting unit detects that the redundant output signals of the redundant paths connected with the output end of the minority voting unit are minority in the three redundant output signals, the feedback signals output by the minority voting unit are high level; when the minority voting unit detects that the redundant output signals of the redundant paths connected with the output ends of the minority voting unit are majority in the three redundant output signals, the feedback signals output by the minority voting unit are at low level.
Optionally, the minority voting unit includes two three-input and gates and a two-input or gate, the input end of each three-input and gate is connected to three paths of the redundant output signals, the output end of each three-input and gate is connected to one input end of the two-input or gate, and the output end of the two-input or gate outputs the feedback signal.
Optionally, the unit to be consolidated includes a combinational logic unit and the data storage unit.
Optionally, the data storage unit is a trigger; one input end of the trigger is connected with the output end of the selection unit, and the other input end of the trigger is connected with a time sequence control signal.
Optionally, each of the flip-flops is connected to the same timing control signal.
The redundancy structure with feedback correction provided by the invention comprises a redundancy module, wherein the redundancy module comprises a plurality of redundancy paths, each redundancy path is provided with a unit to be reinforced, the redundancy module is used for obtaining redundancy output signals of the corresponding circuit units to be reinforced and carrying out majority voting on all the redundancy output signals to obtain reinforced output signals, and correct output can still be obtained when a few redundancy output signals are wrong, the redundancy structure also comprises a feedback refreshing module, the feedback refreshing module receives the redundancy output signals output by each redundancy path, outputs corresponding feedback signals to each redundancy path after detection, and indicates that the corresponding redundancy path output signals are wrong when the feedback signals are abnormal in characterization, wherein the redundancy module resets the output signals of the redundancy paths corresponding to the feedback signals which are abnormal in characterization to the reinforced output signals at the current moment, the error of the redundant output signal can be corrected in time, and the error of the reinforced output signal caused by the fact that the error accumulation of each path of redundant output signal reaches a plurality of paths is avoided. In addition, because the feedback refreshing module only outputs abnormal feedback signals to the redundant paths with errors, the redundant paths without errors still receive normal feedback signals, can work normally, and do not need to spend one clock cycle for resetting, namely, by using the redundant structure, when errors of a few redundant output signals are corrected in time, the redundant paths without errors can normally receive input signals, namely, normal data updating can be carried out, even if the input signals of the redundant structure are changed during error correction, because the change is timely received and processed by the normal redundant paths, the updated reinforced output signals can be obtained after majority voting, and the circuit function cannot be influenced.
Drawings
Fig. 1 is a schematic diagram of basic structural units of a redundant structure.
Fig. 2 is a schematic diagram of a conventional triple modular redundancy structure.
Fig. 3 is a schematic diagram of a redundancy structure with feedback correction according to an embodiment of the present invention.
FIG. 4 is a logic diagram of a majority voting unit according to an embodiment of the present invention.
Fig. 5 is a logic diagram of a feedback refresh module according to an embodiment of the invention.
Fig. 6 is a logic diagram of a main path minority voter according to an embodiment of the invention.
Description of reference numerals:
101-a first combinational logic unit; 102-a second combinational logic cell; 103-a third combinational logic unit; 201-a first selection unit; 202-a second selection unit; 203-third selection unit; 301-a first flip-flop; 302-a second flip-flop; 303-a third flip-flop; 401-majority voting unit; 410-two input and gate; 420-three input or gate; 501-a feedback refresh module; 510-a first minority voting unit; 511-a second minority voting unit; 512-a third minority voting unit; 520-three input and gate; 521-two input or gate.
Detailed Description
The redundant structure with feedback correction and the integrated circuit chip according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is provided solely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. For the sake of clarity, in all the drawings for assisting the description of the embodiments of the present invention, the same components are denoted by the same reference numerals in principle, and the duplicated description thereof is omitted.
To facilitate understanding of the technical problem to be solved by the present invention, a triple modular redundancy structure is first introduced below. Fig. 1 is a schematic diagram of basic structural units of a redundant structure. Fig. 2 is a schematic diagram of a conventional triple modular redundancy structure. As shown in fig. 1, a basic structure unit (a unit to be reinforced) of a conventional redundant structure includes a combinational logic unit and a flip-flop, a signal input terminal of the combinational logic unit receives a redundant structure input signal D, a signal output terminal of the combinational logic unit is connected to one signal input terminal of the flip-flop, and the flip-flop outputs a redundant output signal. As shown in fig. 2, the conventional triple modular redundancy structure includes three redundancy paths, input signals D of the redundancy structure are respectively transmitted to three flip-flops through combinational logic units in the three redundancy paths, redundant output signals obtained on the three redundancy paths are stored in the flip-flops, and a majority voting unit 401(Voter) receives the redundant output signals output by the three flip-flops and outputs a reinforced output signal after majority voting. By utilizing majority voting, when no error occurs in all three redundant output signals, or when the redundant output signal obtained by a certain redundant path has an error and the other two redundant output signals have no errors, the correct reinforced output signal can be output according to the redundant output signal which becomes the majority. When a certain redundant path in the triple modular redundancy structure has errors and causes the stored redundant data to be wrong, the wrong redundant output signal can be ignored and the correct output can be obtained according to the other two paths of redundant outputs, but if the wrong redundant output signal is not corrected in time and is kept for a long time, if the redundant data (or the redundant output signal) output by the other redundant path has errors after a period of time, the wrong reinforced output signal can be output after the redundant data (or the redundant output signal) is voted by the majority voter. The inventor finds that if a certain path of redundant output signal is found to be wrong, namely, the reinforced output signal is used for resetting or setting all the three triggers, although the situation that wrong data is kept in the triggers is avoided, the reinforced output signal is kept for one clock cycle, the triggers cannot receive the newly input redundant structure input signal D, if the redundant structure input signal D is changed, all the output data of the three redundant paths are wrong, and the circuit function is also wrong at the moment, so that the normal updating of the redundant output signal is influenced.
In order to avoid error accumulation of each path of redundant output signal in the redundant structure and not affect normal updating of the redundant output signal, the embodiment of the present invention includes a redundant structure with feedback correction, which is described in detail below.
The redundancy structure comprises a redundancy module and a feedback refreshing module, wherein the redundancy module comprises a plurality of redundancy paths, each redundancy path is provided with a unit to be reinforced, the redundancy module is used for obtaining redundancy output signals of the corresponding unit to be reinforced and carrying out majority voting on all the redundancy output signals to obtain reinforced output signals, the feedback refreshing module receives each redundancy output signal, outputs corresponding feedback signals to each redundancy path after detection, and when the feedback signals are abnormal in representation, the output signals of the corresponding redundancy paths are indicated to be in error; wherein the redundancy module resets an output signal of a redundant path corresponding to the feedback signal characterizing the anomaly to the ruggedized output signal.
Fig. 3 is a schematic diagram of a redundancy structure with feedback correction according to an embodiment of the present invention. As an example, the redundancy structure shown in fig. 3 is a triple modular redundancy structure, but it is to be understood that the redundancy structure of the present invention is not limited to being a triple modular redundancy structure. In this embodiment, the redundancy module may be a triple modular redundancy module, and the redundancy module may obtain the redundancy output signals of the corresponding units to be reinforced by using three redundancy paths, respectively. However, in other embodiments, the redundancy module may be a five-module redundancy module or a seven-module redundancy module, or other odd redundancy modules including odd redundancy paths. For a triple modular redundancy module, when one redundancy path has an error, the redundancy module outputs a reinforced output signal according to the outputs of the other two redundancy paths when carrying out majority voting. For a five-modulus redundant module, when one or two redundant paths are wrong, a reinforced output signal is output according to the outputs of the other four or three redundant paths when majority voting is carried out. For a seven-module redundancy module, when less than three redundant paths are in error, a reinforced output signal is output according to the output of more than three other redundant paths.
Specifically, as shown in fig. 3, in this embodiment, the redundancy module may include a majority voting unit 401, and a combinational logic unit, a selection unit, and a data storage unit that are disposed in each of the redundancy paths; a redundant structure input signal D is input from an input end of the combinational logic unit, an output end of the combinational logic unit is connected with one input end of the selection unit, another input end of the selection unit is connected with an output end of the majority voting unit, a control end of the selection unit is connected with a corresponding output end of the feedback refreshing module to obtain a corresponding feedback signal, an output end of the selection unit is connected with one input end of the data storage unit, and an output end of each data storage unit is connected with a corresponding input end of the majority voting unit 401 and the feedback refreshing module 501; when the feedback signal represents an abnormality, the selection unit outputs the reinforcement output signal Q to the data storage unit.
The plurality of redundant paths in the redundant structure may have the same structure. The data storage unit may be a flip-flop, such as a D flip-flop. One input end of each trigger is connected with the output end of the selection unit, the other input end of each trigger is connected with a time sequence control signal, each trigger is connected with the same time sequence control signal CK, and the time sequence control signal CK controls the corresponding trigger to output the redundant output signals. The trigger can also be provided with a reset end or a position end.
It should be noted that the to-be-hardened unit disposed in each redundant path in this embodiment may include a combinational logic unit and the data storage unit, for example, the to-be-hardened unit may include the first combinational logic 101 and the first data storage unit (the first flip-flop 301). However, in other embodiments, the unit to be hardened may include only a data storage unit, and the unit to be hardened may also be other structures including a sequential logic circuit and a data storage unit.
It should be understood that the combinational logic cell may be a combination comprising any basic logic gates. The combinational logic unit receives a redundant structure input signal D, the output signal of the combinational logic unit is selectively input to the trigger according to the feedback signal, namely when the feedback signal is represented normally, the selection unit selects to transmit the output signal of the combinational logic unit to the corresponding trigger, and when the feedback signal is represented abnormally, the selection unit selects to transmit the reinforced output signal to the corresponding trigger. The redundancy module resets the output signal of the redundancy path corresponding to the feedback signal representing the abnormality to the current reinforced output signal by resetting the input signal of the corresponding data storage unit by using the corresponding selection unit, so as to achieve the purposes of resetting the latched data in the corresponding data storage unit and changing the output signal of the data storage unit. The redundant paths can be provided with a combined logic unit, a selection unit and a trigger, each redundant path corresponds to one path of redundant output signals, and the output signals are output after majority voting is carried out on the output signals, so that the influence of burrs generated by the combined logic unit or the state reversal of the sequential logic circuit on the functions of a subsequent circuit is reduced.
With continued reference to fig. 3, the redundancy module may include three redundancy paths, where a first combination logic unit 101, a first selection unit 201, and a first flip-flop 301 are disposed on a first redundancy path, and a signal input end of the first redundancy path is connected to a redundancy structure input signal D; a second combinational logic unit 102, a second selection unit 202 and a second trigger 302 are arranged on the second redundant path, and a signal input end of the second redundant path is connected with a redundant structure input signal D; the third redundant path may include a third combinational logic unit 103, a third selector 203, and a third flip-flop 302, and a signal input terminal of the third redundant path is connected to the redundant configuration input signal D. The redundant module further comprises a majority voting unit 401(voter), signal output ends of the first flip-flop 301, the second flip-flop 302 and the third flip-flop 303 are all connected to a signal input end of the majority voting unit 401 respectively, the majority voting unit 401 outputs a reinforced output signal Q after majority voting, and meanwhile, a signal output end of the majority voting unit 401 is also connected to one signal input end of each selection unit.
The majority voting unit 401 of the present embodiment may be a majority voter, and specifically may be a three-input majority voter. The majority voting unit 401 may have a circuit structure that satisfies a first logical relationship Q-Q0 · Q1+ Q0 · Q2+ Q1 · Q2, where Q is the output signal (the hardened output signal) of the majority voting unit, and Q0, Q1, and Q2 are the redundant output signals of the three redundant paths. FIG. 4 is a logic diagram of a majority voting unit according to an embodiment of the present invention. As shown in fig. 4, as an example, the majority voting unit adopted by the redundancy module of this embodiment may include three two-input and gates 410 and a three-input or gate 420, the input end of each two-input and gate 410 is respectively connected to two paths of the redundancy output signals, the redundancy output signals connected to any two-input and gates 410 are not identical, the output end of each two-input and gate 410 is respectively connected to one input end of the three-input or gate 420, and the output end of the three-input or gate 420 outputs the hardened output signal Q. But not limited thereto, the majority voting unit may also use other circuit designs to implement the above-described functions.
The redundant module of the redundant structure can respectively obtain redundant output signals of corresponding units to be reinforced by utilizing a plurality of redundant paths, and carries out majority voting on all the redundant output signals to obtain reinforced output signals. Meanwhile, in order to correct the redundant output signals when errors occur, avoid the error accumulation of each path of redundant output signals in a redundant structure and not influence the data updating of the input signals of the normal redundant path, the redundant structure further comprises a feedback refreshing module, the feedback refreshing module receives each redundant output signal, outputs corresponding feedback signals to each redundant path after detection, and indicates that the corresponding redundant path output signals are in errors when the feedback signals are abnormal in characterization, wherein the redundant module resets the output signals of the redundant paths corresponding to the feedback signals with abnormal characterization to the reinforced output signals.
And the minority voting unit receives each redundant output signal and carries out minority voting so as to judge whether each redundant output signal has errors and output different feedback signals. Specifically, the feedback refresh module 501 may include a plurality of minority voting units, for example, the feedback refresh module 501 includes three minority voting units, and the first minority voting unit satisfies a logical relationship
The circuit structure of (1), wherein P0 is the output signal (feedback signal) of the first minority voting unit, Q0, Q1 and Q2 are the redundant output signals of the three redundant paths, and Q0 is the main path input signal in the first minority voting unit, Q1 and Q2 are the slave path input signals in the first minority voter; the second minority voting unit satisfies the logic relationship
The circuit structure of (1), wherein P1 is the output signal (feedback signal) of the second minority voting unit, Q0, Q1 and Q2 are the redundant output signals of the three redundant paths, and Q1 is the main path input signal in the second minority voting unit, Q0 and Q2 are the slave path input signals in the second minority voter; the third minority voting unit satisfies the logic relationship
Wherein P2 is the output signal (feedback signal) of the third minority voting unit, Q0, Q1, and Q2 are the redundant output signals of the three redundant paths, and Q2 is the main path input signal in the third minority voting unit, and Q0 and Q2 are the slave path input signals in the third minority voter.
Optionally, the input ends of the minority voting units are connected to all the redundant output signals, and the output end of each minority voting unit is connected to the control end of the selection unit in one of the redundant paths; when the minority voting unit detects that the redundant output signals of the redundant paths connected with the output end of the minority voting unit are minority in the three redundant output signals, the feedback signals output by the minority voting unit are high level; when the minority voting unit detects that the redundant output signals of the redundant paths connected with the output ends of the minority voting unit are majority in the three redundant output signals, the feedback signals output by the minority voting unit are at low level.
Fig. 5 is a logic diagram of a feedback refresh module according to an embodiment of the invention. As shown in FIG. 5, the feedback refresh module includes a plurality of minority voting units, including, for example, a first minority voting unit 510, a second minority voting unit 511, and a third minority voting unit 512. Fig. 6 is a logic diagram of a main path minority voter according to an embodiment of the invention. As shown in fig. 6, the minority voting unit may include two three-input and gates 520 and a two-input or gate 521, an input terminal of each three-input and gate 520 is connected to three paths of the redundant output signals, an output terminal of each three-input and gate 520 is connected to one input terminal of the two-input or gate 521, and an output terminal of the two-input or gate 521 outputs a feedback signal.
More specifically, the output terminals of the first flip-flop 301, the second flip-flop 302, and the third flip-flop 303 are simultaneously connected to three input terminals of the feedback refresh module 501, respectively, and a plurality of output terminals of the feedback refresh module 501 are connected to the control terminals of the corresponding first selecting unit 201, the second selecting unit 202, and the third selecting unit 203, respectively. Because each minority voting unit corresponds to each redundant path one by one, and each redundant path is provided with a corresponding selection unit, feedback signals output by each minority voting unit can independently control each selection unit, so that the input signals of the data storage units in the faulty redundant paths can be selectively reset by using the reinforced output signals instead of resetting the input signals of the data storage units in all the redundant paths, the redundant paths which are not reset can normally receive newly input data, and the redundant modules can still output updated reinforced output signals after majority voting, so that the data updating of the redundant output signals is not influenced by error correction of the redundant structure.
The minority voting unit can be a main path minority voter. As shown in fig. 5, when the feedback refresh module 501 operates, the first minority voting unit 510 takes the first redundant output signal Q0 as a master path signal, and the second redundant output signal Q1 and the third redundant output signal Q2 as slave path signals; the second minority voting unit 511 takes the second redundant output signal Q1 as a master path signal, and the first redundant output signal Q0 and the third redundant output signal Q2 as slave path signals; the third minority voting unit 512 uses the third redundant output signal Q2 as the master path signal, and the first redundant output signal Q0 and the second redundant output signal Q1 as the slave path signals. When the first redundant output signal Q0 is 1, the second redundant output signal Q1 is 0, and the third redundant output signal Q2 is 0; or when the first redundant output signal Q0 is 0, the second redundant output signal Q1 is 1, and the third redundant output signal Q2 is 1, that is, the first redundant output signal is a minority of redundant output signals, which indicates that the first redundant output signal Q0 is faulty, the first feedback signal P0 is at a high level (indicated as 1), the first selection unit 201 selects to transmit the reinforcement output signal Q to the input terminal of the first flip-flop 301, that is, resets the latched data in the first flip-flop 301 to the reinforcement output signal Q, and the reinforcement output signal Q remains for one clock cycle on the faulty redundant path; at this time, the second feedback signal P1 and the third feedback signal P2 are at low level (indicated as 0), indicating that the second redundant output signal Q1 and the third redundant output signal Q2 are not faulty, and the second selection unit 202 and the third selection unit 203 respectively select to transmit the output signals of the second combinational logic unit 102 and the third combinational logic unit 103 to the second flip-flop 302 and the third flip-flop 303.
It should be noted that the combinational logic unit can perform a logic operation on its input signal (the redundant structure input signal D), and the logic operation in the combinational logic unit can be set as needed, that is, when the input signal is at a high level, the combinational logic unit can be set to output a low level or a high level. The following description will be made by taking an example in which the case where the combinational logic cell outputs a high level when the input level is high is correct.
As an example, when signal reinforcement is performed using the redundant configuration shown in fig. 3, a timing control circuit is used for timing control. When the first clock cycle redundancy structure input signal D is 1 and the first redundancy path has an error, for the first clock cycle, in one case, the first combinational logic unit 101 has an error, the output signal I0 of the first combinational logic unit 101 is 0, the output signal I1 of the second combinational logic unit 102 is 1, the output signal I2 of the third combinational logic unit 103 is 1, the output signal D0 of the first selection unit 201 is 0, the output signal D1 of the second selection unit 202 is 1, the output signal D2 of the third selection unit 203 is 1, the first redundancy output signal Q0 is 0, the second redundancy output signal Q1 is 1 and the third redundancy output signal Q2 is 1, and the reinforced output signal Q output by the majority voting unit 401 after majority voting is 1; in another case, the first flip-flop 301 goes wrong, the output signal I0 of the first combinational logic unit 101 is 1, the output signal D0 of the first selector 201 is 1, the first redundant output signal Q0 is 0, the second redundant output signal Q1 is 1, and the third redundant output signal Q2 is 1, where the first redundant output signal Q0 is 0 and is a minority. In this clock cycle, the majority voting unit 401 outputs the reinforced output signal Q of 1 after majority voting, the minority voting unit 501 outputs different feedback signals after detecting the first redundant output signal Q0, the second redundant output signal Q1, and the third redundant output signal Q2, and based on the determination that the first redundant output signal Q0 is faulty, the corresponding first feedback signal P0 is at a high level (indicated as 1), and the second redundant output signal Q1 and the third redundant output signal Q2 are determined to be non-faulty, so the corresponding second feedback signal P1 and the third feedback signal P2 are at a low level (indicated as 0).
In a second clock cycle, the redundancy module resets the input signal of the first flip-flop 301 by using the reinforced output signal output in the first clock cycle, and in one case, when the redundant structure input signal D is 1 (same as the first clock cycle), since the reinforced signal Q (1) output in the first clock cycle is not faulty, the first redundant output signal Q0 (1) output by the first flip-flop 301 reset to the reinforced output signal Q is not faulty, and since the second redundant path and the third redundant path are not faulty, the output second redundant output signal Q1 (1) and the output second redundant output signal Q2 (1) are not faulty, and thus after majority voting, the reinforced output signal output by the redundant structure is 1 and no fault occurs. In another case, the input signal D of the redundant structure is 0 (different from the first clock cycle) in the second clock cycle, the first redundant output signal Q0 (1) output by the first flip-flop 301 that is reset to the reinforced output signal Q is faulty, but since the second redundant path and the third redundant path are not faulty, it does not need to take one clock cycle to reset, the second selection unit 202 and the third selection unit 203 will select to transmit the output signals of the second combinational logic unit 102 and the third combinational logic unit 103 to the second flip-flop 202 and the third flip-flop 203, so as to obtain the correct second redundant output signal Q1 (0) and the correct third redundant output signal Q2 (0), and after majority voting, the redundant structure still outputs the correct reinforced output signal Q (0). Therefore, when a few redundant paths have errors, the redundant structure with feedback correction of the embodiment can not only reset the erroneous redundant output signals so that the error data is not kept, but also output correct reinforced output signals regardless of whether the input signal of the redundant structure in the second clock period is the same as the input signal of the first clock period, and the data updating of the redundant output signals is not influenced by error correction.
The redundancy structure with feedback correction of this embodiment includes a redundancy module, where the redundancy module includes multiple redundancy paths, each redundancy path is provided with a unit to be reinforced, the redundancy module is configured to obtain a redundancy output signal of a corresponding circuit unit to be reinforced, and perform majority voting on all the redundancy output signals to obtain a reinforced output signal, and may still obtain a correct output when a few redundancy output signals are in error, and the redundancy structure of this embodiment further includes a feedback refresh module, where the feedback refresh module receives the redundancy output signals output by each redundancy path, performs detection and outputs corresponding feedback signals to each redundancy path, and when the feedback signals are characterized to be abnormal, indicates that the corresponding redundancy path output signals are in error, where the redundancy module resets output signals of the redundancy paths corresponding to the feedback signals characterized to the reinforced output signals, the error of the redundant output signal can be corrected in time, and the error of the reinforced output signal caused by the fact that the error accumulation of each path of redundant output signal reaches a plurality of paths is avoided. In addition, because the feedback refreshing module only outputs abnormal feedback signals to the redundant paths with errors, the redundant paths without errors still receive normal feedback signals, can work normally, and do not need to spend one clock cycle for resetting, namely, by using the redundant structure, when errors of a few redundant output signals are corrected in time, the redundant paths without errors can normally receive input signals, namely, normal data updating can be carried out, even if the input signals of the redundant structure are changed during error correction, because the change is timely received and processed by the normal redundant paths, updated reinforced output signals can be obtained after majority voting, the circuit function cannot be influenced, and the probability of outputting the reinforced output signals with errors by the circuit can be reduced.
In detail, when a combinational logic unit corresponding to a few redundant paths has an error, including a selection unit connected to an output end of the combinational logic unit has an error, since the glitch of the combinational logic unit can only be maintained for a short time, on one hand, the glitch of the combinational logic unit may not be collected by a subsequent trigger, and a reinforcement output signal output by the redundant structure will not have an error, on the other hand, since the redundant output signal output after the trigger collects an input signal is transmitted to a few voting units, even if the redundant output signal has an error, the redundancy output signal can be detected by the few voting units and the erroneous redundant output signal can be reset, that is, the reinforcement output signal is kept for one beat in the erroneous redundant path, and the reinforcement output signal output by the redundant structure with feedback correction still has no.
When a data storage unit (such as a trigger) of a few redundant paths has an error, the redundant output signal which can be detected by a few voting units and has the error is reset, so that the reinforced output signal output by the redundant structure with feedback correction is still correct, and meanwhile, the error data of the data storage unit with the error cannot be maintained.
Further, the majority voting unit (majority voter) and the minority voting unit (main path minority voter) in the redundancy structure described in this embodiment respectively and independently receive the redundant output signal and respectively output the reinforced output signal and the feedback signal, when one of the majority voting unit and the minority voting unit has an error, the other one can still work normally, and the circuit still has the possibility of outputting the correct reinforced output signal.
In detail, when 1 main path minority voter has an error, the majority voting unit has no error, and the majority redundancy output signal has no error, because the majority voting unit independently receives each redundancy output signal, after majority voting, the output reinforcement output signal still has no error, at this time, the correct reinforcement output signal is used to reset the corresponding trigger, that is, the current reinforcement output signal is kept in the trigger for one clock cycle, and the reinforcement output signal output by the redundancy structure with feedback correction still has no error.
When 2 or 3 main path minority voters go wrong at the same time, the majority voting unit goes wrong and the majority redundancy output signal goes wrong, the current correct reinforcement output signal is used for resetting the corresponding trigger, namely the current reinforcement output signal keeps a clock period in the trigger, if the redundancy structure input signal D of the next clock period is inverted, the reinforcement output signal output by the redundancy structure with feedback correction goes wrong in the next clock period, but because the main path minority voter is combinational logic, the wrong data cannot be latched and the data can be updated in the next clock period.
When the majority voting unit has errors, the minority voting unit has no errors and the majority redundancy output signal has no errors, only the currently output reinforcement output signal has errors, but because the majority voting unit can not latch data and the minority voting unit independently receives each redundancy output signal, after the minority voting unit has the errors, the feedback signals input by the minority voting unit can not have errors, the selection unit can not reset the redundancy output signal by using the reinforcement output signal having the errors, the majority voting unit can be refreshed by the signal of the next clock period, the re-output reinforcement output signal is still correct, and meanwhile, the error data can not be maintained.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
Claims (11)
1. A redundant structure with feedback correction, comprising:
the redundancy module comprises a plurality of redundancy paths, each redundancy path is provided with a unit to be reinforced, and the redundancy module is used for obtaining redundancy output signals of the corresponding units to be reinforced and carrying out majority voting on all the redundancy output signals to obtain reinforced output signals; and
the feedback refreshing module receives each redundant output signal, outputs corresponding feedback signals to each redundant path after detection, and indicates that the output signals of the corresponding redundant paths are in error when the feedback signals are abnormal in representation;
wherein the redundancy module resets an output signal of a redundant path corresponding to the feedback signal characterizing the anomaly to the ruggedized output signal.
2. The redundancy architecture of claim 1, wherein the redundancy modules comprise a majority voting unit and a combinational logic unit, a selection unit, and a data storage unit disposed on each of the redundancy paths; the redundancy structure input signal is input from the input end of the combinational logic unit, the output end of the combinational logic unit is connected with one input end of the selection unit, the other input end of the selection unit is connected with the output end of the majority voting unit, the control end of the selection unit is connected with the corresponding output end of the feedback refreshing module to obtain the corresponding feedback signal, the output end of the selection unit is connected with one input end of the data storage unit, and the output end of each data storage unit is connected with the corresponding input ends of the majority voting unit and the feedback refreshing module; when the feedback signal is abnormal, the selection unit outputs the reinforced output signal to the data storage unit.
3. The redundancy scheme according to claim 2, wherein the redundancy module is a triple modular redundancy module, which uses three redundancy paths to obtain redundant output signals of the respective cells to be consolidated, respectively.
4. The redundancy scheme of claim 3 wherein the majority voting unit is a circuit structure that satisfies a first logical relationship Q0-Q1 + Q0-Q2 + Q1-Q2, wherein Q is the output signal of the majority voting unit and Q0, Q1, and Q2 are the redundant output signals of the three redundant paths.
5. The redundancy structure of claim 4, wherein the majority voting unit comprises three two-input AND gates and a three-input OR gate, wherein two paths of the redundant output signals are respectively connected to input ends of each two-input AND gate, the redundant output signals connected to any two-input AND gates are not identical, an output end of each two-input AND gate is respectively connected to one input end of the three-input OR gate, and an output end of the three-input OR gate outputs the reinforced output signal.
6. The redundancy scheme of claim 3 wherein the feedback isThe refreshing module comprises a plurality of minority voting units satisfying a second logic relationship
Wherein P0 is the output signal of the minority voting unit, Q0, Q1 and Q2 are the redundant output signals of the three redundant paths, and Q0 is the main path input signal in the minority voting unit, and Q1 and Q2 are the slave path input signals in the minority voter.
7. The redundancy architecture of claim 6, wherein the inputs of the minority voting units are coupled to all of the redundant output signals, and the output of each of the minority voting units is coupled to the control of a selection unit within one of the redundant paths; when the minority voting unit detects that the redundant output signals of the redundant paths connected with the output end of the minority voting unit are minority in the three redundant output signals, the feedback signals output by the minority voting unit are high level; when the minority voting unit detects that the redundant output signals of the redundant paths connected with the output ends of the minority voting unit are majority in the three redundant output signals, the feedback signals output by the minority voting unit are at low level.
8. The redundancy architecture of claim 6, wherein said minority voting unit comprises two three-input AND gates and a two-input OR gate, wherein an input of each of said three-input AND gates receives three of said redundant output signals, an output of each of said three-input AND gates is connected to an input of said two-input OR gate, and an output of said two-input OR gate outputs said feedback signal.
9. The redundancy structure of claim 2, wherein the cells to be consolidated comprise the combinational logic cells and the data storage cells.
10. The redundancy scheme of claim 2 wherein the data storage unit is a flip-flop; one input end of the trigger is connected with the output end of the selection unit, and the other input end of the trigger is connected with a time sequence control signal.
11. The redundancy scheme of claim 10 wherein each of said flip-flops is connected to the same timing control signal.
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