JP5618792B2 - Error detection and repair device - Google Patents

Description

  The present invention relates to a circuit restoration device that autonomously restores a function when a function mounted inside a semiconductor integrated circuit fails.

  As miniaturization of semiconductor integrated circuits progresses, higher integration of reconfigurable semiconductor integrated circuits progresses, and semiconductor integrated circuits are being used in large-scale systems. However, with the miniaturization of semiconductor processes and the lowering of the power supply voltage, problems due to soft errors caused by cosmic rays, which have not been a problem until now, have become more prominent. In particular, in a system such as a social infrastructure, economic loss caused by a system failure due to a failure is large. For this reason, there is a demand for means for restoring a normal state without stopping the system even when a failure occurs.

  Furthermore, in a system that requires high reliability, even when a permanent failure such as a failure of a transistor inside the chip or a disconnection of wiring occurs, robustness is required to avoid the influence and continue operation. Yes.

  A transient failure due to a soft error can be repaired by a multiplexing system such as TMR (Triple Module Redundancy) or a method such as error correction using a redundant code. On the other hand, when a permanent failure occurs in the constituent circuits, the function of detecting a transient failure is impaired and the reliability is lowered. For example, in the case of TMR, if a permanent failure occurs in one system of a three-layer module, the output of the permanent failure module becomes abnormal. If a soft error occurs in the other two normal systems, the output of the majority circuit The result is abnormal.

  For example, in the computer system described in Patent Document 1, an abnormality (failure) is detected by a majority circuit, and the number of abnormality detections is counted by an abnormality number counter. When the count value exceeds a predetermined threshold value, it is determined that the failure that has occurred is a permanent failure, and otherwise, it is determined that it is a transient failure.

JP 2004-13396 A

  However, the above-described conventional technique has a problem in that it cannot perform an accurate abnormality determination because the abnormality determination of whether the generated failure is a permanent failure or a transient failure is performed based on the number of abnormality detections. It was. Further, when it is determined that a permanent failure has occurred, the internal bus and control signal of the CPU module are merely disconnected, and there is a problem that a highly reliable operation cannot be ensured.

  The present invention has been made in view of the above, and an object of the present invention is to obtain an error detection and repair device capable of maintaining high system reliability over a long period of time.

In order to solve the above-described problems and achieve the object, the present invention provides a logic circuit including a plurality of error-correctable logic blocks, an error detection unit for detecting an error occurring in the logic block, and the error When a hard error is detected from the errors detected by the detection unit, a hard error detection unit that outputs at least one hard error information, and the number of hardware error information output from the hard error detection unit are counted, Based on the counting result, it is determined whether or not the logical block has a permanent failure. When the logical block has a permanent failure, a switching instruction to switch the logical block determined to be a permanent failure to a normal logical block is issued. An error counter to be transmitted, and a logic block determined to be a permanent failure when the switching instruction is transmitted from the error counter. The click, anda reconfiguration control unit to switch to normal logic blocks, determines that the hard error detection unit, the hard error occurs when an error is detected in predetermined cycles continuously from the error detection unit Then, at least one of the hard error information is output .

  According to the present invention, it is possible to maintain the high reliability of the system over a long period of time.

FIG. 1 is a diagram illustrating the configuration of the error detection and repair apparatus according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of functional blocks according to the first embodiment. FIG. 3 is a diagram illustrating a configuration example of the hard error detection circuit according to the first embodiment. FIG. 4 is a diagram illustrating another configuration example of the hard error detection circuit according to the first embodiment. FIG. 5 is a diagram for explaining a first example of a permanent failure determination method. FIG. 6 is a diagram for explaining a second example of the permanent failure determination method. FIG. 7 is a diagram for explaining a third example of the permanent failure determination method. FIG. 8 is a diagram illustrating the configuration of the error detection and repair apparatus according to the third embodiment. FIG. 9 is a diagram illustrating a configuration of functional blocks according to the third embodiment. FIG. 10 is a diagram illustrating a configuration example of a hard error detection circuit according to the third embodiment. FIG. 11 is a flowchart showing an operation procedure of the test circuit according to the third embodiment.

  Hereinafter, an error detection and repair apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. Note that the present invention is not limited to the embodiments. Further, in the drawing used for description of the embodiment, the wiring information to the clock terminal of the flip-flop is omitted.

Embodiment 1 FIG.
FIG. 1 is a diagram illustrating the configuration of the error detection and repair apparatus according to the first embodiment. The error detection / repair device 100 is a device that detects a hard error by a soft error (transient failure) / hard error (permanent failure) discrimination function when any one of error-correctable logic blocks fails. . The error detection / repair device 100 disconnects a system in which a hard error has occurred from other systems, and restores (reconfigures) the function in which the hard error has occurred with a normal system spare circuit.

  The error detection / repair device 100 includes a reconfiguration control unit 6, a hard error detection circuit (hard error detection unit) 4, an error counter (error counting unit) 5, and a plurality of functional blocks. . Here, a case where the error detection / repair device 100 includes three functional blocks 1A to 1C will be described.

  Each of the functional blocks 1A to 1C includes a correctable logic block 11 (a set of elements having a mechanism capable of error correction) and an error detection circuit 15 to be described later. The functional blocks 1A to 1C are connected to signal input lines 0A to 0C, normal signal lines 2A to 2C used in normal operation, and error notification signal lines 3A to 3C, respectively.

  The hard error detection circuit 4 is connected to the error notification signal lines 3A to 3C. The hard error detection circuit 4 and the error counter 5 are connected by a hard error notification signal line 7. Further, the error counter 5 and the reconstruction control unit 6 are connected by a reconstruction instruction signal line 9. Further, the reconfiguration control unit 6 and the previous circuit (not shown) are connected by the previous signal line 10.

  The reconfiguration controller 6 inputs various input information (input signals) sent from the previous circuit via the previous signal line 10 to the function blocks 1A to 1C and controls the reconfiguration of the function blocks 1A to 1C. To do.

  The pre-stage signal line 10 is a signal line for sending various input information sent from the pre-stage circuit to the reconstruction control unit 6. The signal input lines 0A to 0C are signal lines that send input signals sent from the reconfiguration control unit 6 to the function blocks 1A to 1C. Further, the normal signal lines 2A to 2C send signals (normal signals) used in normal operation sent from the functional blocks 1A to 1C to other functional blocks (not shown) and logic elements (not shown). It is a signal line. The error notification signal lines 3A to 3C are signal lines that send error information (error determination information) 3a to 3c (not shown) sent from the functional blocks 1A to 1C to the hard error detection circuit 4.

  The normal signal sent to the normal signal lines 2A to 2C is used for normal system operation in other functional blocks and logic elements. The error detection circuit 15 included in the functional blocks 1A to 1C detects an error that has occurred in an error correctable logic block (hereinafter referred to as a correctable logic block 11) existing in the logic circuit, and error information 3a to 3c is notified to the hardware error detection circuit 4 via the error notification signal lines 3A to 3C.

  When the error information 3a to 3c is notified to any of the error notification signal lines 3A to 3C, the hardware error detection circuit 4 determines whether the error information 3a to 3c is a soft error or a hard error based on the error information 3a to 3c. Analyze the cause (failure type). The hardware error detection circuit 4 notifies the hardware error information X indicating the hardware error from the hardware error notification signal line 7 to the error counter 5 only when the error information 3a to 3c is a hardware error (permanent failure).

  When the hardware error information X is issued from the hardware error detection circuit 4 to the hardware error notification signal line 7, the error counter 5 counts the number of times the hardware error information X is issued. The error counter 5 determines whether to reconfigure the functional blocks 1A to 1C based on the parameter input information sent via the parameter input line 8 and the count value (counting result) of the error counter 5 itself. To do.

  When the reconfiguration requirements are satisfied, the error counter 5 updates the reconfiguration information and issues a reconfiguration instruction (transmission of reconfiguration information) to the reconfiguration control unit 6. The reconfiguration information includes a switching instruction for switching a logical block determined to be a permanent failure to a normal logical block. For example, when the number of hard errors (hardware error information X) reaches a predetermined number, the error counter 5 gives a reconfiguration instruction to the reconfiguration control unit 6.

  Upon receiving the reconfiguration instruction, the reconfiguration control unit 6 updates the connection relation between the previous stage input information and the output (signal input lines 0A to 0C) and the internal states of the functional blocks 1A to 1C based on the reconfiguration information. In other words, the reconfiguration control unit 6 distributes various input information sent from the preceding circuit to the signal input lines 0A to 0C based on the reconfiguration information sent from the error counter 5.

  As a result, the reconfiguration control unit 6 sets the failed correctable logical block 11 to be unusable based on the reconfiguration information, and switches to a normal block (system). In other words, when the number of hard errors reaches a predetermined number, the error location is disconnected from the normal system, and the function equivalent to the error location is restored.

  For example, an operation system and a standby system are constructed using an FPGA (Field-Programmable Gate Array) which is a kind of PLD (Programmable Logic Device). When a permanent failure occurs in any one of the functional blocks 1A to 1C, the reconfiguration control unit 6 switches the functional block in which the permanent failure has occurred to the standby system, so that the functional block in which the permanent failure has occurred. Perform reconfiguration. The reconfiguration of the functional blocks 1A to 1C may be performed by any method, and is not limited to the above method.

  As described above, the error detection and repair device 100 manages the number of occurrences of hard errors, and reconfigures the functional blocks 1A to 1C based on the number of occurrences of hard errors. The error detection / restoration apparatus 100 autonomously restores the function without stopping the operation of the system when the function mounted in the semiconductor integrated circuit has a permanent failure.

  Next, the configuration of the functional blocks 1A to 1C will be described. Since the functional blocks 1A to 1C have the same configuration, the configuration of the functional block 1A will be described here.

  FIG. 2 is a diagram illustrating a configuration of functional blocks according to the first embodiment. FIG. 2 shows the internal configuration of the functional block 1A. The functional block 1A includes a correctable logic block 11 and an error detection circuit (error detection unit) 15.

  Here, as an example of the correctable logic block 11, a case where the correctable logic block 11 operates using a flip-flop having a TMR (Triple Module Redundancy) configuration will be described.

  The correctable logic block 11 has three systems of flip-flops 12A to 12C and a majority circuit 14. Input signals from the signal input line 0A are input to the flip-flops 12A to 12C. The flip-flops 12A to 12C are connected to the individual output signal lines 13A to 13C, respectively. The individual output signal lines 13A to 13C connect the flip-flops 12A to 12C and the error detection circuit 15, and also connect the flip-flops 12A to 12C and the majority circuit 14.

  The error detection circuit 15 is connected to the individual output signal lines 13A to 13C as an input side signal line, and is connected to the error notification signal line 3A as an output side signal line. The majority circuit 14 is connected to the individual output signal lines 13A to 13C as input-side signal lines, and is connected to the normal signal line 2A as output-side signal lines.

  When a failure occurs in any of the flip-flops 12A to 12C and the output value is inverted, the other two normal flip-flop outputs are selected by majority in the majority circuit 14, and the normal signal line 2A (major circuit output) Is output. The output signal output to the normal signal line 2A is used in normal operation.

  The error detection circuit 15 performs error detection based on outputs from the flip-flops 12A to 12C in the correctable logic block 11 (individual signals sent to the individual output signal lines 13A to 13C). The error detection circuit 15 receives the individual signals sent to the individual output signal lines 13A to 13C, and notifies the error information 3a from the error notification signal line 3A when all of the individual signals do not match.

  In addition, although the case where the structure of the functional block 1A has the flip-flop of TMR structure was demonstrated here, the structure of the functional block 1A is not restricted to this structure. For example, the functional block 1A may be one having a flip-flop that performs error correction by an ECC circuit to which a redundant code is assigned, or one that performs error correction by a more sophisticated block including peripheral logic circuits and memories. In these cases, an error is notified when error correction is performed based on the error correction method.

  FIG. 3 is a diagram illustrating a configuration example of the hard error detection circuit according to the first embodiment. A failure caused by a soft error is updated to a correct value in the next operation cycle by an error correction function or an input value (input information) from a preceding circuit. For this reason, in this embodiment, a hard error is determined when an error is detected for two consecutive cycles.

  The hard error detection circuit 4 includes an OR circuit 21, flip-flops 22 and 23, and an AND circuit 24. The OR circuit 21 is connected to the error notification signal lines 3A to 3C, and receives error information 3a to 3c from the error notification signal lines 3A to 3C. The OR circuit 21 is connected to the signal line 25, and outputs a logical sum of the error information 3 a to 3 c to the signal line 25.

  The flip-flop 22 is connected to the signal line 25, and a signal (logical sum of the error information 3 a to 3 c) from the OR circuit 21 is input from the signal line 25 to the flip-flop 22. The flip-flop 22 is connected to the signal line 26 and outputs a signal obtained by delaying the signal from the signal line 25 to the signal line 26.

  The AND circuit 24 is connected to the signal line 25 and receives a signal (logical sum of the error information 3a to 3c) from the signal line 25. The AND circuit 24 is connected to the signal line 26 and receives a signal from the signal line 26. The AND circuit 24 calculates the logical product of the signal from the signal line 25 and the signal from the signal line 26, and detects an error in two consecutive cycles when an error occurs in two consecutive cycles. The AND circuit 24 is connected to the flip-flop 23 via the signal line 27. The AND circuit 24 outputs an output signal to the signal line 27 when detecting an error for two consecutive cycles. The flip-flop 23 delays / waveforms the output signal from the AND circuit 24 and outputs the delayed / waveform-shaped signal to the hard error notification signal line 7 as hard error information X.

  With this configuration, in the hard error detection circuit 4, when the error information 3a to 3c is input via any of the error notification signal lines 3A to 3C, the AND circuit 24 calculates the logical sum of the error information 3a to 3c. . This logical sum information is output from the AND circuit 24 to the signal line 25 and sent to the flip-flop 22 and the AND circuit 24.

  The flip-flop 22 delays the signal from the signal line 25 (logical sum of the error information 3 a to 3 c), and outputs the delayed signal to the signal line 26. The AND circuit 24 calculates the logical product of the signal from the signal line 25 and the signal from the signal line 26. As a result, when an error occurs in two consecutive cycles, the AND circuit 24 detects an error in two consecutive cycles. In the case of a soft error, the error is not notified to the AND circuit 24 for two consecutive cycles. In this case, the error information 3a to 3c is canceled by the AND circuit 24. The flip-flop 23 delays / shapes the output signal from the AND circuit 24 and outputs it as the hard error information X to the hard error notification signal line 7.

  FIG. 4 is a diagram illustrating another configuration example of the hard error detection circuit according to the first embodiment. 4 that have the same functions as those of the hard error detection circuit 4 shown in FIG. 3 are denoted by the same reference numerals, and redundant description thereof is omitted.

  The hard error detection circuit 4 shown in FIG. 3 is configured to determine whether or not a hard error has occurred with respect to the logical sum of the error information 3a to 3c. On the other hand, the hard error detection circuit 4 ′ shown in FIG. 4 determines whether or not there is a hard error for each of the error information 3a to 3c, and then performs a logical sum (logical sum of error determination). It is a configuration.

  The hard error detection circuit 4 ′ includes an OR circuit 21 and a hard error detection circuit for each functional block. The hard error detection circuit 4 'here includes hard error detection units 31A to 31C for the functional blocks 1A to 1C.

  The hard error detection unit 31A is connected to the error notification signal line 3A as an input-side signal line, and is connected to the signal line 32A as an output-side signal line. The hard error detection unit 31B is connected to the error notification signal line 3B as an input-side signal line, and is connected to the signal line 32B as an output-side signal line. The hard error detection unit 31C is connected to the error notification signal line 3C as an input-side signal line, and is connected to the signal line 32C as an output-side signal line. The OR circuit 21 is connected to the signal lines 32A to 32C as input-side signal lines, and is connected to the hard error notification signal line 7 as output-side signal lines.

  The hard error detection units 31A to 31C delete the OR circuit 21 from the configuration of the hard error detection circuit 4 shown in FIG. 3, respectively, and the signal line 25 is directly used as one of the error notification signal lines 3A to 3B. It is a connected configuration.

  Since the hard error detection units 31A to 31C have the same configuration, the configuration of the hard error detection unit 31A will be described here. The hard error detector 31A includes flip-flops 22A and 23A and an AND circuit 24A. The flip-flops 22A and 23A have the same function as the flip-flops 22 and 23, and the AND circuit 24A has the same function as the AND circuit 24. The signal lines 25A to 27A have the same function as the signal lines 25 to 27.

  The error notification signal line 3A is connected to the signal line 25A in the hard error detection unit 31A. The flip-flop 22A is connected to the signal line 25A, and the error information 3a is input from the signal line 25A to the flip-flop 22A. The flip-flop 22A is connected to the signal line 26A, and outputs a signal obtained by delaying the signal from the signal line 25A to the signal line 26A.

  The AND circuit 24A is connected to the signal line 25A and the signal line 26A, and receives a signal from the signal line 25A and a signal from the signal line 26A. The AND circuit 24A calculates the logical product of the signal from the signal line 25A and the signal from the signal line 26A, and detects an error in two consecutive cycles when an error occurs in two consecutive cycles. The AND circuit 24A is connected to the flip-flop 23A via the signal line 27A. The AND circuit 24A outputs an output signal to the signal line 27A when detecting an error for two consecutive cycles. The flip-flop 23A delays / waveforms the output signal from the AND circuit 24A, and sends the delayed / waveform-shaped signal to the signal line 32A as error information 3a.

  With this configuration, when the error information 3a is input to the hardware error detection circuit 4 'via the error notification signal line 3A, the error information 3a is sent to the flip-flop 22A and the AND circuit 24A via the signal line 25A.

  The flip-flop 22A delays the signal from the signal line 25A and outputs the delayed signal to the signal line 26A. The AND circuit 24A calculates a logical product of the signal from the signal line 25A and the signal from the signal line 26A. The AND circuit 24A outputs an output signal to the signal line 27A when detecting an error for two consecutive cycles. The flip-flop 23A delays / shapes the output signal from the AND circuit 24A and outputs it as error information 3a to the signal line 32A. The error information 3a is input to the OR circuit 21.

  Similarly, when the error information 3b is input to the hard error detection unit 31B via the error notification signal line 3B, when the hard error detection unit 31B detects an error for two consecutive cycles, the hard error detection unit Error information 3b is input to the OR circuit 21 from 31B.

  Similarly, when the error information 3c is input to the hard error detection unit 31C via the error notification signal line 3C, when the hard error detection unit 31C detects an error for two consecutive cycles, the hard error detection unit Error information 3c is input to the OR circuit 21 from 31C.

  The OR circuit 21 outputs the logical sum of the signals (error information 3a to 3c) from the hardware error detection units 31A to 31C to the hardware error notification signal line 7 as the hardware error information X.

  As described above, in the hard error detection circuit 4 ′, the outputs of the hard error detection units 31A to 31C corresponding to the error information 3a to 3c are input to the OR circuit 21, and the logical sum output is output as the hard error information X. To do.

  With the configuration of the hard error detection circuit 4 shown in FIG. 3, it is possible to perform hard error determination with a simple configuration. Further, with the configuration of the hard error detection circuit 4 ′ shown in FIG. 4, even if a soft error occurs in different functional blocks in a continuous operation cycle, a logical sum output (hard error notification) from the OR circuit 21 The signal line 7) does not report an error for two consecutive cycles. For this reason, erroneous hardware error determination can be prevented. Therefore, the reliability of hard error determination can be improved.

  In the configuration of the hard error detection circuit 4 ′ shown in FIG. 4, the flip-flop 23A is deleted, and the output of the OR circuit 21 is delayed / shaped by the flip-flop. The error information X may be output.

  Further, in the hard error detection circuit 4 and the hard error detection circuit 4 ′, the flip-flop itself used in the hard error detection circuit is configured to be capable of error correction such as TMR, thereby further improving the reliability of hard error determination. Is possible. When the hardware error information X is output from the hardware error detection circuit 4 or the hardware error detection circuit 4 ′, the hardware error information X is sent to the error counter 5.

  As described above, the error detection / repair device 100 discriminates between a transient failure due to a soft error and a permanent failure due to a hardware error, and among the types of errors (soft errors / hard errors) occurring in the functional block, Only errors are targeted for error. When the hard error reaches a predetermined number, the reconfiguration control unit 6 switches the functional block in which the hard error has occurred to a normal block, so that the system in which the permanent failure has occurred can be restored. In addition, it is possible to prevent a loss of circuit resources caused by disconnecting a soft error circuit, which is a transient failure, from the system.

  In addition, since only a permanent failure is disconnected from a normal system and autonomously restored to the state before the permanent failure, it is possible to maintain high reliability of each function in the system for a long period of time. As a result, it is possible to provide a logic circuit suitable for a device that requires continuous operation for a long period of time and is difficult to perform repair work such as an artificial satellite or a control device of a nuclear power plant.

  In the present embodiment, the case where the functional blocks are the three functional blocks 1A to 1C has been described. However, the number of functional blocks may be two, or may be four or more. In this embodiment, a hard error is determined when an error is detected for two consecutive cycles. However, a hard error may be determined when an error is detected for a predetermined cycle of three or more cycles.

  As described above, according to the first embodiment, a transient failure and a permanent failure are discriminated, and the function is restored in the case of the permanent failure, so that the high reliability of the system is maintained for a long period of time. It becomes possible.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, the error counter 5 determines whether a permanent failure (hard error) has occurred according to various conditions.

  FIG. 5 is a diagram for explaining a first example of a permanent failure determination method. FIG. 6 is a diagram for explaining a second example of the permanent failure determination method. FIG. 7 is a diagram for explaining a third example of the permanent failure determination method.

  5 to 7 show a count example of the number of hard errors by the error counter 5 and a permanent failure determination example. 5 to 7, the horizontal axis represents time, and the vertical axis represents the number of hard errors (count value by the error counter 5).

  For example, the graph of FIG. 5 is a graph in the case where the error counter 5 monotonically increases (adds) the hard error count every time the hardware error information X is notified. When the hardware error information X is notified to the error counter 5, the error counter 5 adds a predetermined number to the count value and holds it until the next hardware error notification. The error counter 5 compares the count value with the threshold value 41. When the count value exceeds the threshold value 41, the error counter 5 updates the reconfiguration information and instructs the reconfiguration control unit 6 to perform a reconfiguration.

  The graph of FIG. 6 shows the case where the error counter 5 decreases the count value (error value) when the hardware error information X is not received for a predetermined time (during a predetermined period) (when no error is detected). It is a graph of. In this case, the error counter 5 has a function of reducing the count value when the hardware error information X is not received for a predetermined time. For example, if the error counter 5 does not receive the hardware error information X during the time range 42, the error counter 5 subtracts a predetermined subtraction value 43 from the count value.

  The graph of FIG. 7 is a graph when the count value is cleared to zero when the error counter 5 does not receive the hardware error information X within a predetermined time (time range 44). In this case, the error counter 5 has a function of clearing the count value to zero when the hard error information X is not received within a predetermined time.

  The threshold value 41, the time ranges 42 and 44, and the subtraction value 43 are set based on parameter input information sent via the parameter input line 8, and are external to the apparatus (for example, an external control computer). Or change from the inside.

  If the error counter 5 is configured so that the count value of the error counter 5 does not become less than 0 (does not underflow), the subtraction value is 0 in the case of FIG. 5 and the subtraction value is the threshold value 41 in FIG. It is possible to freely use the functions of FIG. 5 to FIG. The time ranges 42 and 44 are measured by a timer (not shown) separate from the error counter 5, for example.

  Thus, in this embodiment, a threshold value is set for the count value, and a reconfiguration instruction is issued to the reconfiguration control unit 6 when the threshold value is exceeded. In addition, a timer for measuring a predetermined period is provided, and the number of errors is subtracted when no error is detected within the predetermined period. In addition, by making the threshold value, the timer timing amount, and the subtraction value variable, it is possible to flexibly control whether or not the reconfiguration process is performed according to the number of occurrences and the frequency of errors.

  In other words, a reconfiguration instruction or a test start instruction is output only when the count value exceeds the threshold value, and subtraction is performed from the count value when a hard error is not notified for a predetermined time. The threshold value, the time range, and the subtraction value are variable from outside or inside the apparatus. Thereby, it is possible to flexibly perform error repair by reconfiguration according to the frequency of occurrence of hard errors and the degree of reliability required for the apparatus.

  As described above, according to the second embodiment, each time the hardware error information X is notified, the count number of the hardware error is monotonously increased. Therefore, whether or not a permanent failure has occurred by the error counter 5 having a simple configuration. It becomes possible to determine.

  In addition, when the hardware error information X is not received within a predetermined time, the count value is decreased, so that it is possible to accurately determine whether or not a permanent failure has occurred. Further, when the hardware error information X is not received within a predetermined time, the count value is cleared to zero, so that it is possible to accurately determine whether or not a permanent failure has occurred.

Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, a test circuit for specifying the correctable logic block 11 (functional blocks 1A to 1C) in which a permanent failure has occurred is provided. Then, before the functional blocks 1A to 1C are reconfigured, the correctable logic block 11 in which the permanent failure has occurred is specified by the test circuit. Thereafter, the specified correctable logical block 11 is reconfigured.

  FIG. 8 is a diagram illustrating the configuration of the error detection and repair apparatus according to the third embodiment. Of the constituent elements in FIG. 8, constituent elements that achieve the same functions as those of the error detection / repair device 100 shown in FIG. 1 of the first embodiment are given the same numbers, and redundant descriptions are omitted.

The error detection / repair device 101 is configured by making the following additions / changes to the error detection / repair device 100.
(1) A test circuit 52 is added, the output of the error counter 5 is used as a test start signal, and a test control signal is output from the test circuit 52.
(2) The reconfiguration information is output from the test circuit 52.
(3) A selector 59 is added. As a parameter input to the error counter 5, the selector 59 selects either normal parameter input information or test parameter input information. The parameter input information to be input to the error counter 5 during the test and the selection instruction (select input) to the selector 59 are performed by the test circuit 52.
(4) The functional blocks 1A to 1C are changed to functional blocks 50A to 50C. In the function blocks 50A to 50C, a selector for selecting either normal input or test data input is added.
(5) The hard error detection circuit 4 is changed to the hard error detection circuit 51. The hard error detection circuit 51 has a function of selecting and bypassing any of the error information 3a to 3c.

  Specifically, the functional blocks 50A to 50C are connected to the test control signal line 56 in addition to the signal input lines 0A to 0C, the normal signal lines 2A to 2C, and the error notification signal lines 3A to 3C. The hard error detection circuit 51 is connected to the test control signal line 56 in addition to the error notification signal lines 3A to 3C and the hard error notification signal line 7.

  The error counter 5 is connected to the test start instruction signal line 58 in addition to the hardware error notification signal line 7 and the parameter input line 8. The test circuit 52 is connected to the test start instruction signal line 58, the parameter input line 54, the select signal line 55, the test control signal line 56, and the reconfiguration instruction signal line 9. The selector 59 is connected to the parameter input line 54, the select signal line 55, the parameter input line 53, and the parameter input line 8.

  With this configuration, in the normal operation (hardware error detection process), the error detection / repair device 101 sends an instruction for selecting the signal input lines 0A to 0C to the function blocks 50A to 50C. An instruction to select the signal input lines 0A to 0C is sent to the functional blocks 50A to 50C as a control signal for normal operation via the test control signal line 56. Thereby, the functional blocks 50A to 50C perform the same operation as in the first embodiment.

  Further, during normal operation, the test circuit 52 sends an instruction to the hard error detection circuit 51 to select the hard error detection circuit 4. An instruction to select the hard error detection circuit 4 is sent to the hard error detection circuit 51 through the test control signal line 56 as a control signal for normal operation. Thereby, the hard error detection circuit 51 performs the same operation as that of the hard error detection circuit 4 of the first embodiment.

  Further, during normal operation, the test circuit 52 sends an instruction to select the parameter input line 53 to the selector 59 via the select signal line 55. Thus, the selector 59 selects the normal parameter input information sent from the parameter input line 53 and sends it to the error counter 5.

  The error counter 5 determines whether to reconfigure the functional blocks 50A to 50C based on the parameter input information and the count value of the hardware error information X. When reconfiguring the functional blocks 50A to 50C, the error counter 5 sends information (test start signal) indicating reconfiguration to the test circuit 52.

  As a result, the error detection / repair device 101 starts a test operation for specifying the functional blocks 50A to 50C in which the permanent failure has occurred. In the test operation, the test circuit 52 sends a test control signal to any one of the functional blocks 50A to 50C and the hard error detection circuit 51 via the test control signal line 56.

  The test control signals sent to the functional blocks 50A to 50C include test data, an instruction for selecting the test data, and an instruction for specifying any of the functional blocks 50A to 50C (an instruction for specifying a functional block to be tested). ,It is included. Thereby, any one of the functional blocks 50A to 50C performs a test operation using the test data.

  The test control signal for starting the test sent to the hard error detection circuit 51 includes an instruction to select the error information 3a to 3c. Thereby, the hard error detection circuit 51 performs a test operation using the error information 3a to 3c corresponding to the test data.

  In the test operation, the test circuit 52 sends parameter input information at the time of testing to the selector 59 via the parameter input line 54. Further, the test circuit 52 sends an instruction to select the parameter input line 54 to the selector 59 via the select signal line 55. Accordingly, the selector 59 selects parameter input information at the time of testing sent from the parameter input line 54 and sends the selected parameter input information to the error counter 5 via the parameter input line 8.

  During the test operation, the error counter 5 indicates that any of the functional blocks 50A to 50C has a permanent failure based on the parameter input information sent via the parameter input line 8 and the count value by the error counter 5. It is determined whether or not the function block has occurred.

  When the error counter 5 identifies the functional block in which the permanent failure has occurred, the error counter 5 sends information identifying the functional block to the test circuit 52. As a result, the test circuit 52 sends a reconfiguration instruction to the reconfiguration control unit 6 so as to reconfigure the functional block in which the permanent failure has occurred. Based on the reconfiguration information, the reconfiguration control unit 6 disables the correctable logical block 11 in which the permanent failure has occurred and switches it to a normal block (system).

  Next, the configuration of the functional blocks 50A to 50C will be described. Since the functional blocks 50A to 50C have the same configuration, the configuration of the functional block 50A will be described here.

  FIG. 9 is a diagram illustrating a configuration of functional blocks according to the third embodiment. FIG. 9 shows the internal configuration of the functional block 50A. In addition, the same number is attached | subjected about the component which achieves the same function as the functional block 1A shown in FIG. 2 of Embodiment 1 among each component of FIG. 8, and the overlapping description is abbreviate | omitted.

  The functional block 50A includes a correctable logic block 11, an error detection circuit 15, and a selector 61. That is, the functional block 50A has a configuration in which a selector 61 is added to the functional block 1A.

  The selector 61 is a signal input line 0A, a test data input line 62 that is a test data input line, a select signal input line 63 that is a select signal input line, and a signal that is a signal line to the correctable logic block 11. Is connected to the line 64. The test data input line 62 and the select signal input line 63 are connected to the test control signal line 56.

  An input signal sent from the reconfiguration control unit 6 is input to the selector 61 via the signal input line 0A. Further, the test data in the test control signal sent from the test circuit 52 is input to the selector 61 via the test control signal line 56 and the test data input line 62. The input signal from the reconfiguration controller 6 and the test data from the test circuit 52 are selected input data for the selector 61. Further, the selector 61 receives a select signal in the test control signal sent from the test circuit 52 via the test control signal line 56 and the select signal input line 63.

  In normal operation or when testing the functional blocks 50B and 50C, an instruction to select the signal input line 0A is input from the select signal input line 63 to the selector 61. Accordingly, the selector 61 selects an input signal from the signal input line 0A and sends it out to the signal line 64. Then, the correctable logic block 11 and the error detection circuit 15 perform the same operation as in the first embodiment.

  In the test operation, an instruction to select the functional block 50A and an instruction to select the test data input line 62 are input from the select signal input line 63 to the selector 61. As a result, the selector 61 selects the test data from the test data input line 62 and sends it to the signal line 64. Then, the correctable logic block 11 and the error detection circuit 15 perform a test operation using the test data.

  As described above, when testing the functional block 50A, test data is input to the correctable logic block 11 of the functional block 50A, and during normal operation or when testing the functional blocks 50B and 50C, the signal input line 0A. Are input to the correctable logic block 11.

  As a result, during the test operation, test data is selected in the functional block to be tested, and test data is not selected in functional blocks other than the test target. Thereby, it becomes possible to test the operation of the functional block to be tested. In the present embodiment, for example, the function blocks 50A to 50C are set as test targets in order, and the function blocks 50A to 50C are tested in order.

  FIG. 10 is a diagram illustrating a configuration example of a hard error detection circuit according to the third embodiment. The hard error detection circuit 51 includes a hard error detection circuit 4 and a selector 71. The hard error detection circuit 4 has an input side connected to the error notification signal lines 3 </ b> A to 3 </ b> C and an output side connected to the signal line 72.

  The selector 71 is connected to the error notification signal lines 3 </ b> A to 3 </ b> C, the signal line 72, and the select signal line 73 connected to the test control signal line 56 on the input side, and connected to the hard error notification signal line 7 on the output side. ing.

  Error information 3a to 3c sent from the function blocks 50A to 50C is input to the selector 71 via error notification signal lines 3A to 3C, respectively. In addition, the hardware error information X sent from the hardware error detection circuit 4 is input to the selector 71 via the signal line 72. The error information 3 a to 3 c and the hard error information X are selected input data for the selector 71. Further, an error information selection signal in the test control signal sent from the test circuit 52 is input to the selector 71 via the test control signal line 56 and the select signal line 73.

  In the normal operation, an instruction to select the signal line 72 is input to the selector 71 via the select signal line 73. As a result, the selector 71 selects the hard error information X from the signal line 72 and sends it to the hard error notification signal line 7. The error counter 5 performs the same operation as in the first embodiment.

  In the test operation, an instruction for selecting any one or a plurality of error notification signal lines 3A to 3C (error information 3a to 3c) to be tested is input from the select signal line 73 to the selector 71. As a result, the selector 71 selects the error information to be tested from the error information 3 a to 3 c and sends it to the hard error notification signal line 7. In this way, during the test operation, error information sent from the functional block to be tested is selected and sent to the hard error notification signal line 7, and errors sent from functional blocks other than the test target are sent. Information is not sent to the hardware error notification signal line 7.

  The error counter 5 counts error information. The error counter 5 compares the threshold value set based on the parameter input information at the time of the test with the count value of the error information. Then, the error counter 5 determines that the functional block to be tested is a permanent failure when the count value is larger than the threshold value.

  FIG. 11 is a flowchart showing an operation procedure of the test circuit according to the third embodiment. In the error detection / repair device 101, when the error counter 5 detects the occurrence of a permanent failure, a test start instruction is sent from the error counter 5 via the test start instruction signal line 58. Thereby, the test circuit 52 receives the test start instruction, and the test by the test circuit 52 is started.

  The test circuit 52 sets the parameter of the error counter 5 to a test parameter (parameter input information at the time of test) (step S81). Specifically, a threshold value 41, time ranges 42 and 44, a subtraction value 43, and the like defined for the test parameter are sent from the test circuit 52 to the selector 53 via the parameter input line 54.

  Further, the test circuit 52 sends an instruction (select signal) for selecting the parameter input line 54 to the selector 59 via the select signal line 55. In other words, the test circuit 52 controls the select signal so that the selector 59 selects the test parameter from the parameter input line 54. As a result, the selector 59 selects the parameter input information for the test sent from the parameter input line 54 and sends it to the error counter 5.

  Subsequently, the test circuit 52 executes tests on the functional blocks 50A to 50C. The test circuit 52 selects one functional block to be tested (hereinafter referred to as a target functional block) from the functional blocks 50A to 50C (step S82). The test circuit 52 includes an instruction (select signal) for selecting the target function block (error information) in the test control signal, and sends the instruction block to the function blocks 50A to 50C and the hardware error detection circuit 51. Specifically, a select signal designating the target function block is sent to the selectors 61 of the function blocks 50A to 50C via the test control signal line 56 and the select signal input line 63. A select signal designating the target functional block is sent to the selector 71 via the test control signal line 56 and the select signal input line 73. As a result, the target functional block is set to the test mode. Further, the hard error detection circuit 51 is set to bypass the output of the target functional block (step S83).

  Then, the test circuit 52 applies test data (hard error detection pattern) to the target functional block (step S84). Examples of the test data include a pattern in which 0/1 for stuck-at fault detection is alternately applied in time series.

  The function blocks 50 </ b> A to 50 </ b> C select the test data from the test data input line 62 by the selector 61 if their function block is designated as the target function block in the select signal.

  As a result, a test using the test data is performed in the target functional block. Specifically, test processing using test data is performed in the flip-flops 12A to 12C, and test results are transmitted from the flip-flops 12A to 12C.

  The error detection circuit 15 detects an error that has occurred in the correctable logic block 11 based on the test result, and notifies the hardware error detection circuit 51 of the error information 3a to 3c.

  The hard error detection circuit 51 selects error information corresponding to the target functional block and outputs the error information to the hard error notification signal line 7 as the hard error information X. Specifically, the selector 71 selects error information (error notification signal line) corresponding to the target functional block from the error information 3a to 3c (error notification signal lines 3A to 3C), and the hardware error information X is hardware. The error notification signal line 7 is output.

  After completing the application of the test data to the target function block, the test circuit 52 inputs an instruction to set the target function block to the normal operation (normal mode) to the target function block and the hardware error detection circuit 51. As a result, the target functional block is returned to the normal operation, and the setting of the hard error detection circuit 51 is returned to the original state (normal operation state) (step S85). Specifically, the selector 61 of the target functional block selects a signal input line connected to the reconfiguration control unit 6 and sends an input signal from this signal input line to the correctable logic block 11. The selector 71 selects the hard error information X from the signal line 72 and sends it to the hard error notification signal line 7.

  When an error occurs in the target functional block during the test operation, the hardware error information X is input from the hardware error detection circuit 51 to the error counter 5. Thus, since the error information (error notification signal) from the target functional block is directly input to the error counter 5 as the hard error information X, the error counter 5 counts the hard error information X. If the error counter 5 determines that the target functional block is a permanent failure based on the hardware error information X, an error notification is sent to the test circuit 52.

  At this time, the test result is output from the error counter 5. When the count value by the error counter 5 exceeds a predetermined threshold value, the error counter 5 issues an error notification. When an error notification is issued from the error counter 5 (step S86, Yes), the test circuit 52 issues a reconfiguration instruction from the reconfiguration instruction signal line 9.

  Thereby, the reconfiguration control unit 6 determines that the target functional block is a permanent failure and separates it, and switches the target functional block to a spare normal block (step S87). On the other hand, when error notification is not performed from the error counter 5 (step S86, No), the test circuit 52 performs the following process without issuing a reconfiguration instruction.

  Thereafter, the test circuit 52 determines whether or not all the tests (tests for all the functional blocks 50A to 50C) have been completed (step S88). If the 100% test has not been completed (No at Step S88), the process returns to Step S82, and the processes at Steps S82 to S88 are repeated for the unprocessed function block.

  On the other hand, when the exhaustive test is completed (step S88, Yes), the test circuit 52 restores the parameter of the error counter 5 to the parameter for normal operation. Specifically, the test circuit 52 sends an instruction (select signal) for selecting the parameter input line 53 to the selector 59 via the select signal line 55. In other words, the test circuit 52 controls the select signal so that the selector 59 selects the normal operation parameter from the parameter input line 53. Accordingly, the selector 59 selects the parameter input information for normal operation sent from the parameter input line 53 and sends it to the error counter 5 via the parameter input line 8. Then, the error counter 5 restores the parameters for normal operation and completes the test operation (step S89).

  Further, the test circuit 52 sends an instruction to select the signal input lines 0A to 0C to the functional blocks 50A to 50C. In addition, the test circuit 52 sends an instruction for selecting the hardware error detection circuit 4 to the hardware error detection circuit 51. As a result, the error detection / repair device 101 returns to the normal operation. Thereby, the functional blocks 50A to 50C can be reconfigured after accurately diagnosing the failure state of the circuit to be reconfigured. Therefore, it is possible to correctly disconnect only the system in which a true hard error has occurred.

  Thereafter, when the test circuit 52 receives a test start instruction from the error counter 5, the processes of steps S81 to S89 are performed again. The reconfiguration instruction to the reconfiguration controller 6 may be sent from the error counter 5.

  As described above, according to the third embodiment, the test circuit 52 is provided in the error detection / restoration apparatus 101, so that the target functional block can be tested in detail. As a result, it is possible to perform the reconfiguration after accurately diagnosing the failure state of the circuit to be reconfigured, and it is possible to correctly disconnect only the system in which the true hard error has occurred.

  As described above, the error detection / restoration apparatus according to the present invention is suitable for restoring a function when the function mounted inside the semiconductor integrated circuit has a permanent failure.

1A to 1C, 50A to 50C Functional block 4, 51 Hard error detection circuit 5 Error counter 6 Reconfiguration control unit 11 Correctable logic block 14 Majority circuit 15 Error detection circuit 31A to 31C Hard error detection unit 41 Threshold value 42, 44 Time range 43 Subtraction value 52 Test circuit 100, 101 Error detection and repair device

Claims (5)

A logic circuit including a plurality of error-correctable logic blocks;
An error detection unit for detecting an error occurring in the logical block;
A hard error detection unit that outputs at least one hard error information when a hard error is detected from the errors detected by the error detection unit;
When the number of pieces of hardware error information output from the hardware error detection unit is counted, it is determined whether or not the logical block is a permanent failure based on the counting result, and when the logical block is a permanent failure An error counting unit for sending a switching instruction to switch a logical block determined to be a permanent failure to a normal logical block;
A reconfiguration control unit that switches a logical block determined to be a permanent failure to a normal logical block when the switching instruction is sent from the error counting unit;
Equipped with,
The hard error detection unit determines that the hard error has occurred when an error is detected continuously from the error detection unit for a predetermined cycle, and outputs at least one of the hard error information. apparatus. The error detection and repair device according to claim 1 , wherein the error counting unit determines that the logical block is a permanent failure when the counting result exceeds a predetermined threshold value. 3. The error counting unit according to claim 2 , wherein the hard error information is subtracted when the hard error information is not output for a predetermined period from the hard error detection unit. Error detection and repair device. 4. The error detection and repair device according to claim 3 , wherein the error counting unit variably sets at least one of a subtraction value when subtracting the hard error information, the threshold value, and the predetermined period . A test circuit for identifying a logic block in which a permanent failure has occurred from among the plurality of logic blocks by inputting a test signal to the plurality of logic blocks;
The reconfiguration control unit, error detection repairing apparatus according to the logical block in which the test circuit is identified, in any one of claims 1 4, characterized in that to switch to normal logic blocks.

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