JPH08110865A - Self-diagnostic test method for signal processing board - Google Patents

Abstract

PURPOSE: To speedily and easily specify a fault position of a signal processing board by comparing an input test pattern with an output response pattern by a CPU and diagnosing defective places of plural logic circuits. CONSTITUTION: Only the selector 442n provided at the input stage of an expander 440n is set on a CPU bus side and selectors provided at the input stages of remaining logic circuits are all set on normal data transmission line sides. And, the test pattern for a coupling test is generates in a RAM 406 or read directly from a ROM 404 and inputted to the expander 440n through a signal line TSn. The output is written in an FIFO 440a. Test patterns are read out from the FIFO 440a in order by an MPU 403 and compared with the normal processing test pattern stored in the ROM 404, etc., to check whether or not the coupling processing and timing between logic circuits are normal. The test is repeated as many times as specified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a self-diagnosis test method for a signal processing board, and more particularly to a printing device such as a printing plate making apparatus, an image exposure section, an image recording section or an image of an image processing apparatus such as a copying machine and a printer. The present invention relates to a self-diagnosis test method for a signal processing board that is effective when automatically inspecting an image processing board or the like used in an input unit or the like.

[0002]

2. Description of the Related Art Conventionally, in an image processing apparatus such as an electronically editable printing plate making system or a copying machine, an image reading apparatus for reading an original image original placed on an original table and converting it into digital data, or an image processing apparatus for image processing. A large number of image recording devices are used to print digital information by exposing it on a photosensitive material. In such an image processing apparatus, various kinds of control circuits, logic circuits and memories are used in order to digitally process a large amount of pixel data. And these control circuits,
The logic circuit and the memory include a hybrid IC, a CPU, a PLD (PAL), an LCA, a gate array, a standard cell, an embedded array, and an R on a plurality of electronic circuit boards.
By mounting semiconductor elements such as AM and ROM, various image processing functions are realized with a small number of substrates.

[0003]

However, conventionally, when a failure occurs in these image processing apparatuses, a service person brings all the related signal processing boards, replaces the boards one by one, and replaces the failed boards. After identifying it, he brought it back to the factory and repaired it. However, when the signal processing function becomes complicated,
However, no matter how many hardware inspection means are prepared, it is impossible to identify the faulty part of the board in a short time and it is impossible to repair it.

Although many functional tests are performed on individual elements such as the gate array at the manufacturing stage, it is time-consuming to perform the same functional test at the manufacturing stage again after mounting on the signal processing board. And it is difficult in terms of circuit.

The present invention has been made under the circumstances as described above, and an object of the present invention is to add a simple test signal switching circuit to each logic circuit on a signal processing board for image processing and the like. It is an object of the present invention to provide a self-diagnosis test method for a signal processing board, which can input a variety of test signals and quickly and easily identify a failure location on the board.

[0006]

SUMMARY OF THE INVENTION The present invention relates to a self-diagnosis test method for a signal processing board.
A plurality of logic circuits each connected to the CPU via the PU interface and arranged in a predetermined layout pattern, wirings connecting these logic circuits in a predetermined wiring pattern, and logic at the final stage of the plurality of logic circuits. In a signal processing board having a shared memory connected to the output wiring of the circuit, when executing a self-diagnosis test of the signal processing board, the CPU interface responds to a select signal output during the self-diagnosis test mode. Then the CP
A selector is provided for selecting each test data composed of a predetermined test pattern generated by U and inputting it to the logic circuit respectively, and inputting the input test pattern sequentially from the CPU to each of the plurality of logic circuits and outputting it. This is achieved by sequentially storing the response patterns in the shared memory, respectively, and then comparing the input test pattern with the output response pattern by the CPU to diagnose each defective portion of the plurality of logic circuits.

[0007]

In the signal processing board self-diagnosis test method of the present invention, a simple test signal switching circuit is provided for each logic circuit of the board, and various test signals are input from the switching circuit to perform self-diagnosis of the logic circuit. Since the diagnosis result is stored in the shared memory to identify the failure location, the diagnostic circuit can be simplified and shared. Further, a self-diagnosis is sequentially performed from the logic circuit at the output stage of the board toward the logic circuit at the input stage, whereby a high-speed and diagnostic-free test can be performed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing system which is a premise of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of the overall configuration of an image processing system. A plurality of editing workstations 10 are provided.
Are connected to each other via Ethernet, and one of the workstations 10 is connected to a galley printer 20 which performs galley printing with a relatively low image quality. A workstation 30 for a server having a data server and a recorder server function is further connected to the Ethernet, and a mount input device 40 for reading and inputting a layout mount for printing is attached to the server workstation 30. A plurality of color scanners 50, 50 that are connected via the input controller 40A and that read and input a color image or a monochrome image of patterns, characters, figures, etc. by color separation are input via the plurality of input controllers 50A, 50A. It is connected. Further, the server workstation 30 has an output synchronization buffer 70 having functions of decompression, halftone shading, merging (line drawing and continuous tone (monotone) image), and buffering for synchronization.
A film printer 60 for outputting a high quality image is connected via the.

FIG. 1 shows an example in which a plurality of editing workstations 10 and one server workstation 30 are systematically combined. As shown in FIG. 2, one editing / server workstation 30A is used. It is also possible to have a stand-alone configuration with. In addition, other information (for example, LAN (Lo
(Cal Area Network) information, information from other computer systems, etc.) and processes it. Although the output synchronization buffer 70 is inserted between the server workstation 30 and the film printer 60 in the configuration examples of FIGS. 1 and 2, it may be incorporated in the film printer 60. .

The editing workstation 10 and the server workstation 30 can take various forms depending on the system configuration, but here, for convenience, an example of the same hardware configuration will be described with its details shown in FIG. The workstation 30 (or 10) is a CPU 30 that controls the entire system.
1 and a hard disk 302 for storing necessary information, a CRT 303 as a display unit, a keyboard 304 and a mouse 305 as an input operation unit,
It has a digitizer 306, a pointing means such as a trackball and a joystick, and can be loaded with a floppy disk (FD) 307 as a storage means.

FIG. 4 is a block diagram showing the overall configuration of the system shown in FIG. 1. The mount information KS (1 bit) read by the mount input device 40 is sent to the workstation 30 via the input controller 40A. Has become
C of four colors read by a plurality of color scanners 50, 50
MYK (Cyan, Magenta, Yellow
w, Black) color information CL1, CL2 (= 3)
2 bits; or K monocolor information = 8 bits) is sent to the workstation 30 via the input controllers 50A, 50A. Input controller 40A (50A)
Is designed to simultaneously perform high-density data processing for high image quality processing and coarse-density data processing for display, etc. in parallel at the same time, achieving high speed as a whole and efficient data processing. Has been realized. Input controller 40A,
50A has the same configuration, and the thinning unit 401 repeatedly performs thinning in a feedback manner, for example, 1/2, 1 /
Input data KS (CL1, CL2) is thinned out at an integer ratio such as 3, ..., 1/6, ..., 1 / n, but thinning is naturally performed for high-density data required for high image quality output. Not done. Further, in the input controller 40A (50A), data compression is performed together with data thinning in the compression unit 402, and the thinned and compressed data is temporarily stored in a buffer (not shown).

Data (1 bit (line drawing information), 8 bits (mono color), 32 bits (full color)) temporarily stored in the input controller 40A (50A) is input to the server workstation 30 as input information INS. External information EXS from another personal computer or the like connected to the external system is also input to the server workstation 30. The server workstation 30 includes a scan server 320 for converting the format of each input information and registering an image, and further includes a recorder server 310 for managing an output job. Allocation information from the recorder server 310 is provided. (Characters, figures, tables, etc.
Information for specifying the layout and size of photographs, etc.) PSD
Is input to the raster image processing unit (PSRIP) 312. Further, the server workstation 30 is provided with a data disk 311 for storing image data, and the image data IGS read from the data disk 311 is stored in the image replacement unit (Open PrePress Int).
erface) 313. Image replacement unit 3
The image data IGSA replaced in 13 is input to the raster image processing unit 312, and the raster image processing unit 3
The image is converted into a raster image at 12, and the pattern or the like in the image data is converted into a halftone dot. If necessary, the data-compressed raster data RD is input to the output synchronization buffer 70. The output synchronization buffer 70 synchronizes the data output with the printing speed of the film printer 60, performs necessary expansion on the data-compressed data, and further performs merging and halftone dot transmission to the film printer 60. To do.

FIG. 5 shows the detailed software configuration of the server workstation 30, and the input information INS.
The external information EXS is input to the format conversion unit 321 in the scan server 320, the format-converted data is used to create an image for display (display image) by the display image creation unit 322, and an image for icon (icon image). ) Is also created, and the image registration unit 324 performs image registration processing. Registration data SS of the display image and the icon image output from the scan server 320
Although D is input to the database manager 330 and data is stored therein, the image data IG is stored in the data disk 311.
Is input to the allocation data (PostScript D
ata) PS is input to the recorder server 310 that manages output jobs. Database manager 330
Includes a large attachment module 340 for imposing each page, an image processing module 350 for performing line drawing preprocessing (noise removal, rotation, etc.), retouching and clipping processing of a continuous tone image, a mount layout, A plate collection module 36 for collecting image data such as image layout, figure generation, and shading
0, a data management module 370 that performs output job management and data management, and an operation data control module 380 that performs color editing, hatching editing, ground stop registration, and the like are connected by software.

Here, the processing operation of the database manager 330 will be described with reference to the flowchart of FIG. 6. When the registration data SSD such as the mount and the part image transmitted from the scan server 320 is input (step S1). Image data IG is stored in the data disk 311 via the database manager 330 (step S2). At the time of data correction, the database manager 330 reads out the image data from the data disk 311, and the image processing module 350 performs retouching (correction work for the purpose of correcting color, gradation, scratches, etc.), dust removal, cutout, etc. Manager 330
The data is stored in the data disk 311 via (step S3). Next, the database manager 330 performs plate-collection processing (arranges a mount, arranges each part along the mount, and performs character processing to synthesize parts such as characters, figures, and images according to the designated layout). However, the database manager 330 first reads the image data IG from the data disk 311, performs the plate collection operation by the plate collection module 360, and then stores the processed data in the data disk 311 via the database manager 330. Store. And further data disk 3
Image data IG is read out from 11, and large paste module 3
40, the imposition instruction and work are performed, the imposition data is stored in the data disk 311 via the database manager 330, and the imposition is performed (step S
5) Next, the data is extracted from the data disk 311 to the database manager 330, and the recorder server 310
The output process is performed in step S6.

FIG. 7 shows the target of input data (binary data,
The relation between layout information, bitmap data, continuous tone image) and process (input, plate collection / editing, output) is shown as data and flow of functions that the operator is aware of. The data is read by the mount input device 40 or the color scanner 50 to remove dust, retouch, rotate,
Enlargement / reduction processing is performed to obtain image editing data, and P
The ostScript information is RIP (Raster Im
image processor; data expressed in a page description language such as PostScript is developed and converted into bitmap data or the like) to be image editing data. Also, the bitmap data is format-converted by a filter to become image editing data, and the continuous tone image is read by the color scanner 50 or directly input to be retouched, cut out, and subjected to image processing to become image editing data. . The keyword, the image name, and the job name as the data management information are also captured in the image editing data. Image editing data is processed such as mount processing (closed area automatic recognition), drawing, object editing, composition, transformation, rotation, shading / attribute change, layout, photo embedding, etc., history image display change, distributed editing , Data saving is executed. After each of the above processes, color separation, spot color plate, and trapping are performed, and then imposition is performed page by page, and plate collection / editing is completed. The "special color plate" is a plate for printing with an ink other than ordinary CMYK, and for example, (1) black and gold red "gold red" in two-color printing, (2) gold, silver, (3) When expressing the color of a woman's lipstick in a photograph in a colorful way, use it as a separate plate for the lipstick, adding it to normal CMYK, and stacking ink on it. In addition, "trapping" is, specifically, when arranging with the hair removed,
It means overlapping little by little to prevent blank areas due to misalignment of printing. The data collected / edited by the server workstation 30 is used for galley output by the galley printer 20, and PDL (Page Description).
Language; for example, PostScript) output, or film output by the film printer 60.

FIG. 8 corresponding to FIG. 5 shows a database network relationship among the database manager 330, the recorder server 310, the non-document processing modules 600a to 600m, and the document processing modules 500a to 500n. The numbered devices perform the same function, and the recorder server 310
The PSRIP 312 is built into the inside of the recorder, and the recorder server 310 performs network communication with the database network via the database communication unit 550. Then, in the recorder server 310, the output data transferred from the network is sent to the spooler 7
After being temporarily stored in the file 20, the rearrangement processing unit 730 reconfigures the print arrangement to the file and the like.
The RIP 312 expands the actual print image data and stores it in the OPI disk 313 as an output spool. Thus, when the print image data is ready,
The print image data is output to the output process synchronization buffers 701 to 70k via the print control units 740a to 740k, and the print image is output to the galley printer 20 and the film printer 60. Each process from the process of receiving output data from the network to the process of outputting print image data to the output process synchronization buffer is sequentially executed under the control of the job management unit 710. There is.

Further, the database network includes one or more document processing modules 500a to 500n.
As shown in FIG. 9, an operation input processing unit 510 that processes a mouse operation and a key input, and a document management unit that controls communication with a database network are connected to each document processing module. 540, a data processing unit 520 that performs actual data processing, and a display processing unit 5 that displays the processed results on the display devices 700a to 700n.
And 30 are provided. Then, the data processing unit 52
In 0, a processing history management unit 650 that records / reproduces a history of data processing, a closed region recognition processing unit 640, a CT image boundary extraction unit 660, a PDL generation unit 670, and an edit target are managed as tree type data. A path management unit 620 and an image cache management unit 630 that processes continuous tone image data.
Is provided with an object management unit 610 and the like, and these data processing unit components have a software configuration that can be used alone or in appropriate combination. Incidentally, as a typical example of the document processing module, there is a plate collection module 360 shown in FIG.

Further, the database network has 1
Individual or multiple non-document processing modules 600a-60
As many as 0 m can be connected, as shown in FIG. 10, each non-document processing module has an operation input processing unit 510 for processing mouse operations and key inputs, and a database for controlling communication with a database network. Communication unit 5
50, and a data processing unit 520 that performs actual data processing
And a display processing unit 530 for displaying the processed result on the display device 700 or the like. Then, the data processing unit 520 records a process history management unit 650 that records and reproduces a history of data processing, a closed region recognition processing unit 640, a CT image boundary extraction unit 660, a PDL generation unit 670, and an edit target as a tree. A path management unit 620 that manages as type data and an image cache management unit 6 that processes continuous tone image data
An object management unit 610 composed of 30 and the like are provided, and these data processing unit components have a software configuration that can be used alone or in combination of a plurality of units as appropriate. Note that the non-document processing modules include the large attachment module 340, the image processing module 350, and the cutout module shown in FIG.

The document processing modules 500a to 500n and the non-document processing modules 600a to 600 described above are used.
The difference from m is that communication with the database network is performed via the document management unit 540 or the database communication unit 55.
0 through 0, and the database communication unit 55
When connected to the network via 0, only normal connection processing can be executed, but when connected to the network via the document management unit 540, distributed editing processing can be executed, which is the main difference.

With such a configuration, the self-diagnosis test method for the image processing signal board of the present invention will be described in more detail. First, FIG. 11 corresponding to FIG. 8 is a more detailed illustration of the components related to the signal processing board of the present invention extracted from the electronic editing system. The mount input device 40 includes a line sensor 42 and an AD. A conversion unit 44, a sensitivity correction unit 46 of the line sensor 42, and a magnetic disk,
The color scanner 50 is composed of an original image storage means 48 composed of an optical disk, and the color scanner 50 outputs the output lights of the R, G, and B optical filters 52, 54, 56, respectively.
Like 0, it is stored in the storage means 48 via the line sensor 42, the AD conversion means 44, and the sensitivity correction means 46. Then, these outputs are the image input device 4
The signal KS is input to 0A or 50A and is connected to one port of the input switching means 414. The output is also input to the selector 442C provided in the input means of the thinning circuit 440C together with the self-diagnosis test signal TS3 from the CPU bus, and the thinning circuit 4
The output of 40C is the selector 4 provided in the input means of the compressor 440b together with the test signal TS2 from the CPU bus.
42b, the output of the compressor 440b is input together with the test signal TS1 to the selector 442a provided at the input stage of the FIFO 440a, and its output is output via a bus switching means 416 to a magnetic disk, an optical disk, a flash memory, or the like. DMA in the constructed mass storage means 412
The data is written under the control of the C (DMA controller) 410. Further, the contents of the storage means 412 are read by the dual port memory 408 or the decompressor 440n under the control of the DMAC 410, and the decompressor 440 is read.
A test signal TSn is also input to n, and its output is connected to the other input end of the input switching means 414. In addition, dual port memory 408,
The image bus IBUS to which the DMAC 410 and the storage means 412 are connected is also connected to the scan server 320 shown in FIG. 8, and a hierarchical image data generation command from the scan server 320 is written in the dual port memory 408 via the image bus IBUS. At the same time, the generated layered image data is read from the storage means 412, and the image bus IB is read.
The data is output to the scan server 320 via the US. The CPU bus to which the microprocessor (hereinafter abbreviated as MPU) 403, the ROM 404, the RAM 406, the dual port memory 408, and the like are connected, controls the above-described operation, and the image input device 40A or 5
A self-diagnosis test of 0A is also executed.

In this configuration, the self-diagnosis test operation of the signal processing board will be described in more detail. First, the operator operates the scan server 320 shown in FIG. 8, and the main display shown in FIG. When the menu D2 is displayed and the "option" menu is selected by operating the mouse, the display screen changes as shown in FIG. 13 and a list of "option" menus appears. Therefore, when the self-diagnosis command D148 is selected from this menu, the self-diagnosis dialog D200 appears on the screen, and the self-diagnosis item setting work is performed. In this work, the test target is specified. For example, when all the constituent elements of the board are to be checked, the test execution ON button D202 is activated from the self-diagnosis dialog D200 and is provided in the lower part of the dialog. It is advisable to press the executed button D290. When individual components such as a memory, a FIFO, and a compressor are specified and self-diagnosis is performed, the test ON buttons D206, D210, ... D222 are activated and the execute button D290 is pressed. Further, when a combination test is performed by combining logic circuits or a heat run test is performed, the test ON button D226 or D230 is activated and the execute button D290 is pressed.

Thus, when the test object is specified and the execution button D290 is pressed, a self-diagnosis execution message is output from the scan server 320 to the image processing board 40A or 50A, and the self-diagnosis test of the signal processing board is started.

Next, the self-diagnosis operation in the all test execution mode will be described in detail. In this case, the all test execution ON button D202 described above is selected, and the execution button D2
When 90 is pressed, these pieces of information are processed inside the scan server 320, and the bit "1" indicating all tests is set in the test target items in the self-diagnosis control information 2000 as shown in FIG. , Self-diagnosis control information 2
000 as a self-diagnosis message via the image bus, the dual port memory 4 provided in the signal processing board.
It is written in 08 together with the self-diagnosis command as shown in FIG.

Then, on the side of the signal processing board 40A or 50A, the self-diagnosis execution command is written.
U403 reads the self-diagnosis control information 2000 from the dual port memory 408, and as shown in FIG.
It is copied to the RAM 406 connected to the PU bus. Next, the MPU 403 decodes the self-diagnosis control information 2000, and first, the ROM 404 coupled to the CPU bus.
If the checksum test is executed and the diagnostic result is normal, a PASS message is displayed. If an error is detected, E is displayed.
The RROR message together with the test object name is written in the dual port memory 408 and transferred to the scan server 320 via the image bus as shown in FIG. 15, and the message D80 of FIG. 20 is displayed on the display device of the scan server 320.
Displayed as 0.

Subsequently, the write / read test of the RAM 406 is executed by the MPU 403. RAM406
In the writing / reading test, if the data already written is not desired to be destroyed, only the data of the test address is read and saved in another address before the test, and the MPU4
Write the test pattern to the test address with 03,
After that, the write data is read from the same address and the MPU
After the write data and the read data are compared by 403 for error check, the saved data may be returned. The write test pattern is 0000.
H (H represents hexadecimal number), FFFFH, AAAA
Bit patterns such as H and 5555H are generally used. Thus, when the RAM 406 test is completed,
The result is written in the dual port memory 408 and, as shown in FIG. 15, the scan server 32 via the image bus.
2 is displayed on the display device of the scan server 320.
A message D802 of 0 is displayed. RA
The error message of the M test generally has a format such as "RAM test error address ABCD write data AAAA read data A8AA".

Next, the write / read test of the dual port memory 408 is executed by the MPU 403. This test has almost the same test contents as the RAM test described above, but the interrupt memory address with the scan server 320 is not a test target. Then, when the test of the dual port memory 408 is completed, the result is written in the dual port memory 408 and transferred to the scan server 320 via the image bus as shown in FIG.
A message D804 of FIG. 20 is displayed on the display device of the scan server 320. Thus, the ROM, RAM, and dual port memory test shown in step S10 of the flowchart of FIG. 17 is completed.

Next, the mass storage means 412 and the DMAC
The simplified test of 410 is executed (step S of FIG. 17).
20). This test is a simple test because the storage capacity of the storage means 412 is a large capacity of usually 100 MB (megabytes) or more, so if the entire storage area of the storage means 412 is checked, it takes a huge amount of time (usually 30 minutes or more). For this reason, a small capacity of 4 to 16 MB is checked for the time being, and a strict test is performed when there is enough time or when it is suspected that an error has occurred in the storage means 412. Now, in the test of the storage means 412,
It is desirable to perform a non-destructive test of the storage means 412 similarly to the RAM test. First, the storage means 4 is first stored in the DMAC 410.
The leading read address and read data length of the 12 test areas are set, and then the read destination address of these data to the dual port memory 408 is set. And
When the MPU 403 outputs a transfer start command for the DMAC 410, the MPU 403 stores the write test pattern of the storage means 412 in another area of the dual port memory 408 with the above-mentioned read data length until reading of these test areas is completed. It is generated with the same length and then enters the wait state. Thus, when the save data is read from the storage means 412, the MPU 403 sets the start address of the write test pattern of the dual port memory 408 in the DMAC 410 as the read start address, and the transfer data length is set to the same data length as described above. At the same time, the start address of the test area of the storage means 412 is set as the write start address of the DMAC 410, and then the DMAC 410
Transfer start command is output, and the dual port memory 40
The test pattern preset to 8 is stored in the storage means 41.
Written in 2. After that, the test pattern written from the storage unit 412 is read to another storage area of the dual port memory 408 in the same manner as the above-mentioned save data reading operation, and further written by the MPU 403 in the dual port memory 408. The built-in test pattern and the read test pattern are compared to check whether or not an error has occurred in the read or write operation of the storage means 412. The test result of the storage means 412 is written in the dual port memory 408 in a format such as "storage means transfer error transfer address XXXX write data YYYY read data ZZZZ" and transferred to the scan server 320 via the image bus. At the same time, if there is no error, the above-mentioned read data that has been saved is written back from the dual port memory 408 to the storage means 412.
The functional test of the DMAC 410 is checked by performing the same data transfer from a predetermined address of the dual port memory 408 to another address of the dual port memory 408 and comparing the transfer results with the MPU 403. Therefore, after the memory test of the dual port memory 408 is completed, it is desirable to first perform the transfer function check of the DMAC 410 using only the dual port memory 408, and then perform the write / read test of the storage means 412 (see FIG. 17). Step S20). In the self-diagnosis test of the memory, DMAC, and storage means 412 described above, since test data is input / output, it is not necessary to switch the input test pattern, and all tests can be executed through the normal data transfer path.

Next, the FIFO 44 which is a buffer memory
Execute the unit functional test of 0a. Since the test data is input and output in the subsequent tests, it is necessary to set the path through which the self-diagnosis test signal flows in advance before the test. Therefore, first, the setting operation of the test signal transmission path when testing the FIFO 440a will be described. As shown in FIG. 18A, the MPU 403 switches the selector 442a provided at the input stage of the FIFO 440a to the CPU bus side. Bus switching means 416 also CP
Switch to U-bus side, MPU403 to FIFO440a
Is set so that it can read and write directly. Then, MPU4
03 function check, usually FIFO440
Since the capacity of a is about 1MB to 16MB, the FIF
The O test pattern is read from the test data set in the ROM 404 or the RAM 406 and written up to the FIFO capacity in the FIFO 440a through the sequential signal line TS1. However, if the read operation is not executed during the writing only by writing the data to the FIFO 440a, the near full signal and the buffer full signal are written to the MPU 403 after the writing is performed a predetermined number of times. Confirm that these signals are output reliably, as they will be output. Subsequently, when only the read operation by the MPU 403 is executed from the FIFO 440a and the read result is continuously stored in another storage area of the RAM 406,
When a predetermined number of times is read, near empty (nea
r empty signal and buffer empty (buf)
Since it is planned to output the "ferempty" signals to the MPU 403, it is confirmed again that these signals are surely output. Finally, write test data and RAM4
The read test data stored in 06 is compared by the MPU 403 to check whether a write or read error has occurred in the FIFO 440a. After the test is completed, the test result of the FIFO 440a is written in the dual port memory 408 and transferred to the scan server 320 via the image bus (step S in FIG. 17).
30), the message is displayed on the display device of the scan server 320 as the message D810 in FIG.

Subsequently, a unit function test of the compressor 440b is executed. In this test, first, as shown in FIG. 18B, the MPU 403 switches the selector 442b provided in the preceding stage of the compressor 440b to the CPU bus side and the selector 442a of the FIFO 440a to the compressor 440b side. In both cases, the FIFO 440a is set to the through mode (mode in which the input signal is directly connected to the output signal as it is), and the bus switching means 416 is set to the CPU bus side as described above. When the test signal transmission path is thus set, the MPU 403 then sets the compression mode of the compressor 440b. This compression mode includes run length code mode, Huffman code mode,
There are arithmetic code mode, Lempel-Ziv mode, and the like. When the above setting is completed, the compressor 4 is stored in the RAM 406.
40b test pattern data is generated or RO
The test pattern for the compressor 440b is read directly from M404 and input to the compressor 440b via the signal line TS2. The output is the FIFO 440a in the through state.
Also, it is read by the MPU 403 via the bus switching means 416 and stored in the RAM 406. Then, when a test pattern of a predetermined length is written in and read from the compressor 440b, the MPU 403 thereafter causes the compressor 440b to read.
Output data is read from the RAM 406, and the ROM 40
It is checked whether or not the compression operation in the designated compression mode is normally performed by comparing with the normal compression pattern stored in the memory 4 or the like. After the test, the compressor 4
The compression mode of 40b is switched to another compression mode,
The self-diagnosis similar to the above is repeated again. Thus,
When the function check for all compression modes is completed,
The test result of the compressor 440b is the dual port memory 4
08, the scan server 32 via the image bus
0 (step S40 in FIG. 17) and displayed on the display device of the scan server 320 as the message D812 in FIG.

Next, the unit function test of the thinning circuit 440c is executed in the same manner as described above, and then, in the circuit configuration example of FIG. 11, the unit function test of the decompressor 440n is finally executed. In this test, first, as shown in FIG. 18C, the MPU 403 switches the selector 442n provided in the preceding stage of the decompressor 440n to the CPU bus side, and the input switching means 414 is switched to the decompressor 440n side. The input stage selector 442c of the thinning circuit 440c is set to the input switching means 414 side, and the input stage selector 442b of the compressor 440b is set to the thinning circuit 440c side.
The input stage selector 442a of the FIFO 440a is the compressor 4
40b side, and the bus switching means 416 is set to CP.
While being switched to the U-bus side, the insides of the thinning circuit 440c, the compressor 440b and the FIFO 440a are set to the through mode. Thus, when the test signal path is set, the MPU 403 then sets the expansion mode of the expander 440n. This expansion mode is applied to the compressor 440b.
The operation corresponding to the compressed mode is performed, and the compressed data corresponding to the run mode of the compression mode, the Huffman code mode, the arithmetic code mode, the Lempel-Ziv mode, etc. is converted into the original data. It is supposed to be restored.

When the above setting is completed, the test pattern for the decompressor 440n is generated in the RAM 406 or the test pattern for the decompressor 440n is directly read from the ROM 404 and input to the decompressor 440a via the signal line TSn. It The output is the thinning circuit 44 in the through state.
0c, M through the compressor 440b and the FIFO 440a
It is read by the PU 403 and stored in the RAM 406.
Then, the test pattern having a predetermined length is expanded by the expander 440.
When the data is written in n and read, the restored data of the decompressor 440n is read out from the RAM 406 by the MPU 403 and compared with the normal decompression pattern stored in the ROM 404 or the like, and the decompression operation in the specified decompression mode is normal. It is checked whether or not it has been executed. After the end of the test, the expansion mode of the expander 440n is switched to another expansion mode, and the self-diagnosis similar to the above is repeated again. Thus, when the single function check for all the decompression modes is completed, the test result of the decompressor 440n is written in the dual port memory 408 and transferred to the scan server 320 via the image bus (step S in FIG. 17).
60), the message is displayed on the display device of the scan server 320 as message D816 in FIG. In the circuit configuration of FIG. 11, the selector 442n provided at the input stage of the decompressor 440n can be omitted. In this case, the test data of the decompressor 440n is written once in the dual port memory 408 by the MPU 403. , Then DMA
It is preferable to activate C410 and supply the test data from the dual port memory 408 to the decompressor 440n. However, in general, the test signal selector provided in the input stage cannot be omitted.

When the unit function test of each logic circuit block on the signal processing board is completed, the logic circuit connection test is started. In this logic circuit connection test,
In the case of the circuit configuration of No. 1, first, the compressor 440b and the FIFO
A connection test with 440a is executed. Similar to the above, prior to the coupling test, the transmission path of the test signal is first set. This setting operation will be described with reference to the block diagram of FIG. 19A. The selector 442b is set to the CPU bus side TS2, the selector 442a provided in the input stage of the FIFO 440a is set to the compressor 440b side, and the bus switching means 416 is switched to the CPU bus side. Thus, when the test signal transmission path is set, next, the MPU 40
3 sets the compression mode of the compressor 440b in the same manner as described above. When the above settings are completed, RAM40
6, a test pattern for the compressor 440b is generated,
Alternatively, the test pattern for the compressor 440b is directly read from the ROM 404, and the compressor 440b is read through the signal line TS2.
Is input to Moreover, the output is sequentially the FIFO 440a.
Written in. Since the data is compressed by the compressor 440b, the compressed data written in the FIFO 440a is usually smaller than the number of data supplied from the MPU 403. Thus, when the compression test pattern of a predetermined length is written in the compressor 440b, thereafter, the MPU
The data of the FIFO 440a is sequentially read by 403 and compared with a normal compression pattern stored in the ROM 404 or the like to check whether or not the compression operation in the designated compression mode is normal. After the completion of the test, the compression mode of the compressor 440b is switched to another compression mode, and the self-diagnosis similar to the above is repeated again. When the function check for the predetermined type of compression mode is completed, the compression test result of the compressor-FIFO is written in the dual port memory 408 and transferred to the scan server 320 via the image bus (step S70 in FIG. 17). 2) on the display device of the scan server 320.
0 message D818 is displayed.

Next, the thinning circuit 440c and the compressor 440b.
The connection test of the FIFO 440a and the FIFO 440a will be described. First, the transmission path of the test signal is set as shown in FIG. That is, the selector 442c provided in the input stage of the thinning circuit 440c is set to the CPU bus side TS3, the selector 442b provided in the input stage of the compressor 440b is set to the thinning circuit 440c side, and the FIFO 440a and The setting of the bus switching means 416 is the same as the setting of the above-mentioned coupling test. Thus, when the test signal transmission path is set, the MPU 403 then sets the thinning rate of the thinning circuit 440c to the first test thinning rate 1 and sets the compression mode of the compressor 440b to the normal compression mode. After that, the thinning circuit 44 is added to the RAM 406.
0c test pattern is generated or ROM 40
4, the test pattern for the thinning circuit 440c is directly read and input to the thinning circuit 440c via the signal line TS3. The output is sequentially compressed by the compressor 440b and then written in the FIFO 440a. When the writing operation of the quotation test pattern as described above is repeated a predetermined number of times and the writing operation of the quotation test pattern is completed, the MPU 4
The test data, which has been thinned and compressed from the FIFO 440a by 03, is sequentially read and compared with a normal thinning and compression pattern stored in the ROM 404 or the like to check whether or not the thinning operation at the designated thinning rate 1 is normal. It After the test of the thinning rate 1 is completed, the thinning circuit 44
Only the thinning rate of 0c was changed to the next thinning rate for test 2,
The self-diagnosis similar to the thinning-out rate 1 described above is repeated. When the function check for a predetermined type of thinning rate (usually 5 to 10 types) is completed, the thinning circuit-compressor-FIF.
The combined test result of O is written in the dual port memory 408 and transferred to the scan server 320 via the image bus (step S80 in FIG. 17), and the scan server 32.
No. 0 is displayed on the display device like message D830 in FIG.

Finally, in the circuit configuration example of FIG. 11, the decompressor 440n-thinning circuit 4400-compressor 440b-FIF.
The coupling test of O440a is executed. In this coupling test, as shown in FIG. 19C, only the selector 442n provided in the input stage of the decompressor 440n is set on the CPU bus side, and the selectors provided in the input stages of the remaining logic circuits are set. Are all set on the normal data transmission line side. Thus, when the test signal transmission path is set,
Next, the MPU 403 sets the thinning rate of the thinning circuit 440c to, for example, 3, sets the normal compression mode to the compressor 440b, and then sets the expansion mode corresponding to this compression mode to the expander 440n. It When the above setting is completed, this coupling test test pattern is generated in the RAM 406, or the above coupling test pattern is read directly from the ROM 404 and sequentially input to the decompressor 440n via the signal line TSn. The output is thinned out by the thinning circuit 440c, and the compressor 440b
After being compressed by, it is written in the FIFO 440a. When the write operation of the test pattern as described above is repeated a predetermined number of times and the write operation of the test pattern for coupling test of all the logic circuits is completed, the MPU 403 causes the FIFO 440a.
The combined test patterns are sequentially read from
It is compared with a normal processing test pattern stored in the OM 404 or the like, and it is checked whether the coupling processing between logic circuits and the timing are operating normally. This combination test is repeated a predetermined number of times for a predetermined thinning rate and compression-expansion mode, and the result is written to the dual port memory 408 and transferred to the scan server 320 via the image bus (FIG. 17). Step S90), the message D of FIG. 20 is displayed on the display device of the scan server 320.
822 is displayed. Thus, the combinational connection test of the logic circuit is completed.

In the above description, the output of the FIFO 440a is switched to the CPU bus side by the bus switching means 416 and written in the RAM 406, or the MPU 403 executes the FI.
Although the test circuit configuration is such that the output of the FO 440a is directly read, the output of the final-stage logic circuit (FIFO 440a in this case) should be read from the MPU 403 via the dual port memory 408 or the like as in the hardware configuration of FIG. If it is possible, the bus switching means 416 is unnecessary, and
When the output of the IFO 440a is constantly written to a predetermined storage area of the dual port memory 408 by the DMAC 410 or the like and the output result of the FIFO 440a is read from the specific storage area of the dual port memory 408, the test signal wiring and The switching means can be saved.

In the case of the hardware configuration shown in FIG. 11, the MPU 403 writes the same test pattern for the decompressor-thinning-out circuit-compressor-FIFO coupling test to the dual port memory 408, and controls the DMAC 410. After writing the test pattern for the coupling test in a predetermined storage area of the storage means 412 under
Under the control of 0, the above-mentioned test pattern for coupling test is read from the storage means 412 and supplied to the decompressor 440n, and the final result thereof is read out from the FIFO 440a, and the storage means 412 is controlled under the control of the DMAC 410. If the MPU 403 reads the final result from the storage means 412 into the dual port memory 408 and checks the final result under the control of the DMAC 410, the test signal transmission path is not used at all. The self-diagnostic test of can also be realized.

[0038]

As described above, according to the self-diagnosis test method for a signal processing board of the present invention, a selector for switching signals with the CPU bus is provided in the input means of each logic circuit, and a simple signal through is provided. MP just by adding a circuit
With U403, all the functions of each logic circuit can be independently checked, and a coupling test between a plurality of logic circuits can be easily realized, and a failure location can be quickly identified.

Immediately after the power is turned on, all the simplified component tests are executed each time, the results are written in the dual port memory 408, and transferred to the scan server 320 via the image bus. The reliability of can be improved.

[Brief description of drawings]

FIG. 1 is a system configuration diagram showing an example of a hardware configuration of an electronic editing system of the present invention.

FIG. 2 is a diagram showing an example of another system configuration of the electronic editing system of the present invention.

FIG. 3 is a block diagram of hardware of an editing workstation used in the present invention.

FIG. 4 is a block diagram showing an example of a software configuration of the electronic editing system of the present invention.

FIG. 5 is a block diagram showing an example of a server workstation of the electronic editing system of the present invention.

FIG. 6 is a flowchart showing the flow of the entire editing work of the electronic editing system of the present invention.

FIG. 7 is a diagram showing a relationship between data to be edited and software steps in the electronic editing system of the present invention.

FIG. 8 is a block diagram showing a configuration of database communication in the electronic editing system of the present invention.

FIG. 9 is a block diagram showing a configuration of a document processing module used in the present invention.

FIG. 10 is a block diagram showing a configuration of a non-document processing module used in the present invention.

FIG. 11 is an example of a hardware block diagram of a signal processing board according to the present invention.

FIG. 12 is an example of a main menu screen of the scan server.

FIG. 13 is an example of an option menu and a self-diagnosis dialog screen of the present invention.

FIG. 14 is a diagram showing a signal transmission path from a scan server to a signal processing board.

FIG. 15 is a diagram showing a signal transmission path from a signal processing board to a scan server.

FIG. 16 is a structural example of self-diagnosis control information according to the present invention.

FIG. 17 is an example of a flowchart of a self-diagnosis test of the present invention.

FIG. 18 is a configuration example of a signal path for a unit function test in the self-diagnosis test of the present invention.

FIG. 19 is a structural example of a signal circuit for combined function test of the present invention.

FIG. 20 is an example of a message display of the self-diagnosis result of the present invention.

[Explanation of symbols]

10, 30, 30A workstation 40 mount input device 50 color scanner 40A, 50A input controller 60 film printer 70, 70a, ... 70k output synchronization buffer 310 recorder server 311, 313 data disk 312 raster image processor (PSRIP) 320 Scan server 330 Database manager 403 MPU 406 RAM 408 Dual port memory 410 DMAC 412 Large capacity storage means 414, 416 Switching means 440a, 440b, 440c, ..., 440n Logic circuit 442a, 442b, ..., 442n Selector 500a, 500b ,. , 500n Document processing module 600a, 600b, ..., 600m Non-document processing module 700a, 700b, ..., 700n Display device 510, 510a, 510b, ..., 510n Operation input processing unit 520, 520a, 520b, .., 520n Data processing unit 530, 530a, 530b, .., 530n Display processing unit 540, 540a, 540b ,. Document management unit 550, 550a, 550b, ..., 550n Database communication unit 610 Object management unit 640 Closed region recognition processing unit 650 Processing history management unit 660 CT image boundary extraction unit 670 PDL generation unit 710 Job management unit 720 Spooler 730 Relocation Processing unit 740a, ..., 740k Printer control unit

Claims (4)

[Claims] 1. A plurality of logic circuits each connected to a CPU via a CPU interface and arranged in a predetermined layout pattern, wirings connecting these logic circuits in a predetermined wiring pattern, and the plurality of logic circuits. In a self-diagnosis test method for a signal processing board, comprising: a shared memory connected to an output wiring of a logic circuit at the final stage of
A selector is provided for selecting test data composed of a predetermined test pattern generated by the CPU in response to a select signal output from the interface during the self-diagnosis test mode and inputting the selected test data to the logic circuit. Patterns are sequentially input from the CPU to the plurality of logic circuits, output response patterns thereof are sequentially stored in the shared memory, and then the CPU compares the input test pattern and the output response pattern with each other. A method for self-diagnosing a signal processing board, characterized in that each defective portion of the logic circuit is diagnosed. 2. The self-diagnosis test method for a signal processing board according to claim 1, wherein each logic circuit of the signal processing board is sequentially self-diagnosed from the final stage logic circuit toward the input stage logic circuit. 3. The self-diagnosis test method for a signal processing board according to claim 1, wherein the logic circuit is composed of an LSI, a PAL, a standard cell, a hybrid IC, or a gate array. 4. The self-diagnosis test method for a signal processing board according to claim 1, wherein the signal processing board is an image signal processing board.