CN104778324A - Integrated circuit selective reinforcement method with aging delaying and soft error tolerance functions - Google Patents

Integrated circuit selective reinforcement method with aging delaying and soft error tolerance functions Download PDF

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Publication number
CN104778324A
CN104778324A CN201510181497.6A CN201510181497A CN104778324A CN 104778324 A CN104778324 A CN 104778324A CN 201510181497 A CN201510181497 A CN 201510181497A CN 104778324 A CN104778324 A CN 104778324A
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aging
error
latch
door
logic gate
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梁华国
闫爱斌
黄正峰
蒋翠云
易茂祥
许晓琳
方祥圣
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Hefei University of Technology
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Hefei University of Technology
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Abstract

The invention discloses an integrated circuit selective reinforcement method with aging delaying and soft error tolerance functions. According to the integrated circuit selective reinforcement method with the aging delaying and soft error tolerance functions, on the premise of not affecting the circuit performance, partial extra power consumption and area overhead are increased, less computer simulation operation time is increased in the circuit designing process, and a part of logic gates are replaced in the circuit, so that the aging of the circuit can be delayed when the circuit is idle and in a sleeping state, and soft errors, caused by SET transient fault pulses with certain widths, can be weakened even shielded when the circuit is at work. Meanwhile, a part of latches are replaced in the aging critical paths and time sequence critical paths of the circuit, so that the circuit can be immune to SEU which causes the soft errors in the working process; a part of latches are replaced in the non-critical paths, so that the circuit can weaken and even shield the SET transient pulses with certain widths in the working process, and is immune to the SEU, therefore the purpose of tolerating the soft errors is achieved.

Description

A kind of delaying aging also tolerates the integrated circuit selective reinforcement means of soft error
Technical field
The present invention relates to Integration ofTechnology circuit fault-tolerant design field, particularly relate to a kind of delaying aging and tolerate the integrated circuit selective reinforcement means of soft error.
Background technology
Aging of integrated circuit can be caused by several physical, wherein common aging inducement has: negative bias thermal instability NBTI, grid oxygen time breakdown (Time-Dependent Dielectric Breakdown, be called for short TDDB), hot carrier in jection (Hot Carrier Injection, be called for short HCI) and electromigration (Electromigration is called for short EM).There are some researches show, under nanometer technology, NBTI effect causes integrated circuit that aging principal element occurs.
NBTI effect is a kind of physical influence acting on PMOS transistor and cause its performance degradation, and the generating process of this effect follows diffusion-reaction model.When the grid of PMOS transistor is in negative bias state, namely when grid voltage is " 0 ", on transistor silicon oxide interface, silicon-hydrogen bond ruptures under the effect of high electric field, thus forms positively charged hole in channels, and now the state of PMOS transistor is called as the aging biased phase.Along with continuing to increase of PMOS transistor grid pressing times, more silicon-hydrogen bond ruptures, and forms hydrogen and discharges from interface oxide layer.Because the hole of positively charged continues to increase, cause that PMOS transistor channel conduction ability declines, transistor drive current constantly reduces and the continuing to increase of threshold voltage.
Under the effect of NBTI effect, when grid is in negative bias, although PMOS transistor can occur aging, but, when grid is in forward bias, when namely grid voltage is " 1 ", hydrogen atom in transistor can recombine with positively charged silicon ion, reduce the quantity in hole in raceway groove, thus realize the part self-recoverage of transistor ageing, now PMOS transistor is in aging convalescence.Therefore, the digital integrated circuit caused by NBTI effect is aging has the self-healing feature of part.
According to the feature of NBTI effect self, static NBTI effect and dynamic N BTI effect can be divided into.Under grid is in negative bias state all the time, it is aging that PMOS transistor can continue generation, now, is called static NBTI effect.When forward voltage and negative voltage alternately appear in grid, what PMOS transistor can replace is in aging biased phase and aging convalescence, now, is called dynamic N BTI effect.When being in static NBTI effect, transistor threshold voltage can continue to raise; And under dynamic N BTI effects, the threshold voltage of PMOS transistor can change in the mode raised and decline replaces, namely can constantly raise at aging biased phase threshold voltage, in aging convalescence, threshold voltage there will be the phenomenon of decline.
Along with the continuous lifting of technological level, metal-oxide-semiconductor grid oxide layer thickness constantly reduces, and NBTI effect becomes serious all the more.In recent years, constantly there is scholar's research and propose to delay NBTI and cause aging technology.The people such as Huazhong Yang propose door replacement technology in document Leakage Power and Circuit Aging Cooptimization by GateReplacement Techniques, can reach the object delaying aging of integrated circuit simultaneously and reduce leakage power; The people such as Kumar propose a kind of method of bit reversal in document Impact of NBTI on SRAM Read Stabilityand Design for Reliability, have effectively recovered the static noise margin of sram cell; In addition pin is also had to reorder the technology such as method, NBTI overall approach, input vector control.
On the other hand, along with constantly reducing of integrated circuit technology size, supply voltage constantly reduces, the node capacitor of circuit is caused constantly to reduce, thus make the logic state of circuit node overturn required for the quantity of electric charge (critical charge) also decrease, circuit is all the more easily subject to the impact of the particles such as heavy ion, α particle, neutron and proton in space radiation environment and produces soft error.
Particle entrance crystal pipe sensitizing range in space radiation environment will cause semiconductor material to ionize, and the incident track of particle produce deposit electric charge and is collected by sensitive nodes, cause single particle effect.When there is not electric field, the normal running of electron hole pair on circuit of ionization does not affect.But when there is electric field, the electron hole pair on particle trajectory will be collected by electrode, form momentary current.If this situation occurs in combinational circuit, larger momentary current will make the output voltage generation transient changing of logic gate, thus produces SET transient pulse; If this situation occurs in memory circuitry, Charger transfer a large amount of between transistor drain and substrate will make the normal logic state of storage unit change, and namely SEU occurs, and shows as data bit upset.
SET and SEU is the major reason causing integrated circuit generation single-particle to lose efficacy.The anti-single particle reinforcement technique of integrated circuit, has proposed comparatively multi-scheme both at home and abroad, and redundancy is most common way.Redundancy is mainly divided into spatial redundancy and time redundancy.For the SET that combinational logic produces, there are replicated gate method, Voltage Cortrol method, door adjusted size method, export clamping circuit method and select the schemes such as logic node method.For the anti-SEU reinforcement technique of timing unit, mainly design has the timing unit structure of anti-SEU, and traditional timing unit is replaced with the timing unit of anti-SEU.By constructing the timing unit structure of soft fault preventing, storage unit will to be reduced in circuit dramatically to the susceptibility of soft error.Existing radiation hardening structure is as TMR-latch, DICE-latch, HiPeR-latch, and all kinds of latch structures etc. that HeFei University of Technology proposes.
At aerospace field, integrated circuit works long hours the space radiation environment existed in a large number in high energy particle and cosmic rays, proposes severe challenge to the reliability of circuit.Meanwhile, what the lifting of technological level made NBTI effect cause agingly can not be ignored all the more.Therefore, with lower expense, selectivity that is anti-aging and soft fault preventing is carried out to integrated circuit and reinforces fault-tolerant design, have important practical significance and using value.Although a lot of scholar proposes delay that NBTI effect causes aging respectively, and the method for soft error that tolerance space radiation effect causes.But up to the present, also do not have scholar to propose a kind ofly to reach these two objects simultaneously and not affect the effective ways of circuit performance, and the method that the present invention proposes, SET and SEU can be suppressed simultaneously well, and can delay that NBTI effect causes aging.Because the method proposed can reduce the probability of circuit generation soft error effectively, thus improve the reliability of integrated circuit, therefore can be applied to aerospace field.
Summary of the invention
The object of the invention is exactly the defect in order to make up prior art, provides a kind of delaying aging and tolerates the integrated circuit selective reinforcement means of soft error.
The present invention is achieved by the following technical solutions:
Delaying aging also tolerates the integrated circuit selective reinforcement means of soft error, and utilize computing machine to carry out design of Simulation to reference circuit, concrete steps are as follows:
Step (1): test signal topological sequences when described reference circuit being tested to described computer input;
Step (2): calculate the integrated circuit soft error rate considering negative bias thermal instability NBTI effect, finds out the logic gate set { G that soft error occurs errorand there is the latch set { L of soft error error, and by the logic gate set { G of described generation soft error errorand the latch set { L of described generation soft error errorelement sort from high to low according to the size of soft error rate;
Step (3): access each the NAND Logic door in described reference circuit in aging critical path by described topological sequence, i.e. aging key logic door G aging, find out the described aging key logic door G directly affecting this reference circuit time delay aging;
Step (4): judge in aging critical path, described aging key logic door G agingprevious fan-in door G 1output signal:
If: described previous fan-in door G 1output be " 0 ",
Then: samely add sleep signal at input end replacement door G 1' replace described previous fan-in door G 1, this replacement door G can be made when described reference circuit leaves unused 1' output become " 1 ", reach the aging object delaying NBTI effect and cause, and record all logic gates for replacing;
If: described previous fan-in door G 1output be " 1 ",
Then: abandon the previous fan-in door G described in replacing 1;
Step (5): same replacement door G PMOS/NMOS transistor width length geometric ratio being amplified to (door adjusted size method) aging' replace aging key logic door G aging, to increase this aging key logic door G agingcritical charge amount, thus weaken and even shield the single-ion transient state down pulse (being referred to as the pulse of SET transient fault) of one fixed width, reach the object of tolerance soft error, and record all logic gates for replacing;
Step (6): search described aging key logic door G aginglatch set { the L connected aging_sub, and the latch set { L described in judging aging_subcharacter:
If: described latch set { L aging_subin comprise the latch reinforced;
Then: from described latch set { L aging_subin the latch reinforced of rejecting;
Step (7): the replacement latch L of same anti-single particle overturn SEU aging' replace this latch set { L agingelement, by this latch set { L agingelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing;
Step (8): judge this aging key logic door G agingwith the logic gate set { G that soft error occurs errorrelation:
If: this aging key logic door G agingfor there is the logic gate set { G of soft error errorelement;
Then: from the logic gate set { G that soft error occurs errormiddle this aging key logic door G of rejecting aging, and access the aging key logic door G described in the next one aging;
If: this aging key logic door G agingnot for there is the logic gate set { G of soft error errorelement,
Then: abandon the logic gate set { G from there is soft error errormiddle this aging key logic door G of rejecting aging, and the next described aging key logic door G of access aging;
Step (9): access logic gate G that is in described reference circuit on sequential key path and that reinforce without door adjusted size method by described topological sequence timing, find out the sequential key logic gate G directly affecting this reference circuit performance timing;
Step (10): the same replacement door G that PMOS/NMOS transistor width length geometric ratio is amplified timing' replace sequential key logic gate G timing, to increase sequential key logic gate G timingcritical charge amount, thus weaken and even shield the SET transient fault pulse of one fixed width, reach the object of tolerance soft error, and record all logic gates for replacing;
Step (11): search described sequential key logic gate G timinglatch set { the L connected timing, and the latch set { L described in judging timingcharacter:
If: described latch set { L timingin comprise the latch reinforced;
Then: from described latch set { L timingin the latch reinforced of rejecting;
Step (12): the replacement latch L of same anti-SEU timing' replace latch set { L timingelement, by this latch set { L timingelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing;
Step (13): judge this sequential key logic gate G timingwith the logic gate set { G that soft error occurs errorrelation:
If: this sequential key logic gate G timingfor there is the logic gate set { G of soft error errorelement,
Then: from the logic gate set { G that soft error occurs errormiddle this sequential key of rejecting logic gate G timing, and access the sequential key logic gate G described in the next one timing;
If: this sequential key logic gate G timingnot for there is the logic gate set { G of soft error errorelement,
Then: abandon the logic gate set { G from there is soft error errormiddle this sequential key of rejecting logic gate G timing, and access the sequential key logic gate G described in the next one timing;
Step (14): judge whether consolidation effect has reached the reliability objectives of integrated circuit (IC) design:
If: consolidation effect does not reach the reliability objectives of integrated circuit (IC) design,
Then: to soft error key logic door G errorafter reinforcing, by this soft error key logic door G errorfrom the logic gate set { G that soft error occurs errormiddle rejecting, and access the soft error key logic door G described in the next one error;
If: consolidation effect has reached the reliability objectives of integrated circuit (IC) design,
Then: stop strengthening flow process.
In step (4), for the replacement of not right and wrong door, if after replacing when circuit leaves unused described previous fan-in door G 1output be still " 0 ", then attempt replacing G 1all fan-in doors to make G 1output become " 1 ", if still can not G be made 1output become " 1 ", then do not replace G 1.
In step (14), for soft error key logic door G errorreinforcement means, from the logic gate set { G of soft error occurs errorin take out the highest logic gate G of soft error rate error_top, the logic gate G that this soft error rate is the highest error_topone be decided to be by described topological sequence access in described reference circuit in non-aging critical path, in non-sequential critical path, without door adjusted size method reinforce remaining logic gate G error;
Search described soft error key logic door G errorlatch set { the L connected error, and the latch set { L described in judging errorcharacter:
If: described latch set { L errorin comprise the latch reinforced;
Then: from described latch set { L errorin the latch reinforced of rejecting;
Now, described latch set { L errorin do not comprise the latch reinforced, the replacement latch L of same tolerance SET and SEU error' replace this latch set { L errorelement, by this latch set { L errorelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing.
In step (9), when the time sequence allowance of sequential critical path is less than the replacement latch L tolerating SET and SEU described in step (14) error' time delay, do not reinforce by step (14), need be reinforced by step (10), (11), (12), (13), otherwise sequential occurs in violation of rules and regulations.
Advantage of the present invention is:
1) replace door method structure simple, and do not affect the performance of circuit itself, by a kind of this method, when integrated circuit leaves unused, what can delay that NBTI effect causes is circuit aging;
2) door adjusted size method is easy to realize, do not affect the performance of circuit itself equally, by a kind of this method, when integrated circuit operation (effective equally time idle), the SET transient fault pulse (within the scope of one fixed width) that even shielding space radiation effect causes can be weakened;
3) latch carrying out anti-SEU in aging critical path and sequential key path is replaced, do not affect the performance of circuit itself equally, by a kind of this method, when integrated circuit operation (effective equally time idle), the SEU that energy tolerance space radiation effect causes;
4) latch carrying out anti-SET and SEU on non-critical path is replaced, do not affect the performance of circuit itself equally, by a kind of this method, when integrated circuit operation (effective equally time idle), the SET transient fault pulse (within the scope of one fixed width) that even shielding space radiation effect causes can be weakened simultaneously, and to SEU immunity.
Accompanying drawing explanation
Fig. 1 is the present invention's gate replacing method for NBTI in critical path.
Fig. 2 is the present invention's door adjusted size method for SET in aging critical path and sequential key path.
Fig. 3 is the present invention sets up electric effect look-up table overall flow when counting circuit soft error rate.
Fig. 4 is that the present invention works in coordination with the circuit soft error rate overall calculation flow process considering NBTI effect.
Fig. 5 is the tolerance SEU latch that the present invention replaces in aging critical path and sequential key path.
Fig. 6 is the latch tolerating SET and SEU while the present invention replaces on non-critical path.
Fig. 7 is whole implementation process flow diagram of the present invention.
Embodiment
Delaying aging also tolerates the integrated circuit selective reinforcement means of soft error, and utilize computing machine to carry out design of Simulation to reference circuit, concrete steps are as follows:
Step (1): test signal topological sequences when described reference circuit being tested to described computer input;
Step (2): calculate the integrated circuit soft error rate considering negative bias thermal instability NBTI effect, finds out the logic gate set { G that soft error occurs errorand there is the latch set { L of soft error error, and by the logic gate set { G of described generation soft error errorand the latch set { L of described generation soft error errorelement sort from high to low according to the size of soft error rate;
Step (3): access each the NAND Logic door in described reference circuit in aging critical path by described topological sequence, i.e. aging key logic door G aging, find out the described aging key logic door G directly affecting this reference circuit time delay aging;
Step (4): judge in aging critical path, described aging key logic door G agingprevious fan-in door G 1output signal:
If: described previous fan-in door G 1output be " 0 ",
Then: samely add sleep signal at input end replacement door G 1' replace described previous fan-in door G 1, this replacement door G can be made when described reference circuit leaves unused 1' output become " 1 ", reach the aging object delaying NBTI effect and cause, and record all logic gates for replacing;
If: described previous fan-in door G 1output be " 1 ",
Then: abandon the previous fan-in door G described in replacing 1;
Step (5): same replacement door G PMOS/NMOS transistor width length geometric ratio being amplified to (door adjusted size method) aging' replace aging key logic door G aging, to increase this aging key logic door G agingcritical charge amount, thus weaken and even shield the single-ion transient state down pulse (being referred to as the pulse of SET transient fault) of one fixed width, reach the object of tolerance soft error, and record all logic gates for replacing;
Step (6): search described aging key logic door G aginglatch set { the L connected aging_sub, and the latch set { L described in judging aging_subcharacter:
If: described latch set { L aging_subin comprise the latch reinforced;
Then: from described latch set { L aging_subin the latch reinforced of rejecting;
Step (7): the replacement latch L of same anti-single particle overturn SEU aging' replace this latch set { L agingelement, by this latch set { L agingelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing;
Step (8): judge this aging key logic door G agingwith the logic gate set { G that soft error occurs errorrelation:
If: this aging key logic door G agingfor there is the logic gate set { G of soft error errorelement;
Then: from the logic gate set { G that soft error occurs errormiddle this aging key logic door G of rejecting aging, and access the aging key logic door G described in the next one aging;
If: this aging key logic door G agingnot for there is the logic gate set { G of soft error errorelement,
Then: abandon the logic gate set { G from there is soft error errormiddle this aging key logic door G of rejecting aging, and the next described aging key logic door G of access aging;
Step (9): access logic gate G that is in described reference circuit on sequential key path and that reinforce without door adjusted size method by described topological sequence timing, find out the sequential key logic gate G directly affecting this reference circuit performance timing;
Step (10): the same replacement door G that PMOS/NMOS transistor width length geometric ratio is amplified timing' replace sequential key logic gate G timing, to increase sequential key logic gate G timingcritical charge amount, thus weaken and even shield the SET transient fault pulse of one fixed width, reach the object of tolerance soft error, and record all logic gates for replacing;
Step (11): search described sequential key logic gate G timinglatch set { the L connected timing, and the latch set { L described in judging timingcharacter:
If: described latch set { L timingin comprise the latch reinforced;
Then: from described latch set { L timingin the latch reinforced of rejecting;
Step (12): the replacement latch L of same anti-SEU timing' replace latch set { L timingelement, by this latch set { L timingelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing;
Step (13): judge this sequential key logic gate G timingwith the logic gate set { G that soft error occurs errorrelation:
If: this sequential key logic gate G timingfor there is the logic gate set { G of soft error errorelement,
Then: from the logic gate set { G that soft error occurs errormiddle this sequential key of rejecting logic gate G timing, and access the sequential key logic gate G described in the next one timing;
If: this sequential key logic gate G timingnot for there is the logic gate set { G of soft error errorelement,
Then: abandon the logic gate set { G from there is soft error errormiddle this sequential key of rejecting logic gate G timing, and access the sequential key logic gate G described in the next one timing;
Step (14): judge whether consolidation effect has reached the reliability objectives of integrated circuit (IC) design:
If: consolidation effect does not reach the reliability objectives of integrated circuit (IC) design,
Then: to soft error key logic door G errorafter reinforcing, by this soft error key logic door G errorfrom the logic gate set { G that soft error occurs errormiddle rejecting, and access the soft error key logic door G described in the next one error;
If: consolidation effect has reached the reliability objectives of integrated circuit (IC) design,
Then: stop strengthening flow process.
In step (4), for the replacement of not right and wrong door, if after replacing when circuit leaves unused described previous fan-in door G 1output be still " 0 ", then attempt replacing G 1all fan-in doors to make G 1output become " 1 ", if still can not G be made 1output become " 1 ", then do not replace G 1.
In step (14), for soft error key logic door G errorreinforcement means, from the logic gate set { G of soft error occurs errorin take out the highest logic gate G of soft error rate error_top, the logic gate G that this soft error rate is the highest error_topone be decided to be by described topological sequence access in described reference circuit in non-aging critical path, in non-sequential critical path, without door adjusted size method reinforce remaining logic gate G error;
Search described soft error key logic door G errorlatch set { the L connected error, and the latch set { L described in judging errorcharacter:
If: described latch set { L errorin comprise the latch reinforced;
Then: from described latch set { L errorin the latch reinforced of rejecting;
Now, described latch set { L errorin do not comprise the latch reinforced, the replacement latch L of same tolerance SET and SEU error' replace this latch set { L errorelement, by this latch set { L errorelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing.
In step (9), when the time sequence allowance of sequential critical path is less than the replacement latch L tolerating SET and SEU described in step (14) error' time delay, do not reinforce by step (14), need be reinforced by step (10), (11), (12), (13), otherwise sequential occurs in violation of rules and regulations.
Although a lot of scholar proposes the method delaying the soft error that aging and tolerance space radiation effect that NBTI effect causes causes respectively, but up to the present, also do not have scholar to propose a kind ofly to reach these two objects simultaneously and not affect the effective ways of circuit performance.The method that the present invention proposes, be when circuit design by Computer Simulation, calculate the circuit node soft error rate considering NBTI effect, and the replacement allocative decision of logic gate and latch in evaluation circuits.Manufacturing circuit by replacing allocative decision, under the prerequisite not affecting circuit performance, using when circuit leaves unused signal controls the input signal of the logic gate after replacing thus reaches the aging object delaying NBTI effect and cause.Meanwhile, the logic gate original logic gate to soft error sensitivity being replaced with large-size in aging critical path and sequential key path when circuit working (effective equally time idle) can reach the object that reduction even shields the SET transient fault pulse of one fixed width.Moreover, the latch that aging critical path is connected with logic gate on sequential key path is replaced with the latch of tolerance SEU, can to SEU immunity.Finally, latch logic gate on non-critical path connected replaces with the reinforced lock storage simultaneously tolerating SET and SEU, not only can weaken the SET transient fault pulse even shielding the one fixed width come from propagate upstream, and to SEU immunity, thus reach the object of tolerance soft error.
The basic thought that door is replaced is, original aging key logic door replace with and there is said function, but add the door of a sleep control signal wherein be the input signal topological sequences of this logic gate, sleep is the sleep control signal of circuit.Door replacement technology need meet the following conditions:
(1) when the circuit is operating (sleep=0), namely, before and after replacement, the function of logic gate needs completely the same;
(2) when circuit leaves unused (sleep=1), with compare, can as an internal control node delay that NBTI effect causes aging.
Consider the aging situation different with soft error two kinds, it is how to delay that NBTI effect causes aging that Fig. 1 illustrates circuit door replacement technology when idle, it is how to weaken the soft error that even shielding SET pulse causes (to be only illustrated the logic gate of NAND2 and INV respectively in Fig. 1, Fig. 2 that Fig. 2 illustrates an adjusted size method, and be not limitation of the present invention, gate replacing method and door adjusted size method can be implemented on the logic gate of any one type).And for how tolerating SEU, be then the latch (only tolerating SEU) that the latch connected logic gate in aging critical path or sequential key path replaces with to SEU immunity, or the latch (simultaneously can tolerate SET and SEU) of anti-SET and SEU is simultaneously replaced with to the latch that logic gate on non-critical path connects.
In FIG, when circuit leaves unused, due to NAND2 logic gate G 2fan-in door G 1output be " 0 ", make G 2be in negative bias state, so G 2the impact being subject to NBTI effect is very large.If by G 1replace with a NAND3 logic gate G 1', then when circuit leaves unused, rely on sleep signal, G 1' output can become " 1 ", make G 2be in positive bias state, therefore effectively alleviate G 2nBTI effect.
The delaying aging that the present invention proposes also tolerates the integrated circuit selective reinforcement means of soft error, mainly implements by following four steps:
1, calculate the integrated circuit soft error rate considering NBTI effect, find out logic gate the set ({ G that soft error occurs error) and latch the set ({ L of soft error occurs error), and by logic gate the set ({ G of described generation soft error error) and latch the set ({ L of described generation soft error error) element sort from high to low according to the size of soft error rate.
2, investigate the input of the logic gate in all aging critical paths, and to driving the logic gate of these inputs to replace, make the aging as far as possible little of the logic gate in aging critical path; , by door adjusted size method, the logic gate in aging critical path is replaced meanwhile, and by anti-SEU means of reinforcing, the latch that the logic gate in aging critical path connects is replaced.
3, investigate the logic gate on all sequential key paths, the logic gate on all sequential key paths is replaced with to the logic gate of large-size, the logic gate on sequential key path is weakened even shield the SET transient fault pulse of one fixed width; Meanwhile, the latch that the logic gate on sequential key path connects is replaced with the latch of tolerance SEU.
4, the latch connected the logic gate on non-critical path replaces with the latch simultaneously tolerating SET and SEU.
Below illustrating of these four steps:
The first step, calculates the integrated circuit soft error rate considering NBTI effect, finds out logic gate the set ({ G that soft error occurs error) and latch the set ({ L of soft error occurs error), and by logic gate the set ({ G of described generation soft error error) and latch the set ({ L of described generation soft error error) element sort from high to low according to the size of soft error rate.
The specific implementation details of this step is as follows:
1) parameter reads and described reference circuit net table analysis
Parameter reads the circuit node state, the door characteristic parameter table that mainly comprise and to apply to test circuit under different test and excitation (signal topological sequences), and soft error rate parameter of analytic model; Described reference circuit net table analysis is the fan-in fan-out topological relation being obtained all logic gates of described reference circuit by circuit meshwork list analyzer.
2) logic shielding effect is analyzed
Test signal topological sequences when described reference circuit being tested to described computer input; Use circuit emulator to carry out Gate Level Simulation to described reference circuit and obtain all logic gate input/output signals, the sensitized path of logic gate to latch or main output is searched by sensitized path lookup algorithm, and the logic gate types recorded on sensitized path and quantity.
3) fault simulation
Use two Exponential current source model to carry out direct fault location to the logic gate that sensitized path may break down, and simulate the initial SET pulse produced at its output terminal.Two Exponential current source models that this step uses are as follows:
I inj ( t ) = Q τ α - τ β ( e - t / τ α - e - t / τ β )
Wherein Q is incident particle deposited charge amount, τ αfor charge collection time constant, τ βfor charge pathway constant Time Created, the value of time constant is relevant to circuit technology size.
4) electric effect analysis
NBTI is used to cause the analytic model of pulse broadening in production process to carry out broadening to initial SET pulse; Further, use to combine and consider that the electric effect look-up table of NBTI quantizes the broadening of SET pulse in communication process, thus by the SET pulse propagation of simulation to latch or main output.The Establishing process of electric effect look-up table as shown in Figure 3.The NBTI model that this step uses is as follows:
Wherein Δ V thfor threshold voltage delta, A, K v, β tfor the function of voltage, temperature, negative bias time and duty cycle alpha, δ and c is constant, t oxfor grid oxide layer thickness, t 0the beginning and ending time that PMOS transistor stands static NBTI effect is respectively, T with t clkfor the circuit working clock period, n is time index.
5) by time window screening model assessment propagate the error probability that the SET pulse that arrives latch causes latch, and error probability to be added up.The time window screening model that this step uses is as follows:
P g &RightArrow; l v ( &epsiv; ) = 0 , T pw < T setup + T hold T pw - T sh T c , T pw &GreaterEqual; T setup + T hold
Wherein T pwfor propagating into the SET pulse width of latch, T setup+ T hold(referred to as T sh) be latching element foundation and retention time sum, T cfor the circuit working clock period.The above formula left side is under certain group input vector v, and the SET pulse that logic gate g produces is propagated along sensitized path and is latched the probability of device l latch.
6) judge whether that the particle bombardment of more multi-energy is to this fault door.If not, then the 7th is carried out) step; Otherwise use the particle simulation direct fault location of lower a kind of energy, and carry out the 3rd) step;
7) more logic gates that may be subject to particle bombardment are judged whether.If not, then the 8th is carried out) step; Otherwise search next fault door, and carry out the 3rd) step;
8) the circuit soft error rate considering NBTI effect is calculated.Soft error rate overall calculation framework as shown in Figure 4.The soft error rate computing formula that this step uses is as follows:
SER＝FP comb×R EH×R PH×A comb×3600×10 9
Wherein R eHwith R pHbe respectively the effective impact rate of particle in radiation environment and particle flux, value is 2.2 × 10 respectively -5, 56.5m -2s -1.A combfor circuit all logic gate areas summation.
9) node soft error rate sequence.
By soft error rate and respective nodes name storage in chained list List or map in Map, use the efficient sequence of standard static template base STL algorithm realization node soft error rate.
Second step, investigates the input of the logic gate in all aging critical paths, and to driving the logic gate of these inputs to replace, makes the aging as far as possible little of the logic gate in aging critical path., by door adjusted size method, the logic gate in aging critical path is replaced meanwhile, and by anti-SEU means of reinforcing, the latch that the logic gate in aging critical path connects is replaced.
By each logic gate in topological sequences access circuit.If a logic gate (is designated as G aging) be aging key logic door (directly affecting the logic gate of circuit time delay), and when its previous fan-in door (is designated as G 1) output be " 0 ", then replace G 1for G 1'.If rely on the sleep signal of circuit can make G when circuit leaves unused after replacing 1' output become " 1 ", then record this replacement (that is, when circuit manufactures, G 1logic gate should with the G after replacement 1' manufacture); If the G after replacing 1' output when circuit leaves unused is still " 0 ", then according to G 1type attempt replace G 1all fan-in doors to make G 1output become " 1 ", if can requirement be reached, then record the logic gate of all replacements, otherwise abandon G agingall trials and consider G in topological sequences agingnext logic gate.
For reaching the object of tolerance soft error, in the process as above operated, by door adjusted size method to aging key logic door G agingreplace with the logic gate G of large-size aging', the logic gate in aging critical path is weakened even shield the SET transient fault pulse of one fixed width, and record this replacement (that is, when circuit manufactures, G agingthis logic gate should with the G after replacement aging' manufacture).Meanwhile, by latch L that aging key logic door connects agingreplace with the latch L of anti-SEU aging', the latch that aging key logic door is connected to SEU immunity, and record this replacement (that is, when circuit manufactures, L agingthis latch should with the L after replacement aging' manufacture).
Door is replaced and is caused aging overall thought to be for reducing NBTI effect, when circuit leaves unused, the output of aging key logic doors all in circuit is become " 1 " all as much as possible, thus make PMOS transistor be in positive bias state and alleviate that NBTI effect causes aging.
Door is replaced for tolerating that the overall thought of soft error is, when circuit working (effective equally time idle), make the critical charge amount of all aging key logic doors in circuit as far as possible large, make the SET transient fault pulse strength that produced by particle bombardment aging key logic door as far as possible little thus the SET pulse of tolerance one fixed width.
Latch is replaced for tolerating that the overall thought of soft error is, when circuit working (effective equally time idle), the latch that aging key logic door is connected is to SEU immunity.
3rd step, investigates the logic gate on all sequential key paths, the logic gate on all sequential key paths is replaced with to the logic gate of large-size, the logic gate on sequential key path is weakened even shield the SET transient fault pulse of one fixed width; Meanwhile, the latch that the logic gate on sequential key path connects is replaced with the latch of anti-SEU.
For reaching the object of tolerance soft error, in second step, during by each logic gate in topological sequences access circuit, if a logic gate (is designated as G timing) be that sequential key logic gate (directly affects circuit time delay and except aging key logic door G agingoutside logic gate), by door adjusted size method to sequential key logic gate G timingreplace with the logic gate G of large-size timing', the logic gate on sequential key path is weakened even shield the SET transient fault pulse of one fixed width, and record this replacement (that is, when circuit manufactures, G timingthis logic gate should with the G after replacement timing' manufacture); Meanwhile, latch L sequential key logic gate connected timingreplace with the latch L of anti-SEU timing', the latch that sequential key logic gate is connected to SEU immunity, and record this replacement (that is, when circuit manufactures, L timingthis latch should with the L after replacement timing' manufacture).
In this step, door is replaced and is replaced for tolerating that the overall thought of soft error is identical with tolerating the overall thought of soft error in second step with latch.
4th step, replaces with to the latch that the logic gate on non-critical path connects the latch simultaneously tolerating SET and SEU.
For reaching the object of tolerance soft error, in the third step, during by each logic gate in topological sequences access circuit, if a logic gate (is designated as G error) be that soft error key logic door is (except aging key logic door G agingwith sequential key logic gate G timingoutside logic gate), by the latch L that soft error key logic door connects errorreplace with the latch L simultaneously tolerating SET and SEU error', the latch that soft error key logic door is connected not only to SEU immunity, and can weaken and even shields propagate upstream and the SET transient fault pulse of one fixed width that comes, and record this replacement (that is, when circuit manufactures, L errorthis latch should with the L after replacement error' manufacture).
The latch L of the anti-SEU used in above step aging' structure as shown in Figure 5, tolerate the latch of SET and SEU while use as shown in Figure 6, retarding ageing the integrated circuit selective reinforcement unitarity flow process tolerating soft error are as shown in Figure 7.

Claims (4)

1. delaying aging tolerate the integrated circuit selective reinforcement means of soft error, is characterized in that: utilize computing machine to carry out design of Simulation to reference circuit, concrete steps are as follows:
Step (1): test signal topological sequences when described reference circuit being tested to described computer input;
Step (2): calculate the integrated circuit soft error rate considering negative bias thermal instability NBTI effect, finds out the logic gate set { G that soft error occurs errorand there is the latch set { L of soft error error, and by the logic gate set { G of described generation soft error errorand the latch set { L of described generation soft error errorelement sort from high to low according to the size of soft error rate;
Step (3): access each the NAND Logic door in described reference circuit in aging critical path by described topological sequence, i.e. aging key logic door G aging, find out the described aging key logic door G directly affecting this reference circuit time delay aging;
Step (4): judge in aging critical path, described aging key logic door G agingprevious fan-in door G 1output signal:
If: described previous fan-in door G 1output be " 0 ",
Then: samely add sleep signal at input end replacement door G 1' replace described previous fan-in door G 1, and record all logic gates for replacing;
If: described previous fan-in door G 1output be " 1 ",
Then: abandon the previous fan-in door G described in replacing 1;
Step (5): the same replacement door G that PMOS/NMOS transistor width length geometric ratio is amplified aging' replace aging key logic door G aging, and record all logic gates for replacing;
Step (6): search described aging key logic door G aginglatch set { the L connected aging_sub, and the latch set { L described in judging aging_subcharacter:
If: described latch set { L aging_subin comprise the latch reinforced;
Then: from described latch set { L aging_subin the latch reinforced of rejecting;
Step (7): the replacement latch L of same anti-single particle overturn SEU aging' replace this latch set { L agingelement, by this latch set { L agingelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing;
Step (8): judge this aging key logic door G agingwith the logic gate set { G that soft error occurs errorrelation:
If: this aging key logic door G agingfor there is the logic gate set { G of soft error errorelement;
Then: from the logic gate set { G that soft error occurs errormiddle this aging key logic door G of rejecting aging, and access the aging key logic door G described in the next one aging;
If: this aging key logic door G agingnot for there is the logic gate set { G of soft error errorelement,
Then: abandon the logic gate set { G from there is soft error errormiddle this aging key logic door G of rejecting aging, and the next described aging key logic door G of access aging;
Step (9): access logic gate G that is in described reference circuit on sequential key path and that reinforce without door adjusted size method by described topological sequence timing, find out the sequential key logic gate G directly affecting this reference circuit performance timing;
Step (10): the same replacement door G that PMOS/NMOS transistor width length geometric ratio is amplified timing' replace sequential key logic gate G timing, and record all logic gates for replacing;
Step (11): search described sequential key logic gate G timinglatch set { the L connected timing, and the latch set { L described in judging timingcharacter:
If: described latch set { L timingin comprise the latch reinforced;
Then: from described latch set { L timingin the latch reinforced of rejecting;
Step (12): the replacement latch L of same anti-SEU timing' replace latch set { L timingelement, by this latch set { L timingelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing;
Step (13): judge this sequential key logic gate G timingwith the logic gate set { G that soft error occurs errorrelation:
If: this sequential key logic gate G timingfor there is the logic gate set { G of soft error errorelement,
Then: from the logic gate set { G that soft error occurs errormiddle this sequential key of rejecting logic gate G timing, and access the sequential key logic gate G described in the next one timing;
If: this sequential key logic gate G timingnot for there is the logic gate set { G of soft error errorelement,
Then: abandon the logic gate set { G from there is soft error errormiddle this sequential key of rejecting logic gate G timing, and access the sequential key logic gate G described in the next one timing;
Step (14): judge whether consolidation effect has reached the reliability objectives of integrated circuit (IC) design:
If: consolidation effect does not reach the reliability objectives of integrated circuit (IC) design,
Then: to soft error key logic door G errorafter reinforcing, by this soft error key logic door G errorfrom the logic gate set { G that soft error occurs errormiddle rejecting, and access the soft error key logic door G described in the next one error;
If: consolidation effect has reached the reliability objectives of integrated circuit (IC) design,
Then: stop strengthening flow process.
2. a kind of delaying aging according to claim 1 tolerate the integrated circuit selective reinforcement means of soft error, it is characterized in that: in step (4), for the replacement of not right and wrong door, if after replacing when circuit leaves unused described previous fan-in door G 1output be still " 0 ", then attempt replacing G 1all fan-in doors to make G 1output become " 1 ", if still can not G be made 1output become " 1 ", then do not replace G 1.
3. a kind of delaying aging according to claim 1 tolerate the integrated circuit selective reinforcement means of soft error, is characterized in that: in step (14), for soft error key logic door G errorreinforcement means, from the logic gate set { G of soft error occurs errorin take out the highest logic gate G of soft error rate error_top, the logic gate G that this soft error rate is the highest error_topone be decided to be by described topological sequence access in described reference circuit in non-aging critical path, in non-sequential critical path, without door adjusted size method reinforce remaining logic gate G error;
Search described soft error key logic door G errorlatch set { the L connected error, and the latch set { L described in judging errorcharacter:
If: described latch set { L errorin comprise the latch reinforced;
Then: from described latch set { L errorin the latch reinforced of rejecting;
Now, described latch set { L errorin do not comprise the latch reinforced, the replacement latch L of same tolerance SET and SEU error' replace this latch set { L errorelement, by this latch set { L errorelement from the latch set { L of described generation soft error errormiddle rejecting, and record all latchs for replacing.
4. a kind of delaying aging according to claim 1 tolerate the integrated circuit selective reinforcement means of soft error, it is characterized in that: in step (9), when the time sequence allowance of sequential critical path is less than the replacement latch L tolerating SET and SEU described in step (14) error' time delay, do not reinforce by step (14), need be reinforced by step (10), (11), (12), (13), otherwise sequential occurs in violation of rules and regulations.
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