CN104778324A - Integrated circuit selective reinforcement method with aging delaying and soft error tolerance functions - Google Patents

Abstract

The invention discloses an integrated circuit selective reinforcement method with aging delaying and soft error tolerance functions. According to the integrated circuit selective reinforcement method with the aging delaying and soft error tolerance functions, on the premise of not affecting the circuit performance, partial extra power consumption and area overhead are increased, less computer simulation operation time is increased in the circuit designing process, and a part of logic gates are replaced in the circuit, so that the aging of the circuit can be delayed when the circuit is idle and in a sleeping state, and soft errors, caused by SET transient fault pulses with certain widths, can be weakened even shielded when the circuit is at work. Meanwhile, a part of latches are replaced in the aging critical paths and time sequence critical paths of the circuit, so that the circuit can be immune to SEU which causes the soft errors in the working process; a part of latches are replaced in the non-critical paths, so that the circuit can weaken and even shield the SET transient pulses with certain widths in the working process, and is immune to the SEU, therefore the purpose of tolerating the soft errors is achieved.

Description

A Selective Hardening Method for Integrated Circuits to Delay Aging and Tolerate Soft Errors

technical field

The invention relates to the field of fault-tolerant design of technical integrated circuits, in particular to an integrated circuit selective reinforcement method that delays aging and tolerates soft errors.

Background technique

The aging of integrated circuits can be caused by a variety of physical effects, among which the common aging causes are: negative bias temperature instability NBTI, gate oxide time-dependent breakdown (Time-Dependent Dielectric Breakdown, referred to as TDDB), hot carrier injection (Hot Carrier Injection, referred to as HCI) and electromigration (Electromigration, referred to as EM). Existing studies have shown that under nanotechnology, the NBTI effect is the main factor leading to the aging of integrated circuits.

The NBTI effect is a physical effect that acts on the PMOS transistor and causes its performance to decline. The occurrence process of this effect follows the reaction-diffusion model. When the gate of the PMOS transistor is in a negative bias state, that is, when the gate voltage is "0", the silicon-hydrogen bond on the interface of the silicon oxide layer of the transistor is broken under the action of a high electric field, thereby forming a positive charge in the channel. holes, the state of the PMOS transistor at this time is called the burn-in bias period. As the gate stress time of the PMOS transistor continues to increase, more silicon-hydrogen bonds are broken, hydrogen gas is formed and released from the interface oxide layer. Due to the continuous increase of positively charged holes, the conduction capability of the channel of the PMOS transistor decreases, the driving current of the transistor decreases continuously, and the threshold voltage continuously increases.

Under the action of NBTI effect, when the gate is negatively biased, although the PMOS transistor will age, but when the gate is forward biased, that is, the gate voltage is "1", the hydrogen atoms in the transistor will Recombine with positively charged silicon ions to reduce the number of holes in the channel, thereby realizing partial self-recovery of transistor aging. At this time, the PMOS transistor is in the aging recovery period. Therefore, the aging of digital integrated circuits caused by the NBTI effect has the characteristics of partial self-recovery.

According to the characteristics of NBTI effect itself, it can be divided into static NBTI effect and dynamic NBTI effect. When the gate is always in a negative bias state, the PMOS transistor will continue to age. At this time, it is called the static NBTI effect. When the gate alternately has positive and negative voltages, the PMOS transistor will alternately be in the aging bias period and the aging recovery period. At this time, it is called the dynamic NBTI effect. When under the static NBTI effect, the threshold voltage of the transistor will continue to rise; while under the influence of the dynamic NBTI effect, the threshold voltage of the PMOS transistor will change in an alternating manner of rising and falling, that is, the threshold voltage will continue to increase during the aging bias period. During the aging recovery period, the threshold voltage will decrease.

With the continuous improvement of the technology level, the thickness of the gate oxide layer of the MOS transistor is continuously reduced, and the NBTI effect becomes more and more serious. In recent years, scholars have continuously studied and proposed technologies to delay the aging caused by NBTI. Huazhong Yang et al. proposed gate replacement technology in the document Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques, which can simultaneously delay the aging of integrated circuits and reduce leakage power consumption; Kumar et al. In the document Impact of NBTI on SRAM Read Stability and Design for In Reliability, a method of bit flipping is proposed, which effectively restores the static noise margin of SRAM cells; in addition, there are pin reordering methods, NBTI synthesis methods, input vector control and other technologies.

On the other hand, with the continuous reduction of the size of the integrated circuit process, the supply voltage is continuously reduced, resulting in the continuous reduction of the node capacitance of the circuit, so that the amount of charge (critical charge) required to flip the logic state of the circuit node is also reduced. , circuits are increasingly susceptible to soft errors caused by particles such as heavy ions, alpha particles, neutrons, and protons in the space radiation environment.

Particles incident in the sensitive area of the transistor in the space radiation environment will cause ionization of the semiconductor material, and deposit charges will be generated on the incident trajectory of the particles and collected by the sensitive node, causing single event effects. In the absence of an electric field, the ionized electron-hole pairs have no effect on the normal operation of the circuit. But when there is an electric field, the electron-hole pairs on the particle track will be collected by the electrodes, forming an instantaneous current. If this situation occurs in a combinational circuit, a large instantaneous current will cause a transient change in the output voltage of the logic gate, thereby generating a SET transient pulse; if this situation occurs in a memory circuit, the transistor drain and the substrate A large amount of charge transfer between the memory cells will change the normal logic state of the memory cell, that is, SEU occurs, which is manifested as a data bit flip.

SET and SEU are important causes of single event failure in integrated circuits. For the anti-single event hardening technology of integrated circuits, many schemes have been proposed at home and abroad, and redundancy is the most commonly used method. Redundancy technology is mainly divided into space redundancy and time redundancy. For the SET generated by combinational logic, there are schemes such as copy gate method, voltage adjustment method, gate size adjustment method, output clamp circuit method and logic node selection method. For the anti-SEU hardening technology of the sequential unit, it is mainly to design a sequential unit structure with anti-SEU, and replace the traditional sequential unit with the anti-SEU sequential unit. By constructing a sequential cell structure resistant to soft errors, the sensitivity of memory cells in the circuit to soft errors will be greatly reduced. Existing anti-radiation hardening structures such as TMR-latch, DICE-latch, HiPeR-latch, and various latch structures proposed by Hefei University of Technology.

In the field of aerospace, integrated circuits work for a long time in the space radiation environment where there are a large number of high-energy particles and cosmic rays, which poses a severe challenge to the reliability of the circuit. At the same time, the improvement of the technology level makes the aging caused by the NBTI effect more and more impossible to ignore. Therefore, it has important practical significance and application value to carry out selective hardening and fault-tolerant design for anti-aging and anti-soft errors on integrated circuits with low overhead. Although many scholars have respectively proposed methods to delay the aging caused by the NBTI effect and tolerate soft errors caused by the space radiation effect. But so far, no scholars have proposed an effective method that can simultaneously achieve these two goals without affecting circuit performance, but the method proposed by the present invention can well suppress SET and SEU at the same time, and can delay the NBTI effect leading to of aging. Since the proposed method can effectively reduce the probability of soft errors in the circuit, thereby improving the reliability of the integrated circuit, it can be applied in the aerospace field.

Contents of the invention

The object of the present invention is to remedy the defects of the prior art, and provide a selective hardening method for integrated circuits that delays aging and tolerates soft errors.

The present invention is achieved through the following technical solutions:

A selective hardening method for an integrated circuit that delays aging and tolerates soft errors. The reference circuit is simulated and designed by a computer. The specific steps are as follows:

Step (1): input the test signal topology sequence used when testing the reference circuit to the computer;

Step (2): Calculate the soft error rate of the integrated circuit considering the NBTI effect of negative bias temperature instability, find out the set of logic gates {G _error } and the set of latches {L _error } that have soft errors, and sort the elements of the soft error logic gate set {G _error } and the soft error latch set {L _error } from high to low according to the soft error rate;

Step (3): visit each NAND logic gate on the aging critical path in the reference circuit according to the topology signal sequence, that is, the aging critical logic gate G _aging , and find out the aging factor that directly affects the time delay of the reference circuit Key logic gate G _aging ;

Step (4): On the aging critical path, the output signal of the previous fan gate G ₁ of the aging critical logic gate G _aging is determined:

If: the output of the previous fan gate _G1 is "0",

Then: the same one adds a sleep signal at the input The replacement gate G ₁ ' replaces the previous fan gate G ₁ , so that the output of the replacement gate G ₁ ' can be changed to "1" when the reference circuit is idle, so as to delay the aging caused by the NBTI effect, and record all logic gates used for replacement;

If: the output of the previous fan gate G ₁ is "1",

Then: give up replacing the previous fan gate G ₁ ;

Step (5): Replace the aging key logic gate G _aging with the same replacement gate G _aging that enlarges the width and length of the PMOS/NMOS transistor proportionally (gate size adjustment method), so as to increase the critical charge of the aging key logic gate G _aging , so as to weaken or even shield the single-event transient fault pulse of a certain width (called SET transient fault pulse), achieve the purpose of tolerating soft errors, and record all logic gates used for replacement;

Step (6): Find the latch set {L _{aging_sub} } connected to the aging key logic gate G _aging , and judge the nature of the latch set {L _{aging_sub} }:

If: the set of latches {L _{aging_sub} } contains hardened latches;

Then: remove hardened latches from the set of latches {L _{aging_sub} };

Step (7): replace the elements of the latch set {L aging } with a replacement latch L _aging ' of _{the anti-single event upset SEU, and replace the elements of the latch set {L aging }} from the generation Remove from the set of latches with soft errors {L _error }, and record all latches used for replacement;

Step (8): Determine the relationship between the aging key logic gate G _aging and the logic gate set {G _error } where soft errors occur:

If: the aging key logic gate G _aging is an element of the logic gate set {G _error } where a soft error occurs;

Then: remove the aging key logic gate G _aging from the logic gate set {G _error } where soft errors occur, and access the next aging key logic gate G _aging ;

If: the aging key logic gate G _aging is not an element of the logic gate set {G _error } where a soft error occurs,

Then: give up removing the aging key logic gate G _aging from the logic gate set {G _error } where soft errors occur, and access the next aging key logic gate G _aging ;

Step (9): Access the logic gate G _timing on the timing critical path in the reference circuit according to the topology signal sequence and is not reinforced by the gate size adjustment method, and find out the timing critical logic gate G that directly affects the performance of the reference circuit _timing ;

Step (10): Replace the _timing -critical logic gate G timing with the same replacement gate G _timing that enlarges the width and length of the PMOS/NMOS transistor proportionally, so as to increase the critical charge of the timing-critical logic gate G _timing , thereby weakening or even shielding a certain width SET transient fault pulses to tolerate soft errors and record all logic gates for replacement;

Step (11): Find the set of latches {L _timing } connected to the _timing -critical logic gate G timing, and judge the nature of the set of latches {L _timing }:

If: the latch set {L _timing } contains hardened latches;

Then: remove hardened latches from the set of latches {L _timing };

Step (12): replace the elements of the latch set {L _{timing } with the same SEU-resistant replacement latch L timing '} , and replace the elements of the latch set {L _timing } from the lock where the soft error occurs register set {L _error }, and record all latches used for replacement;

Step (13): Determine the relationship between the sequence-critical logic gate G _timing and the logic gate set {G _error } where soft errors occur:

If: the timing-critical logic gate G _timing is an element of the logic gate set {G _error } where a soft error occurs,

Then: remove the timing-critical logic gate G _timing from the logic gate set {G _error } where a soft error occurs, and access the next timing-critical logic gate G _timing ;

If: the timing-critical logic gate G _timing is not an element of the logic gate set {G _error } where a soft error occurs,

Then: give up removing the timing-critical logic gate G _timing from the logic gate set {G _error } where a soft error occurs, and access the next timing-critical logic gate G _timing ;

Step (14): Judging whether the reinforcement effect has reached the reliability target of integrated circuit design:

If: the reinforcement effect does not meet the reliability target of integrated circuit design,

Then: after hardening the soft error key logic gate G _error , remove the soft error key logic gate G _error from the soft error logic gate set {G _error }, and access the next soft error key logic gate G _error ;

If: the reinforcement effect has reached the reliability target of integrated circuit design,

Then: terminate the hardening process.

In step (4), for the replacement that is not a NAND gate, if the output of the previous fan gate _G1 is still "0" when the circuit is idle after the replacement, then try to replace all fan gates of _G1 so that The output of G ₁ becomes "1", if the output of G ₁ cannot be changed to "1", G ₁ is not replaced.

In step (14), for the hardening method of the soft error key logic gate G _error , the logic gate G _{error_top} with the highest soft error rate is taken out from the logic gate set {G _error } where soft errors occur, and the logic gate with the highest soft error rate The gate G _{error_top} must access the remaining logic gate G _error on the non-aging critical path and the non-timing critical path in the reference circuit according to the topological signal sequence, which has not been hardened by the gate size adjustment method;

Find the latch _set {L error } connected to the soft error key logic gate G _error , and judge the nature of the latch set {L _error }:

If: the set of latches {L _error } contains hardened latches;

Then: remove hardened latches from the set of latches {L _error };

At this time, the latch set {L _error } does not contain hardened latches, and the elements of the latch set {L _error } are replaced with a replacement latch L _error ' that tolerates SET and SEU , remove the elements of the latch set {L _error } from the soft error latch set {L _error }, and record all the latches used for replacement.

In step (9), when the timing margin of the timing critical path is less than the time delay of the replacement latch L _error 'tolerating SET and SEU described in step (14), it cannot be reinforced through step (14), and needs to be strengthened by Steps (10), (11), (12), and (13) are hardened, otherwise timing violations occur.

The advantages of the present invention are:

1) The replacement gate method has a simple structure and does not affect the performance of the circuit itself. With this method, when the integrated circuit is idle, the circuit aging caused by the NBTI effect can be delayed;

2) The gate size adjustment method is easy to implement and does not affect the performance of the circuit itself. With this method, when the integrated circuit is working (it is also effective when idle), it can weaken or even shield the SET transient fault pulse ( within a certain width);

3) Replacement of anti-SEU latches on aging critical paths and timing critical paths also does not affect the performance of the circuit itself. With this method, space radiation can be tolerated when the integrated circuit is working (also effective when idle). SEU caused by the effect;

4) Replacement of anti-SET and SEU latches on non-critical paths also does not affect the performance of the circuit itself. With this method, when the integrated circuit is working (it is also effective when it is idle), the space can be weakened or even shielded at the same time. SET transient fault pulses (within a certain width range) caused by radiation effects and are immune to SEU.

Description of drawings

FIG. 1 is a gate replacement method for NBTI on a critical path according to the present invention.

FIG. 2 is a gate size adjustment method for SET on aging critical paths and timing critical paths according to the present invention.

Fig. 3 is the overall process of establishing the electrical effect look-up table when calculating the circuit soft error rate according to the present invention.

FIG. 4 is the overall calculation flow of the circuit soft error rate in consideration of the NBTI effect in the present invention.

FIG. 5 is a tolerant SEU latch replaced on an aging critical path and a timing critical path according to the present invention.

FIG. 6 is a SET and SEU tolerant latch that the present invention replaces on a non-critical path.

Fig. 7 is an overall implementation flow chart of the present invention.

Detailed ways

A selective hardening method for an integrated circuit that delays aging and tolerates soft errors. The reference circuit is simulated and designed by a computer. The specific steps are as follows:

Step (1): input the test signal topology sequence used when testing the reference circuit to the computer;

Step (2): Calculate the soft error rate of the integrated circuit considering the NBTI effect of negative bias temperature instability, find out the set of logic gates {G _error } and the set of latches {L _error } that have soft errors, and sort the elements of the soft error logic gate set {G _error } and the soft error latch set {L _error } from high to low according to the soft error rate;

Step (3): visit each NAND logic gate on the aging critical path in the reference circuit according to the topology signal sequence, that is, the aging critical logic gate G _aging , and find out the aging factor that directly affects the time delay of the reference circuit Key logic gate G _aging ;

Step (4): On the aging critical path, the output signal of the previous fan gate G ₁ of the aging critical logic gate G _aging is determined:

If: the output of the previous fan gate _G1 is "0",

Then: the same one adds a sleep signal at the input The replacement gate G ₁ ' replaces the previous fan gate G ₁ , so that the output of the replacement gate G ₁ ' can be changed to "1" when the reference circuit is idle, so as to delay the aging caused by the NBTI effect, and record all logic gates used for replacement;

If: the output of the previous fan gate G ₁ is "1",

Then: give up replacing the previous fan gate G ₁ ;

Step (5): Replace the aging key logic gate G _aging with the same replacement gate G _aging that enlarges the width and length of the PMOS/NMOS transistor proportionally (gate size adjustment method), so as to increase the critical charge of the aging key logic gate G _aging , so as to weaken or even shield the single-event transient fault pulse of a certain width (called SET transient fault pulse), achieve the purpose of tolerating soft errors, and record all logic gates used for replacement;

Step (6): Find the latch set {L _{aging_sub} } connected to the aging key logic gate G _aging , and judge the nature of the latch set {L _{aging_sub} }:

If: the set of latches {L _{aging_sub} } contains hardened latches;

Then: remove hardened latches from the set of latches {L _{aging_sub} };

Step (7): replace the elements of the latch set {L aging } with a replacement latch L _aging ' of _{the anti-single event upset SEU, and replace the elements of the latch set {L aging }} from the generation Remove from the set of latches with soft errors {L _error }, and record all latches used for replacement;

Step (8): Determine the relationship between the aging key logic gate G _aging and the logic gate set {G _error } where soft errors occur:

If: the aging key logic gate G _aging is an element of the logic gate set {G _error } where a soft error occurs;

Then: remove the aging key logic gate G _aging from the logic gate set {G _error } where soft errors occur, and access the next aging key logic gate G _aging ;

If: the aging key logic gate G _aging is not an element of the logic gate set {G _error } where a soft error occurs,

Then: give up removing the aging key logic gate G _aging from the logic gate set {G _error } where soft errors occur, and access the next aging key logic gate G _aging ;

Step (9): Access the logic gate G _timing on the timing critical path in the reference circuit according to the topology signal sequence and is not reinforced by the gate size adjustment method, and find out the timing critical logic gate G that directly affects the performance of the reference circuit _timing ;

Step (10): Replace the _timing -critical logic gate G timing with the same replacement gate G _timing that enlarges the width and length of the PMOS/NMOS transistor proportionally, so as to increase the critical charge of the timing-critical logic gate G _timing , thereby weakening or even shielding a certain width SET transient fault pulses to tolerate soft errors and record all logic gates for replacement;

Step (11): Find the set of latches {L _timing } connected to the _timing -critical logic gate G timing, and judge the nature of the set of latches {L _timing }:

If: the latch set {L _timing } contains hardened latches;

Then: remove hardened latches from the set of latches {L _timing };

Step (12): replace the elements of the latch set {L _{timing } with the same SEU-resistant replacement latch L timing '} , and replace the elements of the latch set {L _timing } from the lock where the soft error occurs register set {L _error }, and record all latches used for replacement;

Step (13): Determine the relationship between the sequence-critical logic gate G _timing and the logic gate set {G _error } where soft errors occur:

If: the timing-critical logic gate G _timing is an element of the logic gate set {G _error } where a soft error occurs,

Then: remove the timing-critical logic gate G _timing from the logic gate set {G _error } where a soft error occurs, and access the next timing-critical logic gate G _timing ;

If: the timing-critical logic gate G _timing is not an element of the logic gate set {G _error } where a soft error occurs,

Then: give up removing the timing-critical logic gate G _timing from the logic gate set {G _error } where a soft error occurs, and access the next timing-critical logic gate G _timing ;

Step (14): Judging whether the reinforcement effect has reached the reliability target of integrated circuit design:

If: the reinforcement effect does not meet the reliability target of integrated circuit design,

Then: after hardening the soft error key logic gate G _error , remove the soft error key logic gate G _error from the soft error logic gate set {G _error }, and access the next soft error key logic gate G _error ;

If: the reinforcement effect has reached the reliability target of integrated circuit design,

Then: terminate the hardening process.

In step (4), for the replacement that is not a NAND gate, if the output of the previous fan gate _G1 is still "0" when the circuit is idle after the replacement, then try to replace all fan gates of _G1 so that The output of G ₁ becomes "1", if the output of G ₁ cannot be changed to "1", G ₁ is not replaced.

In step (14), for the hardening method of the soft error key logic gate G _error , the logic gate G _{error_top} with the highest soft error rate is taken out from the logic gate set {G _error } where soft errors occur, and the logic gate with the highest soft error rate The gate G _{error_top} must access the remaining logic gate G _error on the non-aging critical path and the non-timing critical path in the reference circuit according to the topological signal sequence, which has not been hardened by the gate size adjustment method;

Find the latch _set {L error } connected to the soft error key logic gate G _error , and judge the nature of the latch set {L _error }:

If: the set of latches {L _error } contains hardened latches;

Then: remove hardened latches from the set of latches {L _error };

At this time, the latch set {L _error } does not contain hardened latches, and the elements of the latch set {L _error } are replaced with a replacement latch L _error ' that tolerates SET and SEU , remove the elements of the latch set {L _error } from the soft error latch set {L _error }, and record all the latches used for replacement.

In step (9), when the timing margin of the timing critical path is less than the time delay of the replacement latch L _error 'tolerating SET and SEU described in step (14), it cannot be reinforced through step (14), and needs to be strengthened by Steps (10), (11), (12), and (13) are hardened, otherwise timing violations occur.

Although many scholars have proposed methods to delay the aging caused by the NBTI effect and tolerate the soft errors caused by the space radiation effect, so far, no scholar has proposed an effective method that can achieve these two goals at the same time without affecting the circuit performance. . The method proposed by the invention is to calculate the soft error rate of the circuit node considering the NBTI effect through computer simulation during the circuit design, and evaluate the replacement allocation scheme of the logic gate and the latch in the circuit. Manufacture the circuit according to the replacement allocation scheme, and use it when the circuit is idle without affecting the performance of the circuit. The signal controls the input signal of the replaced logic gate so as to delay the aging caused by the NBTI effect. At the same time, when the circuit is working (it is also effective when it is idle), replacing the original logic gates sensitive to soft errors with larger-sized logic gates on the aging critical path and timing critical path can weaken or even shield the SET transient of a certain width. purpose of the fault pulse. Furthermore, replacing the latches connected to the logic gates on the aging-critical and timing-critical paths with SEU-tolerant latches makes them immune to SEU. Finally, replacing the latch connected to the logic gate on the non-critical path with a hardened latch that tolerates both SET and SEU can not only weaken or even shield the SET transient fault pulse of a certain width propagating from the upstream, but also for the SEU immunity, so as to achieve the purpose of tolerating soft errors.

The basic idea of gate replacement is to replace the original aging critical logic gate Replaced by a gate with the same functionality but with the addition of a sleep control signal in is the input signal topology sequence of the logic gate, and sleep is the sleep control signal of the circuit. Door replacement technology needs to meet the following conditions:

(1) When the circuit is working (sleep=0), That is, before and after the replacement, the function of the logic gate must be exactly the same;

(2) When the circuit is idle (sleep=1), and compared to, It can be used as an internal control node to delay the aging caused by NBTI effect.

Considering the two different situations of aging and soft errors, Figure 1 shows how the gate replacement technique can delay the aging caused by the NBTI effect when the circuit is idle, and Figure 2 shows how the gate size adjustment method weakens or even shields the soft error caused by the SET pulse. Mistakes (only one logic gate of NAND2 and INV is exemplified in FIG. 1 and FIG. 2 , but not a limitation of the present invention. The gate replacement method and the gate size adjustment method can be implemented in any type of logic gate). As for how to tolerate SEU, it is to replace the latch connected to the logic gate on the aging critical path or the timing critical path with a latch that is immune to SEU (only SEU is tolerated), or to connect to the logic gate on the non-critical path Replace the latch with a latch resistant to both SET and SEU (both SET and SEU tolerant).

In Figure 1, when the circuit is idle, since the output of the fan gate _G1 of the NAND2 logic gate _G2 is "0", _G2 is in a negative bias state, so _G2 is greatly affected by the NBTI effect. If G ₁ is replaced by a NAND3 logic gate G ₁ ', when the circuit is idle, relying on the sleep signal, the output of G ₁ ' will become "1", making G ₂ in a positive bias state, thus effectively reducing G ₂ NBTI effects.

The selective hardening method for integrated circuits that delays aging and tolerates soft errors proposed by the present invention is mainly implemented in the following four steps:

1. Calculate the soft error rate of the integrated circuit considering the NBTI effect, find out the set of logic gates ({G _error }) and the set of latches ({L _error }) where soft errors occur, and the occurrence The elements of the set of logic gates with soft errors ({G _error }) and the set of latches with soft errors ({L _error }) are sorted from high to low according to the soft error rate.

2. Investigate the inputs of all logic gates on the aging critical path, and replace the logic gates driving these inputs, so that the aging of the logic gates on the aging critical path is as small as possible; at the same time, adjust the gate size on the aging critical path Replace the logic gates, and replace the latches connected to the logic gates on the aging critical path by means of anti-SEU reinforcement.

3. Investigate the logic gates on all timing-critical paths, and replace all logic gates on timing-critical paths with larger-sized logic gates, so that the logic gates on timing-critical paths can weaken or even shield SET transient fault pulses of a certain width ; At the same time, replace the latches connected to the logic gates on the timing-critical paths with SEU-tolerant latches.

4. Replace the latches connected to logic gates on non-critical paths with latches that tolerate both SET and SEU.

Here are the specific instructions for these four steps:

The first step is to calculate the soft error rate of the integrated circuit considering the NBTI effect, find out the set of logic gates ({G _error }) and the set of latches ({L _error }) that have soft errors, and put the The elements of the set of logic gates with soft errors ({G _error }) and the set of latches with soft errors ({L _error }) are sorted from high to low according to the soft error rate.

The specific implementation details of this step are as follows:

1) Parameter reading and netlist analysis of the reference circuit

Parameter reading mainly includes applying to the test circuit the state of the circuit nodes under different test excitations (signal topology sequences), the gate characteristic parameter table, and the soft error rate analysis model parameters; the analysis of the reference circuit netlist is through the circuit netlist analyzer The fan-in and fan-out topological relationships of all logic gates of the reference circuit are obtained.

2) Logic shielding effect analysis

Input the test signal topology sequence used when testing the reference circuit to the computer; use a circuit simulator to perform gate-level simulation on the reference circuit to obtain all logic gate input and output signals, and search for logic gates through a sensitization path search algorithm Sensitized paths to latches or main outputs, and note the type and number of logic gates on the sensitized path.

3) Fault simulation

A double-exponential current source model is used to perform fault injection on logic gates that may fail on the sensitized path and simulate the initial SET pulse generated at its output. The double exponential current source model used in this step is as follows:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; inj</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; Q</span>}}{{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; e</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; \&beta;</span>}}}<span\; class="notranslate">\; )</span>$

Where Q is the amount of charge deposited by incident particles, τ _α is the time constant of charge collection, τ _β is the time constant of charge channel establishment, and the value of the time constant is related to the size of the circuit process.

4) Analysis of electrical effects

The initial SET pulse is broadened using an analytical model that NBTI causes the pulse to broaden during generation; further, the SET pulse broadening during propagation is quantified using a lookup table that considers the electrical effects of NBTI, so that the simulated SET pulse propagation to a latch or main output. The establishment process of the electrical effect lookup table is shown in Figure 3. The NBTI model used in this step is as follows:

Where ΔV _th is the threshold voltage increment, A, K _v , β _t are functions of voltage, temperature, negative bias time and duty cycle α, δ and c are constants, t _ox is the thickness of the gate oxide layer, t ₀ and t is the start and end time of the PMOS transistor subjected to the static NBTI effect, T _clk is the circuit working clock cycle, and n is the time index.

5) Evaluate the error probability caused by the SET pulse propagating to the latch through the time window shielding model, and make statistics on the error probability. The time window shielding model used in this step is as follows:

${\mathrm{<span\; class="notranslate">\; P</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}<span\; class="notranslate">\; \&Right\; Arrow;</span>\mathrm{<span\; class="notranslate">\; l</span>}}^{\mathrm{<span\; class="notranslate">\; v</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&epsiv;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\left\{\begin{array}{cc}\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; ,</span>& {\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; pw</span>}}<span\; class="notranslate">\; <</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; setup</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; hold</span>}}\\ \frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; pw</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; sh</span>}}}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}}<span\; class="notranslate">\; ,</span>& {\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; pw</span>}}<span\; class="notranslate">\; \&Greater\; Equal;</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; setup</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; hold</span>}}\end{array}\right.$

Where T _pw is the SET pulse width propagated to the latch, T _setup + T _hold (abbreviated as T _sh ) is the sum of the setup and hold time of the latch element, and T _c is the circuit working clock cycle. The left side of the above formula is the probability that the SET pulse generated by the logic gate g propagates along the sensitization path and is latched by the latch l under a certain set of input vector v.

6) Judging whether there are particles with more energy bombarding the fault gate. If not, proceed to step 7); otherwise, use particles of the next energy to simulate fault injection, and proceed to step 3);

7) Determine whether there are more logic gates that may be bombarded by particles. If not, then proceed to step 8); otherwise, find the next fault door, and proceed to step 3);

8) Calculate the soft error rate of the circuit considering the NBTI effect. The overall calculation framework of the soft error rate is shown in Figure 4. The soft error rate calculation formula used in this step is as follows:

SER＝FP _comb ×R _EH ×R _PH ×A _comb ×3600×10 ⁹

Among them, R _EH and R _PH are the particle effective impact rate and the particle flux in the radiation environment, and the values are 2.2×10 ^-5 and 56.5m ^-2 s ^-1 respectively. A _comb is the sum of the areas of all logic gate units in the circuit.

9) Node soft error rate sorting.

Store the soft error rate and the corresponding node name in the linked list List or the mapping Map, and use the standard static template library STL algorithm to achieve efficient sorting of the node soft error rate.

The second step is to examine the inputs of all logic gates on the aging critical path, and replace the logic gates driving these inputs, so that the aging of the logic gates on the aging critical path is as small as possible. At the same time, the logic gates on the aging critical path are replaced by the gate size adjustment method, and the latches connected to the logic gates on the aging critical path are replaced by anti-SEU reinforcement means.

Visit each logic gate in the circuit in topological order. If a logic gate (denoted as G _aging ) is an aging key logic gate (a logic gate that directly affects the circuit delay), and when the output of its previous fan gate (denoted as G ₁ ) is "0", replace G ₁ for G ₁ '. If after the replacement, the sleep signal of the circuit can make the output of G ₁ ' become "1" when the circuit is idle, then record this replacement (that is, when the circuit is manufactured, the G ₁ logic gate should be replaced by G ₁ ' to manufacture); if the output of the replaced G ₁ ' is still "0" when the circuit is idle, try to replace all fan gates of G ₁ according to the type of G ₁ so that the output of G ₁ becomes "1", if If the requirement can be met, record all replaced logic gates, otherwise abandon all attempts at G _aging and consider the next logic gate of G _aging in the topological sequence.

In order to tolerate soft errors, during the above operations, the aging key logic gate G _aging is replaced by a larger-sized logic gate G _aging ' through the gate size adjustment method, so that the logic gates on the aging critical path can be weakened Even shield the SET transient fault pulse with a certain width, and record this replacement (that is, when the circuit is manufactured, the logic gate of G _aging should be manufactured with the replaced G _aging '). At the same time, replace the latch L _aging connected to the aging critical logic gate with the anti-SEU latch L _aging ', so that the latch connected to the aging critical logic gate is immune to SEU, and record this replacement (ie, When the circuit is manufactured, the L _aging latch should be manufactured with the replaced L _aging ').

The general idea of gate replacement to reduce aging caused by NBTI effect is to change the output of all aging-critical logic gates in the circuit to "1" as much as possible when the circuit is idle, so that the PMOS transistor is in a positive bias state and Reduces aging due to NBTI effects.

The general idea of gate replacement to tolerate soft errors is to make the critical charge of all aging critical logic gates in the circuit as large as possible when the circuit is working (it is also valid at idle), so that the SET transients generated by particle bombardment of aging critical logic gates The state fault pulse intensity should be as small as possible to tolerate a certain width of the SET pulse.

The general idea of latch replacement for soft error tolerance is to make latches connected to aging critical logic gates immune to SEU while the circuit is active (and also valid at idle).

The third step is to examine the logic gates on all timing-critical paths, and replace all logic gates on timing-critical paths with larger-sized logic gates, so that the logic gates on timing-critical paths can weaken or even shield a certain width of SET transients fault pulse; meanwhile, replace the latches connected to the logic gates on the timing-critical paths with SEU-resistant latches.

In order to tolerate soft errors, in the second step, when visiting each logic gate in the circuit according to the topological sequence, if a logic gate (denoted as G _timing ) is a timing-critical logic gate (which directly affects the circuit delay and except Aging key logic gates (logic gates other than G _aging ), the timing critical logic gate G _timing is replaced by a larger-sized logic gate G _timing ' through the gate size adjustment method, so that the logic gates on the timing critical path can be weakened or even shielded Width of the SET transient fault pulse, and record this replacement (that is, when the circuit is manufactured, the logic gate G _timing should be manufactured with the replaced G _timing '); at the same time, the latch connected to the timing critical logic gate Replace the latch L _timing with an SEU-resistant latch L _timing ' to make the latch connected to the timing-critical logic gate immune to SEU, and document this replacement (that is, at the time of circuit fabrication, the latch L _timing should be Manufactured with the replaced L _timing ').

The general idea of gate replacement and latch replacement for tolerating soft errors in this step is exactly the same as that for tolerating soft errors in the second step.

The fourth step is to replace the latch connected to the logic gate on the non-critical path with a latch that tolerates both SET and SEU.

In order to tolerate soft errors, in the third step, when visiting each logic gate in the circuit according to the topological sequence, if a logic gate (denoted as G _error ) is a soft error critical logic gate (except aging critical logic gate G _aging and timing critical logic gate G _timing ), replace the latch L _error connected to the soft error critical logic gate with a latch L _error that tolerates SET and SEU at the same time, so that the soft error critical logic gate The connected latch is not only immune to SEU, but also can weaken or even shield the SET transient fault pulse of a certain width propagating upstream, and record this replacement (that is, when the circuit is manufactured, the L _error latch should be manufactured with the replaced L _error ').

The anti-SEU latch L _aging 'structure used in the above steps is shown in Figure 5, and the latch used to tolerate SET and SEU at the same time is shown in Figure 6, and the integrated circuit that delays aging and tolerates soft errors is selectively hardened The overall process is shown in Figure 7.

Claims (4)

1. delaying aging tolerate the integrated circuit selective reinforcement means of soft error, is characterized in that: utilize computing machine to carry out design of Simulation to reference circuit, concrete steps are as follows:

Step (1): test signal topological sequences when described reference circuit being tested to described computer input;

Step (2): calculate the integrated circuit soft error rate considering negative bias thermal instability NBTI effect, finds out the logic gate set { G that soft error occurs _errorand there is the latch set { L of soft error _error, and by the logic gate set { G of described generation soft error _errorand the latch set { L of described generation soft error _errorelement sort from high to low according to the size of soft error rate;

Step (3): access each the NAND Logic door in described reference circuit in aging critical path by described topological sequence, i.e. aging key logic door G _aging, find out the described aging key logic door G directly affecting this reference circuit time delay _aging;

Step (4): judge in aging critical path, described aging key logic door G _agingprevious fan-in door G ₁output signal:

If: described previous fan-in door G ₁output be " 0 ",

Then: samely add sleep signal at input end replacement door G ₁' replace described previous fan-in door G ₁, and record all logic gates for replacing;

If: described previous fan-in door G ₁output be " 1 ",

Then: abandon the previous fan-in door G described in replacing ₁;

Step (5): the same replacement door G that PMOS/NMOS transistor width length geometric ratio is amplified _aging' replace aging key logic door G _aging, and record all logic gates for replacing;

Step (6): search described aging key logic door G _aginglatch set { the L connected _{aging_sub}, and the latch set { L described in judging _{aging_sub}character:

If: described latch set { L _{aging_sub}in comprise the latch reinforced;

Then: from described latch set { L _{aging_sub}in the latch reinforced of rejecting;

Step (7): the replacement latch L of same anti-single particle overturn SEU _aging' replace this latch set { L _agingelement, by this latch set { L _agingelement from the latch set { L of described generation soft error _errormiddle rejecting, and record all latchs for replacing;

Step (8): judge this aging key logic door G _agingwith the logic gate set { G that soft error occurs _errorrelation:

If: this aging key logic door G _agingfor there is the logic gate set { G of soft error _errorelement;

Then: from the logic gate set { G that soft error occurs _errormiddle this aging key logic door G of rejecting _aging, and access the aging key logic door G described in the next one _aging;

If: this aging key logic door G _agingnot for there is the logic gate set { G of soft error _errorelement,

Then: abandon the logic gate set { G from there is soft error _errormiddle this aging key logic door G of rejecting _aging, and the next described aging key logic door G of access _aging;

Step (9): access logic gate G that is in described reference circuit on sequential key path and that reinforce without door adjusted size method by described topological sequence _timing, find out the sequential key logic gate G directly affecting this reference circuit performance _timing;

Step (10): the same replacement door G that PMOS/NMOS transistor width length geometric ratio is amplified _timing' replace sequential key logic gate G _timing, and record all logic gates for replacing;

Step (11): search described sequential key logic gate G _timinglatch set { the L connected _timing, and the latch set { L described in judging _timingcharacter:

If: described latch set { L _timingin comprise the latch reinforced;

Then: from described latch set { L _timingin the latch reinforced of rejecting;

Step (12): the replacement latch L of same anti-SEU _timing' replace latch set { L _timingelement, by this latch set { L _timingelement from the latch set { L of described generation soft error _errormiddle rejecting, and record all latchs for replacing;

Step (13): judge this sequential key logic gate G _timingwith the logic gate set { G that soft error occurs _errorrelation:

If: this sequential key logic gate G _timingfor there is the logic gate set { G of soft error _errorelement,

Then: from the logic gate set { G that soft error occurs _errormiddle this sequential key of rejecting logic gate G _timing, and access the sequential key logic gate G described in the next one _timing;

If: this sequential key logic gate G _timingnot for there is the logic gate set { G of soft error _errorelement,

Then: abandon the logic gate set { G from there is soft error _errormiddle this sequential key of rejecting logic gate G _timing, and access the sequential key logic gate G described in the next one _timing;

Step (14): judge whether consolidation effect has reached the reliability objectives of integrated circuit (IC) design:

If: consolidation effect does not reach the reliability objectives of integrated circuit (IC) design,

Then: to soft error key logic door G _errorafter reinforcing, by this soft error key logic door G _errorfrom the logic gate set { G that soft error occurs _errormiddle rejecting, and access the soft error key logic door G described in the next one _error;

If: consolidation effect has reached the reliability objectives of integrated circuit (IC) design,

Then: stop strengthening flow process.

2. a kind of delaying aging according to claim 1 tolerate the integrated circuit selective reinforcement means of soft error, it is characterized in that: in step (4), for the replacement of not right and wrong door, if after replacing when circuit leaves unused described previous fan-in door G ₁output be still " 0 ", then attempt replacing G ₁all fan-in doors to make G ₁output become " 1 ", if still can not G be made ₁output become " 1 ", then do not replace G ₁.

3. a kind of delaying aging according to claim 1 tolerate the integrated circuit selective reinforcement means of soft error, is characterized in that: in step (14), for soft error key logic door G _errorreinforcement means, from the logic gate set { G of soft error occurs _errorin take out the highest logic gate G of soft error rate _{error_top}, the logic gate G that this soft error rate is the highest _{error_top}one be decided to be by described topological sequence access in described reference circuit in non-aging critical path, in non-sequential critical path, without door adjusted size method reinforce remaining logic gate G _error;

Search described soft error key logic door G _errorlatch set { the L connected _error, and the latch set { L described in judging _errorcharacter:

If: described latch set { L _errorin comprise the latch reinforced;

Then: from described latch set { L _errorin the latch reinforced of rejecting;

Now, described latch set { L _errorin do not comprise the latch reinforced, the replacement latch L of same tolerance SET and SEU _error' replace this latch set { L _errorelement, by this latch set { L _errorelement from the latch set { L of described generation soft error _errormiddle rejecting, and record all latchs for replacing.

4. a kind of delaying aging according to claim 1 tolerate the integrated circuit selective reinforcement means of soft error, it is characterized in that: in step (9), when the time sequence allowance of sequential critical path is less than the replacement latch L tolerating SET and SEU described in step (14) _error' time delay, do not reinforce by step (14), need be reinforced by step (10), (11), (12), (13), otherwise sequential occurs in violation of rules and regulations.