CN109669803A - For reducing the method and apparatus of the soft error rate of ECC memory - Google Patents
For reducing the method and apparatus of the soft error rate of ECC memory Download PDFInfo
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- CN109669803A CN109669803A CN201811442640.2A CN201811442640A CN109669803A CN 109669803 A CN109669803 A CN 109669803A CN 201811442640 A CN201811442640 A CN 201811442640A CN 109669803 A CN109669803 A CN 109669803A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
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Abstract
The present invention relates to the method and apparatus of the soft error rate for reducing ECC memory.A kind of method of soft error rate for reducing ECC memory is provided, this method comprises: obtaining the functional relation of the soft error rate of ECC memory；The initial value of the soft error rate of ECC memory is determined according to functional relation；Judge whether the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate；When the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate, the peripheral circuit of ECC memory is reinforced, so that the soft error rate of the ECC memory after reinforcing is less than or equal to goal-selling soft error rate.The above method can instruct the peripheral circuit soft fault preventing optimization design of ECC memory, by peripheral circuit Design of Reinforcement degree quantification, realize the purpose for not only having reduced overall soft error rate but also not reinforced excessively, guarantee that the soft error rate of ECC memory reaches Practical Project requirement.
Description
Technical field
The present invention relates to electronic reliability field, the soft error rate for reducing ECC memory is more particularly related to
Method and apparatus.
Background technique
The reason of soft error can occur during use for memory, generate soft error include radiating particle (α particle,
Neutron, proton, heavy ion etc.), random noise, problems of Signal Integrity, manufacture or design defect, the critical element etc..Occur soft
When mistake, the storage data that will lead to memory change, and influence the correctness of output data, and then cause to system work
It influences.
ECC (error correcting code) i.e. error correcting code, refers to and increases on the basis of original memory data position
Add some check bit, for detection and correcting soft errors.Most common ECC code first is that Hamming code, it can be achieved that correct one
Mistake, two bit-errors of detection are the function of " rectifying one and checking two ".ECC circuit is often used cooperatively with cross structure, refreshing, for disappearing
Except the soft error in memory.
The probability of soft error, storage rack occurs currently, there are some failure probabilities for ECC memory and having stored position
The research of relationship between structure, refreshing frequency and peripheral circuit sensibility, and lack the peripheral circuit for being effectively directed to ECC memory
Soft fault preventing optimum design method causes to face biggish failure risk when ECC memory engineer application, so that peripheral circuit is
No reinforcing and reinforcement degree do not have reasonable scientific basis.
Summary of the invention
Based on this, it is necessary to whether be reinforced for current peripheral circuit and reinforcement degree does not have asking for reasonable scientific basis
Topic, provides a kind of method of soft error rate for reducing ECC memory.
According to an aspect of the invention, there is provided a kind of method of the soft error rate for reducing ECC memory, the party
Method includes: to obtain the functional relation of the soft error rate of ECC memory, and the soft error rate of ECC memory is the storage of ECC memory
The sum of the soft error rate and the soft error rate of peripheral circuit of ECC memory in area；The soft of ECC memory is determined according to functional relation
The initial value of error rate；Judge whether the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate；Work as ECC
When the initial value of the soft error rate of memory is greater than goal-selling soft error rate, the peripheral circuit of ECC memory is reinforced,
So that the soft error rate of the ECC memory after reinforcing is less than or equal to goal-selling soft error rate.
The functional relation of the soft error rate of ECC memory is obtained in one of the embodiments, comprising: acquisition passes through number
Learn the functional relation of the soft error rate for the ECC memory being derived by.
The peripheral circuit of ECC memory includes EDAC circuit module in one of the embodiments,.
EDAC circuit module uses the Hamming code with rectifying one and checking two function as ECC code in one of the embodiments,
The functional relation of the soft error rate of the ECC memory of acquisition are as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, NEDACFor the equivalent sensitive storage bit number amount of peripheral circuit,
RbitFor the soft error rate of each sensitive storage position, TscrubIt is the refresh cycle of ECC memory, NwIt is the memory block of ECC memory
Number of words, NbRefer to the digit in single word, RrawFor memory block original soft error rate of the ECC memory when closing ECC function.
The soft error rate R of each sensitive storage position in one of the embodiments,bitECC function is being closed with ECC memory
The original soft error rate R in memory block when energyrawIt is equal.
The equivalent sensitive storage bit number amount N of peripheral circuit in one of the embodiments,EDACAre as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, RbitFor the soft error rate of each sensitive storage position, TscrubIt is
The refresh cycle of ECC memory, NwIt is the number of words of the memory block of ECC memory, NbRefer to the digit in single word.
The initial value of the soft error rate of ECC memory is determined according to functional relation in one of the embodiments, comprising:
Obtain memory block original soft error rate R of the ECC memory when closing ECC functionraw；Obtain the peripheral circuit of ECC memory
Equivalent sensitivity storage bit number amount NEDACWith the soft error rate R of each sensitive storage positionbit；Obtain the refresh cycle of ECC memory
TscrubWith the storage architecture of ECC memory, storage architecture includes the number of words N of the memory block of ECC memorywWith the position in single word
Number Nb；The parameter and functional relation that are obtained according to above-mentioned steps determine the initial value of the soft error rate of ECC memory.
In one of the embodiments, when the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate
When, the peripheral circuit of ECC memory is reinforced, comprising: when the initial value of the soft error rate of ECC memory is greater than default mesh
When marking soft error rate, reinforced using peripheral circuit of the triplication redundancy method to ECC memory.
In one of the embodiments, when the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate
When, the peripheral circuit of ECC memory is reinforced, comprising: when the initial value of the soft error rate of ECC memory is greater than default mesh
When marking soft error rate, the initial equivalent sensitive storage bit number amount of peripheral circuit is obtained；It is determined according to goal-selling soft error rate
The equivalent sensitive storage bit number amount of the equivalent sensitive storage bit number amount of the target of peripheral circuit, target is less than initial equivalent sensitivity
Storage bit number amount；And ECC is deposited according to the equivalent sensitive storage bit number amount of initial equivalent sensitive storage bit number amount and target
The peripheral circuit of reservoir is reinforced.
According to another aspect of the present invention, a kind of device of soft error rate for reducing ECC memory is provided, it should
Device includes: that functional relation obtains module, the functional relation of the soft error rate for obtaining ECC memory；Initial soft error rate
Determining module, the initial value of the soft error rate for determining ECC memory according to functional relation；Judgment module, for judging ECC
Whether the initial value of the soft error rate of memory is greater than goal-selling soft error rate；Module is reinforced, for working as the soft of ECC memory
When the initial value of error rate is greater than goal-selling soft error rate, the peripheral circuit of ECC memory is reinforced, so that reinforcing
The soft error rate of ECC memory afterwards is less than or equal to goal-selling soft error rate.
The method and apparatus of the above-mentioned soft error rate for reducing ECC memory obtain the soft error of ECC memory first
The functional relation of rate determines the initial value of the soft error rate of ECC memory according to functional relation, judges whether the initial value is greater than
Goal-selling soft error rate, if so, reinforcing to the peripheral circuit of memory, so that the ECC storage after reinforcing
The soft error rate of device is less than or equal to goal-selling soft error rate.The above method and device can instruct the periphery electricity of ECC memory
Road soft fault preventing optimization design, by peripheral circuit Design of Reinforcement degree quantification, realization had not only reduced overall soft error rate but also only
The purpose reinforced is spent, guarantees that the soft error rate of ECC memory reaches Practical Project requirement.
Detailed description of the invention
The preferred rather than embodiment of limitation of the invention will be described with reference to attached drawing by way of example, in which:
Fig. 1 is the flow chart of the method for the soft error rate for reducing ECC memory in one embodiment of the application；
Fig. 2 is the flow chart of the method for the soft error rate for reducing ECC memory in another embodiment of the application；
Fig. 3 is the flow chart of the method for the soft error rate for reducing ECC memory in the another embodiment of the application；
Fig. 4 is the schematic diagram of the device of the soft error rate for reducing ECC memory in one embodiment of the application.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.Many details are explained in the following description in order to fully understand this hair
It is bright.But the invention can be embodied in many other ways as described herein, those skilled in the art can be not
Similar improvement is done in the case where violating intension of the present invention, therefore the present invention is not limited to the specific embodiments disclosed below.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Each technical characteristic of above embodiments can carry out arbitrary group
It closes, for simplicity of description, combination not all possible to each technical characteristic in above-described embodiment is all described, however,
As long as there is no contradiction in the combination of these technical features, all should be considered as described in this specification.
This application provides a kind of methods of soft error rate for reducing ECC memory, as shown in Figure 1, this method packet
Include following steps:
Step S100 obtains the functional relation of the soft error rate of ECC memory.
Specifically, ECC memory refers to the memory with ECC function.In order to determine whether the periphery to ECC memory
The degree that circuit is reinforced and reinforced needs to obtain the functional relation of the soft error rate of ECC memory first.ECC storage
The soft error rate of device is the sum of soft error rate and soft error rate of peripheral circuit of ECC memory of the memory block of ECC memory.
Thus, in order to reduce the soft error rate of ECC memory, it can choose the soft error rate for reducing memory block and/or reduce periphery electricity
The soft error rate on road.The application reduces the soft error rate of ECC memory by reducing the soft error rate of peripheral circuit.
Step S200 determines the initial value of the soft error rate of ECC memory according to functional relation.
Specifically, after obtaining functional relation, the initial of the soft error rate of ECC memory is determined according to the functional relation
Value, i.e., the soft error rate of ECC memory when not reinforced to peripheral circuit.
Step S300, judges whether the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate.
Specifically, goal-selling soft error rate is the soft error rate for the ECC memory that expectation is realized, in order to determine whether to
Peripheral circuit is reinforced, needs whether the initial value for the soft error rate for first judging ECC memory is greater than goal-selling soft error
Accidentally rate.
Step S400 deposits ECC when the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate
The peripheral circuit of reservoir is reinforced, so that the soft error rate of the ECC memory after reinforcing is soft less than or equal to goal-selling
Error rate.
Specifically, when the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate, ECC is stored
The peripheral circuit of device is reinforced, so that the soft error rate of the peripheral circuit of ECC memory reduces, so that after reinforcing
The soft error rate of ECC memory reduces, and is less than or equal to goal-selling soft error rate.
The method of the above-mentioned soft error rate for reducing ECC memory, the first letter of the soft error rate of acquisition ECC memory
Number relationship, the initial value of the soft error rate of ECC memory is determined according to functional relation, judges whether the initial value is greater than default mesh
Soft error rate is marked, if so, reinforcing to the peripheral circuit of memory, so that ECC memory after reinforcing is soft
Error rate is less than or equal to goal-selling soft error rate.It is soft that the above method and device can instruct the peripheral circuit of ECC memory to resist
Mistake optimization design, by peripheral circuit Design of Reinforcement degree quantification, realization had not only reduced overall soft error rate but also had not reinforced excessively
Purpose, guarantee that the soft error rate of ECC memory reaches Practical Project requirement.
In one embodiment, the functional relation of the soft error rate of ECC memory is obtained, comprising: acquisition is pushed away by mathematics
The functional relation of the soft error rate for the ECC memory led.
Specifically, the functional relation of the soft error rate of ECC memory can be determined by way of mathematical derivation.At other
In embodiment, the functional relation of the soft error rate of the available ECC memory obtained by way of experiment.
In one embodiment, the peripheral circuit of ECC memory includes EDAC circuit module.Specifically, ECC memory
Peripheral circuit includes error detection and amendment (error detection and correction, EDAC) circuit module and other
Input/output control circuit (address decoder, I/O circuit, control circuit etc.).Wherein, the major function of EDAC circuit module is
ECC coding and decoding is carried out to storing data, is the soft error sensitive blocks in peripheral circuit.
In one embodiment, EDAC circuit module uses the Hamming code with rectifying one and checking two function as ECC code, obtains
ECC memory soft error rate functional relation are as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, NEDACFor the equivalent sensitive storage bit number amount of peripheral circuit,
RbitFor the soft error rate of each sensitive storage position, TscrubIt is the refresh cycle of ECC memory, NwIt is the memory block of ECC memory
Number of words, NbRefer to the digit in single word, RrawFor memory block original soft error rate of the ECC memory when closing ECC function.
Specifically, the soft error rate of the peripheral circuit of ECC memory is NEDAC·Rbit, the soft error rate of the memory block of ECC memory isOrThe soft error rate of ECC memory is periphery electricity
The sum of the soft error rate and the soft error rate of memory block on road.In other embodiments, EDAC circuit module is using other kinds of
Error correcting code, the principle of optimality of peripheral circuit soft error rate is identical as the principle of the embodiment of simple Hamming code, and simple Hamming
Code accounts for 90% of practical application or more, thus repeats no more.
In one embodiment, the soft error rate R of each sensitive storage positionbitWith ECC memory when closing ECC function
The original soft error rate R in memory blockrawIt is equal.
In one embodiment, the equivalent sensitive storage bit number amount N of peripheral circuitEDACAre as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, RbitFor the soft error rate of each sensitive storage position, TscrubIt is
The refresh cycle of ECC memory, NwIt is the number of words of the memory block of ECC memory, NbRefer to the digit in single word.Carrying out periphery
When circuit soft fault preventing optimization design, the soft error rate (R of ECC memory should be comprehensively consideredsystem), refresh cycle, memory block frame
Structure (NwAnd Nb) and the original soft error rate (R in memory blockbit), select the equivalent sensitive storage bit number amount N of suitable peripheral circuitEDAC。
In general, RsystemAEROSPACE APPLICATION engine request be 10-10Errors/bit/day, RsystemAviation and Ground Application engineering want
Asking generally can be lower, different because of concrete application, is described with FIT value, i.e., 109Working hours in occur mistake number.
Application demanding for soft error rate selects the equivalent sensitive storage bit number amount reduced, i.e. the periphery electricity of progress higher degree
Road solidification；Low application is required for soft error rate, selection drops high equivalent sensitive storage bit number amount, that is, carries out lower degree
Peripheral circuit solidification.Refresh cycle, memory block framework and the original soft error rate (R in memory blockraw) codetermine the soft of memory block
Error rate, the soft error rate of memory block are added to obtain the soft error rate of ECC memory with the soft error rate of peripheral circuit.Therefore,
The soft fault preventing optimization design of peripheral circuit should be required with the soft error rate of ECC memory (i.e. preset target soft error rate) and
The soft error rate level of memory block is foundation.When soft error rate when memory block is lower, it can choose higher equivalent sensitivity and deposit
Storage space quantity, i.e. the peripheral circuit solidification of progress lower degree；When soft error rate when memory block is higher, it should select lower
Equivalent sensitivity storage bit number amount, i.e. the peripheral circuit solidification of progress higher degree.
In one embodiment, as shown in Fig. 2, step S200, the soft error rate of ECC memory is determined according to functional relation
Initial value, comprising:
Step S210 obtains memory block original soft error rate R of the ECC memory when closing ECC functionraw。
Step S220 obtains the equivalent sensitive storage bit number amount N of the peripheral circuit of ECC memoryEDACIt is deposited with each sensitivity
The soft error rate R of storage spacebit。
Step S230 obtains the refresh cycle T of ECC memoryscrubWith the storage architecture of ECC memory, storage architecture packet
Include the number of words N of the memory block of ECC memorywWith the digit N in single wordb。
Step S240, the parameter and functional relation that are obtained according to above-mentioned steps determine the soft error rate of ECC memory
Initial value.
Specifically, the relevant parameter in the functional relation of the soft error rate of ECC memory is obtained first, comprising: memory block
Original soft error rate Rraw, equivalent sensitive storage bit number amount NEDACWith the soft error rate R of each sensitive storage positionbitAnd ECC is deposited
The refresh cycle T of reservoirscrubWith the storage architecture of ECC memory, ECC is then obtained according to the parameter of acquisition and functional relation and is deposited
The initial value of the soft error rate of reservoir, i.e., the soft error rate of ECC memory when not reinforced.
In one embodiment, step S400, when the initial value of the soft error rate of ECC memory is greater than goal-selling soft error
Accidentally when rate, the peripheral circuit of ECC memory is reinforced, comprising: when the initial value of the soft error rate of ECC memory is greater than in advance
If when target soft error rate, being reinforced using peripheral circuit of the triplication redundancy method to ECC memory.Triplication redundancy method is common
The method for being reinforced to peripheral circuit, wherein three modules are performed simultaneously identical operation, with most identical defeated
Out as the correct output of voting system, commonly referred to as two from three, as long as not occurring two identical mistakes in three modules simultaneously
Accidentally, the mistake of malfunctioning module can be masked off, guarantee system correctly exports.Since three modules are independent of each other, two
It is minimum probability event that module, which mistake occurs simultaneously, thus reduces the soft error rate of peripheral circuit, and then improving system can
By property.In other embodiments, it can adopt and the peripheral circuit of ECC memory is reinforced with other methods.
In one embodiment, as shown in figure 3, step S400, when the initial value of the soft error rate of ECC memory be greater than it is pre-
If when target soft error rate, being reinforced to the peripheral circuit of ECC memory, comprising: when ECC memory soft error rate just
When initial value is greater than goal-selling soft error rate,
Step S410 obtains the initial equivalent sensitive storage bit number amount of peripheral circuit.
Step S420 determines the equivalent sensitive storage bit number amount of the target of peripheral circuit according to goal-selling soft error rate,
The equivalent sensitive storage bit number amount of target is less than initial equivalent sensitive storage bit number amount.
Step S430, according to the equivalent sensitive storage bit number amount of initial equivalent sensitive storage bit number amount and target to ECC
The peripheral circuit of memory is reinforced.
Specifically, it when the initial value of the soft error rate of ECC memory is greater than goal-selling soft error rate, needs to ECC
The peripheral circuit of memory is reinforced.And the degree reinforced is needed according to the initial value of the soft error rate of ECC memory and pre-
If target soft error rate determines.Firstly, obtaining the initial equivalent sensitive storage bit number amount and and goal-selling of peripheral circuit
The equivalent sensitive storage bit number amount of the corresponding target of soft error rate, then according to initial equivalent sensitive storage bit number amount and target
Equivalent sensitive storage bit number amount the peripheral circuit of ECC memory is reinforced so that the peripheral circuit after reinforcing is equivalent
Sensitive storage bit number amount is less than or equal to the equivalent sensitive storage bit number amount of target, so that the ECC memory after reinforcing
Soft error rate is less than or equal to goal-selling soft error rate.
Present invention also provides a kind of devices of soft error rate for reducing ECC memory, as shown in figure 4, the device
It comprises the following modules:
Functional relation obtains module 100, the functional relation of the soft error rate for obtaining ECC memory；
Initial soft error rate determining module 200, for determined according to functional relation ECC memory soft error rate it is initial
Value；
Judgment module 300, for judging whether the initial value of soft error rate of ECC memory is greater than goal-selling soft error
Rate；
Reinforce module 400, for when the initial value of the soft error rate of ECC memory be greater than goal-selling soft error rate when,
The peripheral circuit of ECC memory is reinforced, is preset so that the soft error rate of the ECC memory after reinforcing is less than or equal to
Target soft error rate.
The device of the above-mentioned soft error rate for reducing ECC memory, the first letter of the soft error rate of acquisition ECC memory
Number relationship, the initial value of the soft error rate of ECC memory is determined according to functional relation, judges whether the initial value is greater than default mesh
Soft error rate is marked, if so, reinforcing to the peripheral circuit of memory, so that ECC memory after reinforcing is soft
Error rate is less than or equal to goal-selling soft error rate.It is soft that the above method and device can instruct the peripheral circuit of ECC memory to resist
Mistake optimization design, by peripheral circuit Design of Reinforcement degree quantification, realization had not only reduced overall soft error rate but also had not reinforced excessively
Purpose, guarantee that the soft error rate of ECC memory reaches Practical Project requirement.
In one embodiment, functional relation obtains module 100 and is specifically used for: obtaining the ECC obtained by mathematical derivation
The functional relation of the soft error rate of memory.
In one embodiment, the peripheral circuit of ECC memory includes EDAC circuit module.
In one embodiment, EDAC circuit module uses the Hamming code with rectifying one and checking two function as ECC code, obtains
ECC memory soft error rate functional relation are as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, NEDACFor the equivalent sensitive storage bit number amount of peripheral circuit,
RbitFor the soft error rate of each sensitive storage position, TscrubIt is the refresh cycle of ECC memory, NwIt is the memory block of ECC memory
Number of words, NbRefer to the digit in single word, RrawFor memory block original soft error rate of the ECC memory when closing ECC function.
In one embodiment, the soft error rate R of each sensitive storage positionbitWith ECC memory when closing ECC function
The original soft error rate R in memory blockrawIt is equal.
In one embodiment, the equivalent sensitive storage bit number amount N of peripheral circuitEDACAre as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, RbitFor the soft error rate of each sensitive storage position, TscrubIt is
The refresh cycle of ECC memory, NwIt is the number of words of the memory block of ECC memory, NbRefer to the digit in single word.
In one embodiment, initial soft error rate determining module 200 is specifically used for: obtaining ECC memory and is closing ECC
The original soft error rate R in memory block when functionraw；Obtain the equivalent sensitive storage bit number amount N of the peripheral circuit of ECC memoryEDAC
With the soft error rate R of each sensitive storage positionbit；Obtain the refresh cycle T of ECC memoryscrubWith the storage rack of ECC memory
Structure, storage architecture include the number of words N of the memory block of ECC memorywWith the digit N in single wordb；It is obtained according to above-mentioned steps
Parameter and functional relation determine the initial value of the soft error rate of ECC memory.
In one embodiment, it reinforces module 400 to be specifically used for: when the initial value of the soft error rate of ECC memory is greater than
When goal-selling soft error rate, reinforced using peripheral circuit of the triplication redundancy method to ECC memory.
In one embodiment, it reinforces module 400 to be specifically used for: when the initial value of the soft error rate of ECC memory is greater than
When goal-selling soft error rate, the initial equivalent sensitive storage bit number amount of peripheral circuit is obtained；According to goal-selling soft error
Rate determines the equivalent sensitive storage bit number amount of the target of peripheral circuit, and the equivalent sensitive storage bit number amount of target is less than initial etc.
Imitate sensitive storage bit number amount；And the equivalent sensitive storage bit number amount pair according to initial equivalent sensitive storage bit number amount and target
The peripheral circuit of ECC memory is reinforced.
Each technical characteristic of above embodiments can be combined arbitrarily, for simplicity of description, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, the combination of these technical characteristics be not present lance
Shield all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the concept of this application, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of method of the soft error rate for reducing ECC memory, which is characterized in that the described method includes:
The functional relation of the soft error rate of ECC memory is obtained, the soft error rate of the ECC memory is the ECC memory
Memory block soft error rate and the ECC memory the sum of the soft error rate of peripheral circuit；
The initial value of the soft error rate of the ECC memory is determined according to the functional relation；
Judge whether the initial value of the soft error rate of the ECC memory is greater than goal-selling soft error rate；
When the initial value of the soft error rate of the ECC memory is greater than the goal-selling soft error rate, the ECC is stored
The peripheral circuit of device is reinforced, so that the soft error rate of the ECC memory after reinforcing is less than or equal to the goal-selling
Soft error rate.
2. the method according to claim 1, wherein the function of the soft error rate for obtaining ECC memory closes
System, comprising:
Obtain the functional relation of the soft error rate of the ECC memory obtained by mathematical derivation.
3. the method according to claim 1, wherein the peripheral circuit of the ECC memory includes EDAC circuit
Module.
4. according to the method described in claim 3, it is characterized in that, the EDAC circuit module, which uses, has the function of rectifying one and checking two
Hamming code as ECC code, the functional relation of the soft error rate of the ECC memory of acquisition are as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, NEDACFor the equivalent sensitive storage bit number amount of the peripheral circuit, Rbit
For the soft error rate of each sensitive storage position, TscrubIt is the refresh cycle of the ECC memory, NwIt is the ECC memory
The number of words of memory block, NbRefer to the digit in single word, RrawFor memory block original soft error of the ECC memory when closing ECC function
Accidentally rate.
5. according to the method described in claim 4, it is characterized in that, the soft error rate R of each sensitive storage positionbitWith institute
State memory block original soft error rate R of the ECC memory when closing ECC functionrawIt is equal.
6. according to the method described in claim 5, it is characterized in that, the equivalent sensitive storage bit number amount N of the peripheral circuitEDAC
Are as follows:
Or
Wherein, RsystemFor the soft error rate of ECC memory, RbitFor the soft error rate of each sensitive storage position, TscrubIt is described
The refresh cycle of ECC memory, NwIt is the number of words of the memory block of the ECC memory, NbRefer to the digit in single word.
7. according to the method described in claim 4, it is characterized in that, described determine that the ECC is stored according to the functional relation
The initial value of the soft error rate of device, comprising:
Obtain memory block original soft error rate R of the ECC memory when closing ECC functionraw；
Obtain the equivalent sensitive storage bit number amount N of the peripheral circuit of the ECC memoryEDACWith the soft error of each sensitive storage position
Accidentally rate Rbit；
Obtain the refresh cycle T of the ECC memoryscrubWith the storage architecture of the ECC memory, the storage architecture includes
The number of words N of the memory block of ECC memorywWith the digit N in single wordb；
The parameter and the functional relation that are obtained according to above-mentioned steps determine the initial of the soft error rate of the ECC memory
Value.
8. method according to any one of claims 1-7, which is characterized in that the soft error when the ECC memory
When accidentally the initial value of rate is greater than goal-selling soft error rate, the peripheral circuit of the ECC memory is reinforced, comprising:
When the initial value of the soft error rate of the ECC memory is greater than goal-selling soft error rate, using triplication redundancy method pair
The peripheral circuit of the ECC memory is reinforced.
9. method according to any one of claims 1-7, which is characterized in that the soft error when the ECC memory
When accidentally the initial value of rate is greater than goal-selling soft error rate, the peripheral circuit of the ECC memory is reinforced, comprising: when
When the initial value of the soft error rate of the ECC memory is greater than goal-selling soft error rate,
Obtain the initial equivalent sensitive storage bit number amount of the peripheral circuit of the ECC memory；
The equivalent sensitive storage bit number amount of the target of the peripheral circuit, the mesh are determined according to the goal-selling soft error rate
The equivalent sensitive storage bit number amount of target is less than the initial equivalent sensitive storage bit number amount；And
The ECC is deposited according to the equivalent sensitive storage bit number amount of the initial equivalent sensitive storage bit number amount and the target
The peripheral circuit of reservoir is reinforced.
10. a kind of device of the soft error rate for reducing ECC memory, which is characterized in that described device includes:
Functional relation obtains module, the functional relation of the soft error rate for obtaining ECC memory；
Initial soft error rate determining module, for determined according to the functional relation ECC memory soft error rate just
Initial value；
Judgment module, for judging whether the initial value of soft error rate of the ECC memory is greater than goal-selling soft error rate；
Reinforce module, for when the initial value of the soft error rate of the ECC memory be greater than goal-selling soft error rate when, to institute
The peripheral circuit for stating ECC memory is reinforced, so that the soft error rate of the ECC memory after reinforcing is less than or equal to described
Goal-selling soft error rate.
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