CN106169949A - A kind of baseband signal bit synchronization clock wideband extracted in self-adaptive device and method - Google Patents
A kind of baseband signal bit synchronization clock wideband extracted in self-adaptive device and method Download PDFInfo
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- CN106169949A CN106169949A CN201610706012.5A CN201610706012A CN106169949A CN 106169949 A CN106169949 A CN 106169949A CN 201610706012 A CN201610706012 A CN 201610706012A CN 106169949 A CN106169949 A CN 106169949A
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- synchronization clock
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- 238000000034 method Methods 0.000 title claims description 18
- 238000001514 detection method Methods 0.000 claims abstract description 32
- 238000000605 extraction Methods 0.000 claims abstract description 23
- 238000007781 pre-processing Methods 0.000 claims abstract description 19
- 238000007493 shaping process Methods 0.000 claims abstract description 15
- 230000001360 synchronised effect Effects 0.000 claims abstract description 8
- 238000001914 filtration Methods 0.000 claims description 6
- 230000000630 rising effect Effects 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 4
- 239000010453 quartz Substances 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 238000007689 inspection Methods 0.000 claims 1
- 230000003044 adaptive effect Effects 0.000 abstract description 3
- 238000003708 edge detection Methods 0.000 abstract 1
- 238000004891 communication Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The present invention relates to a kind of baseband signal bit synchronization clock wideband extracted in self-adaptive device, including signal pre-processing module, the bit synchronization Clock Extraction module being connected with this signal pre-processing module.The invention still further relates to a kind of baseband signal bit synchronization clock wideband self-adaptation extraction method, the baseband signal of reception be amplified, filter, the pretreatment such as shaping, bit synchronization Clock Extraction is realized afterwards on FPGA or CPLD hardware platform, including: latch the baseband signal after shaping, signal edge detection, minimum pulse width detection and phase-detection, finally formed unit by lock-out pulse and complete the extraction of bit synchronization clock.The present invention is easily achieved, and adaptive tracing base-band signal frequency in the range of wider frequency dynamic, it is possible to extract bit synchronous clock signal quickly and accurately, the bit synchronous clock signal of generation is stable, phase jitter is little.
Description
Technical field
The present invention relates to communication system simultaneous techniques field, adaptive particularly to a kind of baseband signal bit synchronization clock wideband
Answer extraction element and method.
Background technology
Synchronizing have very important effect in a communications system, the quality of its performance directly affects the effective of communication system
Property and reliability.Wherein bit synchronization is also referred to as symbol synchronization, is to realize the most important condition that code element information is correctly recovered.
In digital communication systems, generally use phase locking technique to extract bit synchronization clock, typically shaken by high stable quartz crystal
Swing the part compositions such as device, frequency divider, phase comparator, pulse add-subtract control unit.This method needs priori, i.e. known code
Unit's speed, is determined the divide ratio of frequency divider by it, after chip rate adjusts, is difficult to again reach synchronous effect.
Summary of the invention
Present invention aims to above-mentioned chip rate adjust or adaptive synchronicity problem after change, utilize scun
Wide detection technique, improves existing phase locking technique, proposes a kind of baseband signal bit synchronization clock wideband based on FPGA/CPLD
Extracted in self-adaptive device and and method of work.
In order to solve above-mentioned technical problem, the invention provides a kind of baseband signal bit synchronization clock wideband extracted in self-adaptive
Device, including: signal pre-processing module, the bit synchronization Clock Extraction module being connected with this signal pre-processing module.
Further, described signal pre-processing module includes: amplifier module, filter module, shaping pulse module；Described
Signal pre-processing module is suitable to regenerate channel decay, filtering, the base-band data signal of noise jamming；Described amplifier module is fitted
In amplifying channel decay, filtering, the base-band data signal of noise jamming；Described filter module is adapted to filter out out-of-band noise,
Improve signal quality；Described shaping pulse module is suitable to be shaped as filter output signal low and high level signal, i.e. regenerates base
Tape pulse signal.
Further, described bit synchronization Clock Extraction module includes: system clock, latch units, Edge check, minimum pulse width
Detection, phase-detection, lock-out pulse are formed；Described bit synchronization Clock Extraction module is suitable to wideband extracted in self-adaptive Signal Pretreatment
The regenerated baseband data signal bits synchronised clock that module provides；The detection of described latch units, Edge check, minimum pulse width, phase place
Detection, lock-out pulse are formed and are connected with system clock respectively；Described system clock is suitable to quartz oscillator and produces high stable
Degree clock signal；Described latch units is suitable to the regenerated baseband signal after caching shaping, is allowed to Tong Bu with system clock；Described limit
It is adapted to detect for baseband signal rising edge and trailing edge along detection；Described minimum pulse width detection be suitable in wider frequency band range from
Adapt to the minimum pulse width of detection baseband signal, as the reference frame adjusting bit synchronization clock output frequency parameter；Described
Phase-detection is suitable to the rising edge/trailing edge signal calculating Edge check and forms, with lock-out pulse, the bit synchronization clock that unit produces
The phase contrast of signal, as the phase parameter reference frame adjusting the output of bit synchronization clock；Described lock-out pulse is formed and is suitable to root
Bit synchronous clock signal is produced according to phase contrast and minimum pulse width.
Another aspect, in order to solve same technical problem, present invention also offers a kind of baseband signal bit synchronization clock
Wideband extracted in self-adaptive method of work.
Described baseband signal bit synchronization clock wideband extracted in self-adaptive device, including: signal pre-processing module, with this signal
The bit synchronization Clock Extraction module that pretreatment module is connected.
Further, described signal pre-processing module is suitable to hardware and realizes, and described bit synchronization Clock Extraction module is suitable for use with
Hardware description language realizes based on FPGA or CPLD.Described method of work concrete steps include: (1) receives baseband signal and puts
Greatly；(2) according to base-band signal frequency scope selecting filter, the baseband signal of reception is filtered；(3) Zero-cross comparator shaping
For low and high level pulse signal；(4) on FPGA or CPLD hardware platform, bit synchronization clock extracted in self-adaptive is realized.
Further, FPGA or CPLD hardware platform realizes bit synchronization clock extracted in self-adaptive to include: (1) latches shaping
After baseband signal；(2) detection signal edge；(3) minimum pulse width detection, when minimum pulse width is less, uses equal precision measurement
Principle measures minimum pulse width；(4) phase difference detection；(5) unit is formed according to minimum pulse width and phase contrast by lock-out pulse
Complete the generation of bit synchronization clock.
The beneficial effects of the present invention is:
(1) use FPGA or CPLD hardware realize bit synchronization Clock Extraction, low cost, it is adaptable to miniature high-speed work time
Clock extracts circuit.
(2) according to chip rate from motion tracking minimum pulse width, self-adaptative adjustment divide ratio, quick lock in bit synchronization clock
Frequency and phase place.
(3), when chip rate is higher, use equal precision measurement principle from motion tracking minimum pulse width, minimum pulse width certainty of measurement
High.
Accompanying drawing explanation
The present invention is further described with embodiment below in conjunction with the accompanying drawings.
Fig. 1 is the theory diagram of the baseband signal bit synchronization clock wideband extracted in self-adaptive device embodiment 1 of the present invention；
Fig. 2 is the baseband signal bit synchronization clock wideband extracted in self-adaptive device embodiment 2 method of work flow process of the present invention
Figure.
Detailed description of the invention
The present invention is further detailed explanation below in conjunction with the accompanying drawings.These accompanying drawings are the schematic diagram of simplification, only with
The basic structure of the illustration explanation present invention, therefore it only shows the composition relevant with the present invention.
Embodiment 1
Fig. 1 is the theory diagram of the baseband signal bit synchronization clock wideband extracted in self-adaptive device of the present invention.
As it is shown in figure 1, a kind of baseband signal bit synchronization clock wideband extracted in self-adaptive device of the present invention, including: signal
Pretreatment module, the bit synchronization Clock Extraction module being connected with this signal pre-processing module.
Specifically, described signal pre-processing module includes: amplifier module, filter module, shaping pulse module；Described
Signal pre-processing module is suitable to regenerate channel decay, filtering, the base-band data signal of noise jamming；Described amplifier module is fitted
In amplifying channel decay, filtering, the base-band data signal of noise jamming；Described filter module is adapted to filter out out-of-band noise,
Improve signal quality；Described shaping pulse module is suitable to be shaped as filter output signal low and high level signal, i.e. regenerates base
Tape pulse signal.
Further, described bit synchronization Clock Extraction module includes: system clock, latch units, Edge check, minimum pulse width
Detection, phase-detection, lock-out pulse are formed；Described bit synchronization Clock Extraction module is suitable to wideband extracted in self-adaptive Signal Pretreatment
The regenerated baseband data signal bits synchronised clock that module provides；The detection of described latch units, Edge check, minimum pulse width, phase place
Detection, lock-out pulse are formed and are connected with system clock respectively；Described system clock is suitable to quartz oscillator and produces high stable
Degree clock signal；Described latch units is suitable to the regenerated baseband signal after caching shaping, is allowed to Tong Bu with system clock；Described limit
It is adapted to detect for baseband signal rising edge and trailing edge along detection；Described minimum pulse width detection be suitable in wider frequency band range from
Adapt to the minimum pulse width of detection baseband signal, as the reference frame adjusting bit synchronization clock output frequency parameter；Described
Phase-detection is suitable to the rising edge/trailing edge signal calculating Edge check and forms, with lock-out pulse, the bit synchronization clock that unit produces
The phase contrast of signal, as the phase parameter reference frame adjusting the output of bit synchronization clock；Described lock-out pulse is formed and is suitable to root
Bit synchronous clock signal is produced according to phase contrast and minimum pulse width.
Embodiment 2
On the basis of embodiment 1, present invention also offers a kind of baseband signal bit synchronization clock wideband extracted in self-adaptive work
Making method, wherein said baseband signal bit synchronization clock wideband extracted in self-adaptive device includes: signal pre-processing module, with this letter
The bit synchronization Clock Extraction module that number pretreatment module is connected.
Further, the specific implementation process of a kind of baseband signal bit synchronization clock wideband extracted in self-adaptive method of work is such as
Under:
Fig. 2 shows the method for work flow process of the baseband signal bit synchronization clock wideband extracted in self-adaptive device of the present invention
Figure.
(1) receive baseband signal to amplify；
(2) according to base-band signal frequency scope selecting filter, the baseband signal of reception is filtered；
(3) Zero-cross comparator is shaped as low and high level pulse signal；
(4) on FPGA or CPLD hardware platform, bit synchronization clock extracted in self-adaptive is realized.
Further, FPGA or CPLD hardware platform realizes bit synchronization clock extracted in self-adaptive to include:
(1) baseband signal after shaping is latched；
(2) detection signal edge；
(3) minimum pulse width detection；
(4) phase difference detection；
(5) formed unit by lock-out pulse and complete the generation of bit synchronization clock according to minimum pulse width and phase contrast.
With the above-mentioned desirable embodiment according to the present invention for enlightenment, by above-mentioned description, relevant staff is complete
Entirely can carry out various change and amendment in the range of without departing from this invention technological thought.The technology of this invention
The content that property scope is not limited in description, it is necessary to determine its technical scope according to right.
Claims (5)
1. a baseband signal bit synchronization clock wideband extracted in self-adaptive device, it is characterised in that including:
Signal pre-processing module, the bit synchronization Clock Extraction module being connected with this signal pre-processing module.
Baseband signal bit synchronization clock wideband extracted in self-adaptive device the most according to claim 1, it is characterised in that
Described signal pre-processing module includes: amplifier module, filter module, shaping pulse module；
Described signal pre-processing module is suitable to regenerate channel decay, filtering, the base-band data signal of noise jamming；
Described amplifier module is suitable to amplify channel decay, filtering, the base-band data signal of noise jamming；
Described filter module is adapted to filter out out-of-band noise, improves signal quality；
Described shaping pulse module is suitable to be shaped as filter output signal low and high level signal, i.e. regenerated baseband pulse letter
Number.
Baseband signal bit synchronization clock wideband extracted in self-adaptive device the most according to claim 1, it is characterised in that
Described bit synchronization Clock Extraction module includes: the detection of system clock, latch units, Edge check, minimum pulse width, phase place inspection
Survey, lock-out pulse is formed；
Described bit synchronization Clock Extraction module is suitable to the regenerated baseband data that wideband extracted in self-adaptive signal pre-processing module provides
Signal bit synchronization clock；
The detection of described latch units, Edge check, minimum pulse width, phase-detection, lock-out pulse formed respectively with system clock phase
Even；
Described system clock is suitable to quartz oscillator and produces high stability clock signal；
Described latch units is suitable to the regenerated baseband signal after caching shaping, is allowed to Tong Bu with system clock；
Described Edge check is adapted to detect for baseband signal rising edge and trailing edge；
The detection of described minimum pulse width is suitable to the minimum pulse width of self-adapting detecting baseband signal in wider frequency band range, makees
For adjusting the reference frame of bit synchronization clock output frequency parameter；
Described phase-detection is suitable to the rising edge/trailing edge signal calculating Edge check and forms, with lock-out pulse, the position that unit produces
The phase contrast of synchronizing clock signals, as the phase parameter reference frame adjusting the output of bit synchronization clock；
Described lock-out pulse is formed and is suitable to produce bit synchronous clock signal according to phase contrast and minimum pulse width.
4. a baseband signal bit synchronization clock wideband self-adaptation extraction method, it is characterised in that
Described baseband signal bit synchronization clock wideband extracted in self-adaptive device, including: signal pre-processing module, locate in advance with this signal
The bit synchronization Clock Extraction module that reason module is connected.
Baseband signal bit synchronization clock wideband self-adaptation extraction method the most according to claim 4, including:
Described signal pre-processing module is suitable to hardware and realizes, and described bit synchronization Clock Extraction module is suitable for use with hardware description language
Realizing based on FPGA or CPLD, groundwork method includes: receives baseband signal and amplifies；Choose according to base-band signal frequency scope
Wave filter, is filtered the baseband signal of reception；Zero-cross comparator is shaped as low and high level pulse signal；Afterwards at FPGA or
Realize bit synchronization Clock Extraction on CPLD hardware platform, farther include: latch the baseband signal after shaping, detect signal limit
Edge, carries out minimum pulse width detection and phase difference detection simultaneously, when minimum pulse width is less, uses equal precision measurement principle to measure
Little pulsewidth, is finally formed unit by lock-out pulse and completes the generation of bit synchronization clock according to minimum pulse width and phase contrast.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107483170A (en) * | 2017-07-14 | 2017-12-15 | 天津大学 | A kind of binary baseband signal bit synchronization Clock Extraction and digital display method |
| CN111130534A (en) * | 2019-12-20 | 2020-05-08 | 钜泉光电科技(上海)股份有限公司 | Buffer circuit and crystal oscillator circuit |
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| CN102611447A (en) * | 2012-03-26 | 2012-07-25 | 东北大学 | Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array) |
| CN102904849A (en) * | 2011-07-25 | 2013-01-30 | 苏州东奇信息科技有限公司 | Burst communication system utilizing transient peak energy |
| CN104111481A (en) * | 2014-07-30 | 2014-10-22 | 桂林电子科技大学 | Synchronous clock phase difference measuring system and method |
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2016
- 2016-08-22 CN CN201610706012.5A patent/CN106169949B/en active Active
Patent Citations (4)
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|---|---|---|---|---|
| US6272441B1 (en) * | 1998-10-12 | 2001-08-07 | Peter Peyerl | Method for determining the pulse response of a broad band linear system and a measuring circuit for carrying out the method |
| CN102904849A (en) * | 2011-07-25 | 2013-01-30 | 苏州东奇信息科技有限公司 | Burst communication system utilizing transient peak energy |
| CN102611447A (en) * | 2012-03-26 | 2012-07-25 | 东北大学 | Noise adding signal synchronization clock extraction device based on FPGA (field programmable gate array) |
| CN104111481A (en) * | 2014-07-30 | 2014-10-22 | 桂林电子科技大学 | Synchronous clock phase difference measuring system and method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107483170A (en) * | 2017-07-14 | 2017-12-15 | 天津大学 | A kind of binary baseband signal bit synchronization Clock Extraction and digital display method |
| CN111130534A (en) * | 2019-12-20 | 2020-05-08 | 钜泉光电科技(上海)股份有限公司 | Buffer circuit and crystal oscillator circuit |
| CN111130534B (en) * | 2019-12-20 | 2024-03-01 | 钜泉光电科技(上海)股份有限公司 | Buffer circuit and crystal oscillator circuit |
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Effective date of registration: 20231204 Address after: 213, Block A, Maker Service Center, No. 1, Xihu Road, Wujin National High-tech Industrial Development Zone, Changzhou City, Jiangsu Province, 213000 Patentee after: JIANGSU LAITE BEIDOU INFORMATION TECHNOLOGY CO.,LTD. Address before: 213001, No. 1801, Wu Cheng Road, bell tower, Changzhou, Jiangsu Patentee before: JIANGSU University OF TECHNOLOGY |