WO2022077775A1

WO2022077775A1 - Eye diagram oscilloscope system and an eye diagram testing method

Info

Publication number: WO2022077775A1
Application number: PCT/CN2020/140579
Authority: WO
Inventors: 胡帅帅; 赵建中; 李智
Original assignee: 中国科学院微电子研究所
Priority date: 2020-10-13
Filing date: 2020-12-29
Publication date: 2022-04-21
Also published as: CN112462121A; CN112462121B

Abstract

Disclosed in the content of the present disclosure are an eye diagram oscilloscope system and an eye diagram testing method. The system comprises an equalizer (1), a clock data recovery circuit (2) and an eye diagram oscilloscope (3); after an input signal is adjusted by the equalizer (1), clock information for the clock data recovery circuit (2) to recover the input signal input is inputted, and the clock information and the input signal are inputted into the eye diagram oscilloscope (3); the eye diagram oscilloscope (3) comprises an algorithm logic module (31), a first phase interpolator (32) and a first sampler (33); and the algorithm logic module (31) controls an output clock of the first phase interpolator (32) to traverse N phases, and controls the threshold voltage of the first sampler (33) to traverse M voltage values, thereby testing the bit error rate under each phase and each voltage value, and obtaining an eye diagram of M*N test points. The systems and methods of some embodiments of the content of the present disclosure solve the technical problem of high signal testing costs in the prior art.

Description

An eye-diagram oscilloscope system and an eye-diagram testing method

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed on October 13, 2020, with the application number of 202011092482.X and the title of "An eye-diagram oscilloscope system and an eye-diagram testing method", the entire contents of which are incorporated herein by reference .

technical field

The present disclosure relates to the field of testing, and in particular, to an eye pattern oscilloscope system and an eye pattern testing method.

Background technique

In the field of high-speed serial interface, the signal needs to go through packages, connectors, through holes and circuit board copper wires from the transmitter to the receiver. These non-ideal factors can introduce inter-symbol interference and deteriorate the signal quality.

The quality of the current test signal mainly uses a high-speed real-time oscilloscope, which is relatively expensive and requires the support of other configurations such as circuit boards. And the test effect needs to be improved.

SUMMARY OF THE INVENTION

In order to solve the defects of the prior art, the present disclosure provides an eye pattern oscilloscope system and an eye pattern testing method.

In a first aspect, the present disclosure provides an eye-diagram oscilloscope system including an equalizer, a clock data recovery circuit, and an eye-diagram oscilloscope, wherein an input signal input to the eye-diagram oscilloscope system is adjusted by the equalizer and then input to the clock data recovery circuit; the clock data recovery circuit recovers the clock information of the input signal, and inputs the clock information and the input signal into the eye-diagram oscilloscope; the eye-diagram oscilloscope includes an algorithm a logic module, a first phase interpolator and a first sampler; after receiving the clock information and the input signal, the algorithm logic module controls the output clock of the first phase interpolator to traverse N phases, and controls the The threshold voltage of the first sampler traverses M voltage values, so as to test the bit error rate of the input signal sampled by the first sampler under each of the phases and each of the voltage values, to obtain M*N tests The eye diagram of the point, N and M are positive integers.

In one or more embodiments, the eye diagram oscilloscope system further includes an external interface, which is connected to the algorithm logic module and receives the eye diagram output by the algorithm logic module; the external interface is further used to adjust N and the value of M.

In one or more embodiments, N is 16 and M is 8.

In one or more embodiments, the eye-diagram oscilloscope system further includes: a phase-locked loop that provides an initial clock for the clock recovery circuit and the eye-diagram oscilloscope.

In a second aspect, the present disclosure further provides an eye pattern testing method, the method being applied to the system of the first aspect, comprising: after the equalizer adjusts the input signal, input to the clock data recovery circuit; the clock data recovery circuit recovers the clock information of the input signal, and inputs the clock information and the input signal into the eye-diagram oscilloscope; the eye-diagram oscilloscope After receiving the clock information and the input signal, the algorithm logic module controls the output clock of the first phase interpolator to traverse N phases, and controls the threshold voltage of the first sampler to traverse M voltage values, thereby testing The first sampler samples the bit error rate of the input signal at each of the phases and each of the voltage values to obtain an eye diagram of M*N test points, where N and M are both positive integers.

In one or more embodiments, the test points in the eye diagram are hollow dots to indicate that the bit error rate meets requirements, and the test points in the eye diagram are solid dots to indicate that the bit error rate does not meet the requirements Require.

In one or more embodiments, before inputting the clock information and the input signal into the eye-diagram oscilloscope, the method further includes: the clock-data recovery circuit removes traceable jitter components within a part of the loop bandwidth.

In one or more embodiments, the eye diagram testing method further includes: setting the equalizer to a plurality of equalization coefficients, and executing the method of claim 5 under each equalization coefficient to obtain a corresponding plurality of M*N eye diagrams of the multiple test points; determining a target equalization coefficient of the equalizer according to the eye diagrams of the multiple M*N test points.

In one or more implementation manners, the determining the target equalization coefficient of the equalizer according to the eye diagrams of the multiple M*N test points includes: The equalization coefficient corresponding to the eye diagram with the largest eye opening degree of the eye diagram is determined as the target equalization coefficient.

In one or more embodiments, the eye diagram testing method further includes: setting the jitter frequency to a plurality of jitter frequency values; maintaining each of the jitter frequency values and gradually increasing the jitter amplitude of the input signal; When the oscilloscope detects that the bit error rate of the input signal does not meet the preset requirements, it records the over-standard jitter amplitude at that time; according to the multiple over-standard jitter amplitude values corresponding to the multiple jitter frequency values, obtain Graph the jitter tolerance curve of the receiver connected to the oscilloscope.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present disclosure more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only the embodiments of the present disclosure. , for those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without any creative effort.

1 is a structural diagram of an eye-diagram oscilloscope system according to one or more embodiments of the present disclosure;

2 is a flowchart of an eye-diagram testing method according to one or more embodiments of the present disclosure;

3 is a schematic diagram of an eye diagram according to one or more embodiments of the present disclosure.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions/layers with different shapes, sizes, relative positions can be additionally designed as desired.

In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with specific implementations. For the definition of the technical solutions of the present application, the embodiments of the present application and the technical features in the embodiments may be combined with each other unless there is a conflict.

According to an aspect of the present disclosure, an eye-diagram oscilloscope system is provided, as shown in FIG. 1 , including:

Equalizer 1, clock data recovery circuit 2 and eye diagram oscilloscope 3;

The input signal input to the eye-diagram oscilloscope system is adjusted by the equalizer 1 and then input to the clock data recovery circuit 2; the clock data recovery circuit 2 recovers the clock information of the input signal, and converts the The clock information and the input signal are input into the eye diagram oscilloscope 3;

The eye diagram oscilloscope 3 includes an algorithm logic module 31, a first phase interpolator 32 and a first sampler 33;

Wherein, after receiving the clock information and the input signal, the algorithm logic module 31 controls the output clock of the first phase interpolator 32 to traverse N phases, and controls the threshold voltage of the first sampler 33 to traverse M voltage values, so as to test the bit error rate of the input signal sampled by the first sampler 33 under each phase and each voltage value, and obtain eye diagrams of M*N test points, N and M All are positive integers.

In the specific implementation process, the eye pattern oscilloscope system is an on-chip system, which is used to test the quality of the eye pattern corresponding to the input signal after the transmitter passes through the channel, and can also be used to test the overall performance of the receiver (by adding jitter to the input data). , voltage noise and other non-ideal factors to obtain the stress eye diagram, test the bit error rate of the receiver, and get the receiver jitter tolerance curve), and adjust the equalizer coefficient through the eye diagram test result feedback to improve the receiver bit error rate performance , and the specific usage will be described in the subsequent method examples, which are not limited here. This on-chip eye diagram oscilloscope is suitable for a wide data rate range, the bandwidth of the clock data recovery circuit is adjustable, and it is compatible with a variety of serial protocols. In some embodiments, the algorithm logic module 31 can be used to adjust the phase and threshold voltage of data samples, test the bit error rate, record eye diagram information, and adjust the equalizer coefficients. The first phase interpolator 32 performs phase interpolation on the output clock of the phase-locked loop. Preferably, it can obtain 16 equally divided sampling clocks by interpolation. The first sampler 33 samples the data, and the determined threshold voltage can be adjusted. The eye pattern oscilloscope system utilizes the clock information of the clock data recovery circuit 2 to adjust the sampling clock of the first phase interpolator 32 horizontally and the decision threshold voltage of the first sampler 33 vertically during data sampling, so that the entire eye pattern is analyzed Scan, record the bit error rate of each point, count all points that meet the bit error rate requirements, construct the eye diagram of the input data, and obtain the eye opening information. According to the eye opening information, the performance of the transmitter and receiver can be determined and adjusted Equalization coefficients for the equalizer.

The eye-diagram oscilloscope system can be independent of the receiver system, working when testing the eye-diagram or finding the best equalizer coefficients, and can be powered down in other cases to reduce power consumption.

The eye-diagram oscilloscope system may further include: a phase-locked loop, which provides an initial clock for the clock recovery circuit 2 and the eye-diagram oscilloscope 3 .

In some embodiments, the clock information of the clock data recovery circuit 2 can be used to remove the jitter that can be traced by part of the clock data loop, which is closer to the data eye diagram seen when the receiver samples in practical applications. At the same time, the clock data recovery loop The bandwidth of the path can be adjusted. Of course, when testing the eye diagram of the input signal, clock data recovery may not be used, and the complete jitter information of the input data is retained in the eye diagram test result. That is, the clock recovery using or not using the input data can be realized by selecting whether to use the clock recovery information in the clock data recovery circuit 2 .

The eye diagram oscilloscope system may further include: an external interface, which is connected to the algorithm logic module and receives the eye diagram output by the algorithm logic module; the external interface is further used to adjust the values of N and M.

In some embodiments, N may be 16 and M may be 8. That is, when sampling, the clocks of 16 phases are scanned horizontally, and the threshold voltages of 8 samples are scanned vertically. The bit error rate is used to judge whether the eyes of each sampling point are open, and the entire two-dimensional eye pattern lattice is traversed to construct the eye pattern information. In some embodiments, the 16-phase lateral clock during sampling is generated by the first phase interpolator 32, which has the same function as the phase interpolator in the clock data recovery circuit 2, and the interpolated phase number can also be obtained by external The interface is configured to 32 or 64, which requires a trade-off between test time and test accuracy. The eight sampling threshold voltages during sampling are generated by the first sampler 33. Due to the influence of non-ideal factors in circuit design and processing, the differential threshold voltage of the sampler itself may not be 0. Before the eye diagram test, the sampler mismatch can be passed first. The correction circuit eliminates the mismatch, and then the test is performed. The number of sampling threshold voltages can be configured to 32, 64 or 128 through the external interface, which requires a trade-off between test time and test accuracy.

According to another aspect of the present disclosure, an eye-diagram testing method is also provided, and the method is applied to the aforementioned eye-diagram oscilloscope system, as shown in FIG. 2 , including:

Step S201, after the equalizer 1 adjusts the input signal, the input signal is input to the clock data recovery circuit 2;

Step S202, the clock data recovery circuit 2 recovers the clock information of the input signal, and inputs the clock information and the input signal into the eye-diagram oscilloscope 3;

Step S203, after receiving the clock information and the input signal, the algorithm logic module in the eye diagram oscilloscope 3 controls the output clock of the first phase interpolator to traverse N phases, and controls the first phase interpolator to traverse N phases. The threshold voltage of the sampler traverses M voltage values, so as to test the bit error rate of the input signal sampled by the first sampler under each of the phases and each of the voltage values, to obtain the M*N test points. Eye diagram, N and M are positive integers.

In some embodiments, the test points in the eye diagram are hollow dots to indicate that the bit error rate meets the requirements, and the test points in the eye diagram are solid circles to indicate that the bit error rate does not meet the requirements. Preferably, the bit error rate is set to be less than 10 ^-12 to meet the requirements. Of course, other values can also be set, which are not limited here.

In some embodiments, when the system is used to determine the performance of the transmitter, or to determine whether the equalization coefficient set by the equalizer 1 is reasonable, the following method is used: test the eye diagram of the output signal of the transmitter, if the transmitter and the on-chip The eye-diagram oscilloscope system is on the same chip, and the signal connection can be made on the chip, and of course, the signal connection can be made through the channel on the off-chip circuit board, which is not limited here. When the signal from the transmitter enters the receiver, it goes through the equalizer 1 to improve the signal quality, and then enters the clock data recovery circuit 2 to recover a proper clock for sampling at the center of the eye diagram. The output of the digital filter in the clock data recovery circuit 2 contains clock information, which is simultaneously input to the eye diagram oscilloscope for clock recovery when testing the eye diagram, removing traceable jitter components in part of the loop bandwidth, and obtaining more accurate information. True eye diagram information. After the clock recovery information of the filter is input to the algorithm logic module 31, the algorithm logic module 31 performs mathematical operations, and then controls the first phase interpolator 32 so that the phase of the output clock is at the first phase. At the same time, the threshold voltage of the first sampler 33 is adjusted, and all 8 threshold voltage values are traversed. The algorithm logic module 31 receives the data output from the first sampler 33, performs detection at the same time, records the number of bit errors, and calculates the bit error rate. The bit error rate at each voltage is counted while traversing all voltage thresholds. Then adjust the output clock of the phase interpolator to the second phase, continue to traverse 8 threshold voltages, and record the bit error rate under each voltage. Repeat the previous operation until all 16 phases are traversed, so that the bit error rate of all two-dimensional lattices in the eye diagram is tested, and the eye diagram shown in Figure 3 is obtained, where the point that meets the bit error rate requirement is hollow Circle, the point that does not meet the bit error rate requirement is a solid circle, so that the eye diagram of the input signal is obtained, the hollow circle in the middle is the eye opening, which can be compared with the corresponding eye diagram template, or the eye diagram can be tested. The eye opening and eye width can determine the performance of the transmitter, or determine whether the equalization coefficient set by the equalizer 1 is reasonable.

In some embodiments, when the system is used to adaptively adjust the equalization coefficients of the equalizer, the following manner is adopted: the equalizer is set to a plurality of equalization coefficients, and steps S201-S203 are performed under each equalization coefficient, The eye diagrams of the corresponding multiple M*N test points are obtained, and then the target equalization coefficient of the equalizer is determined according to the eye diagrams of the multiple M*N test points. That is, adjust different equalization coefficients, test the eye opening and eye width of the eye diagrams under the coefficients, and determine the equalization coefficient corresponding to the eye diagram with the largest eye opening degree of the eye diagrams of the multiple M*N test points as the target equalization coefficient.

In a specific implementation process, the eye diagram with the largest eye opening degree may be the eye diagram with the largest product of the eye height and the eye width, or the eye diagram with the largest eye height and eye width. The corresponding determined target equalization coefficient is the best coefficient to adapt to the current channel environment. After the equalization coefficient of equalizer 1 is set to the target equalization coefficient, the eye diagram oscilloscope can be turned off to reduce power consumption.

In some embodiments, when the system is used to test the performance of the receiver, the following method is adopted: the jitter frequency is set to a plurality of jitter frequency values, each of the jitter frequency values is maintained, and the jitter of the input signal is gradually increased until the eye pattern oscilloscope 3 detects that the bit error rate of the input signal does not meet the preset requirement, and records the current exceeding jitter amplitude. According to a plurality of out-of-standard jitter amplitude values corresponding to the plurality of jitter frequency values, a jitter tolerance curve representing the receiver connected to the eye-pattern oscilloscope is obtained. That is, the function of the system to test the bit error rate is used, and the sampling phase and threshold voltage are not adjusted. The fixed jitter frequency gradually increases the jitter amplitude of the input signal until the receiver does not meet the bit error rate requirements, and the amplitude of the jitter value is recorded. Change the dither frequency and continue with the previous operation. This yields the receiver's jitter tolerance curve.

The technical solutions in the above embodiments of the present application have at least the following technical effects or advantages:

In the eye-diagram oscilloscope system and the eye-diagram testing method provided by the embodiments of the present application, on the one hand, the output of the clock data recovery circuit includes clock information, and the information is input to the eye-diagram oscilloscope, so that the clock information can be used to remove part of the loop when testing the eye-diagram. Jitter components that can be tracked within the bandwidth to get more realistic eye diagram information. On the other hand, the algorithm logic module is set for traversal to obtain multi-point distribution eye diagrams of different phases and different threshold voltages, which can more comprehensively characterize the signal quality. No expensive high-speed real-time oscilloscope and bit error tester are required, and the requirements for the test environment are relatively low, so the cost is low and the flexibility is high. Compared with the real-time oscilloscope, the present invention is more economical, convenient and flexible, and has higher precision.

In the eye-diagram oscilloscope system and the eye-diagram testing method provided by the embodiments of the present application, the input signal input to the eye-diagram oscilloscope system is set, and after being adjusted by the equalizer, it is input to the clock data recovery circuit; the clock information of the input signal, and input the clock information and the input signal into the eye-diagram oscilloscope; after receiving the clock information and the input signal, the algorithm logic module controls the first phase interpolator to output a clock Traverse N phases, and control the threshold voltage of the first sampler to traverse M voltage values, so as to test the error of sampling the input signal by the first sampler under each phase and each voltage value code rate to obtain the eye diagram of M*N test points. On the one hand, the output of the clock data recovery circuit contains clock information, which is input to the eye-diagram oscilloscope, so that the clock information can be used in the eye-diagram test to remove the traceable jitter component in part of the loop bandwidth and obtain more real eye-diagram information. . On the other hand, set the algorithm logic module to traverse to obtain multi-point distribution eye diagrams of different phases and different threshold voltages, and more comprehensively characterize the signal quality. No expensive high-speed real-time oscilloscope and bit error tester are required, and the requirements for the test environment are relatively low, so the cost is low and the flexibility is high. Compared with the real-time oscilloscope, the present disclosure is more economical, convenient and flexible, and has higher precision.

In the above description, technical details such as the composition and design of each layer have not been described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. Additionally, although the various embodiments have been described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

It will be apparent to those skilled in the art that various changes and modifications can be made to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, provided that such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to cover such modifications and variations.

Claims

An eye diagram oscilloscope system includes:

Equalizer, clock data recovery circuit and eye diagram oscilloscope;

The input signal input to the eye-diagram oscilloscope system is adjusted by the equalizer and then input to the clock data recovery circuit; the clock data recovery circuit recovers the clock information of the input signal, and converts the clock information to the clock data recovery circuit. and the input signal into the eye-diagram oscilloscope;

The eye diagram oscilloscope includes an algorithm logic module, a first phase interpolator and a first sampler;

Wherein, after receiving the clock information and the input signal, the algorithm logic module controls the output clock of the first phase interpolator to traverse N phases, and controls the threshold voltage of the first sampler to traverse M voltage values , so as to test the bit error rate of the input signal sampled by the first sampler under each of the phases and each of the voltage values, and obtain an eye diagram of M*N test points, where N and M are both positive integers .
The eye pattern oscilloscope system of claim 1, further comprising:

an external interface, which is connected to the algorithm logic module and receives the eye diagram output by the algorithm logic module; the external interface is also used to adjust the values of N and M.
The eye pattern oscilloscope system of claim 1 , wherein N is 16 and M is 8.
The eye pattern oscilloscope system of claim 1, further comprising:

A phase-locked loop provides an initial clock for the clock recovery circuit and the eye-diagram oscilloscope.
An eye pattern testing method, applied to the system of any one of claims 1-4, the method comprising:

After the equalizer adjusts the input signal, the input signal is input to the clock data recovery circuit;

The clock data recovery circuit recovers clock information of the input signal, and inputs the clock information and the input signal into the eye-diagram oscilloscope;

After receiving the clock information and the input signal, the algorithm logic module in the eye diagram oscilloscope controls the output clock of the first phase interpolator to traverse N phases, and controls the threshold of the first sampler The voltage traverses M voltage values, so as to test the bit error rate of the input signal sampled by the first sampler under each of the phases and each of the voltage values, and obtains an eye diagram of M*N test points, N and M are positive integers.
The method of claim 5, wherein the test points in the eye diagram are hollow circles to indicate that the bit error rate meets requirements, and the test points in the eye diagram are solid circles to indicate the bit error rate Does not meet the requirements.
The method of claim 5, wherein before inputting the clock information and the input signal to the eye diagram oscilloscope, further comprising:

The clock data recovery circuit removes traceable jitter components within a portion of the loop bandwidth.
The method of claim 5, further comprising:

The equalizer is set to a plurality of equalization coefficients, and the method of claim 5 is executed under each equalization coefficient to obtain eye diagrams of corresponding multiple M*N test points;

A target equalization coefficient of the equalizer is determined according to the eye diagrams of the multiple M*N test points.
The method of claim 8, wherein the determining the target equalization coefficient of the equalizer according to the eye diagrams of the multiple M*N test points comprises:

The equalization coefficient corresponding to the eye pattern with the largest eye opening degree of the eye patterns of the multiple M*N test points is determined as the target equalization coefficient.
The method of claim 5, further comprising:

Set the jitter frequency to multiple jitter frequency values;

maintaining each of the jitter frequency values and gradually increasing the jitter amplitude of the input signal;

Until the eye pattern oscilloscope detects that the bit error rate of the input signal does not meet the preset requirement, record the current exceeding jitter amplitude;

According to a plurality of out-of-standard jitter amplitude values corresponding to the plurality of jitter frequency values, a jitter tolerance curve representing the receiver connected to the eye-pattern oscilloscope is obtained.