JP3449341B2 - Demodulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device used in a digital carrier transmission system.

[0002]

2. Description of the Related Art In recent years, a digital carrier transmission type communication system has been widely used in a wireless communication system. In the demodulator used for the receiver of this digital carrier wave transmission system, a clock signal is required to convert the demodulated signal into a digital signal. As a method of regenerating a clock signal with a demodulator, for example, there is a method disclosed in Japanese Patent Laid-Open No. 09-247229. According to the method disclosed in Japanese Patent Laid-Open No. 09-247229, as shown in FIG. 8, a band-limited baseband signal is converted into a digital signal by an A / D converter 101, and based on this digital signal. The phase detector 102 detects the phase information of the sampling clock, and the voltage-controlled oscillator 104
The sampling clock supplied to the A / D converter 101 is controlled so as to have the optimum phase, and there is an advantage that the clock phase adjustment is unnecessary and the optimum timing can be maintained.

[0003]

However, the A / D
If the signal output from the converter 101 is affected by an orthogonal error or the like due to imperfections of the transmitter, the gain of the clock phase determination decreases, and the jitter characteristic of the recovered clock deteriorates. It was In order to suppress the jitter characteristic of the reproduced clock, the quadrature error component of the transmitter may be removed from the output signal of the A / D converter 101. But,
When an orthogonal error correction means for removing an orthogonal error component is added after the A / D converter 101 and clock phase information is detected based on the output signal of the orthogonal error correction means, the orthogonal error is added to the clock control loop. The delay time of the correction means is added to increase the circuit delay, and in the synchronization pull-in process of the demodulation system, the synchronization pull-in time is delayed due to the unstable operation until the orthogonal error correction means is stabilized. A main object of the present invention is to realize a demodulation device capable of obtaining an optimum clock synchronization characteristic when the receiving device is in a stable state or when the receiving device is in an unstable state due to a synchronization pull-in process. Especially.

[0004]

SUMMARY OF THE INVENTION The present invention is a QP on the transmitting side.
A demodulator provided in a receiver for receiving a modulated signal that is quadrature-modulated by a quadrature modulation method such as SK or QAM,
A / D conversion means (1) for sampling a modulated analog signal in synchronization with a sampling clock and converting it into a digital signal, and phase rotation control for two mutually orthogonal digital signals output from the A / D conversion means. An infinite phase shift means (3) for obtaining a demodulated signal, an orthogonal error correction means (5) for removing an orthogonal error component from two mutually demodulated demodulated signals output from the infinite phase shift means, and a receiving device in a synchronization established state. , The two orthogonal demodulation signals output from the orthogonal error correction means are selected and output, and when the receiving device is in the synchronization pull-in process, the two orthogonal demodulation signals output from the infinite phase shift means. Selection means (8) for selecting and outputting a signal, and clock phase detection for detecting phase information of the sampling clock based on the signal output from the selection means A stage (9), an integrating means (10) for integrating the clock phase information detected by the clock phase detecting means, and an A / D converting means for sampling clocks having a frequency and a phase according to the control voltage output from the integrating means. And a voltage controlled oscillation means (11) for outputting to. Thus, when the receiving device is in the synchronization established state, the selecting means selects and outputs two demodulated signals which are orthogonal to each other and which are output from the orthogonal error correcting means, and when the receiving device is in the synchronization pull-in process, By selecting and outputting two mutually orthogonal demodulated signals output from the infinite phase shift means, the optimum control that can suppress the jitter component of the recovered clock is selected in the case of the synchronization established state, and the case of the synchronization pull-in process. Can switch the clock control system to select a control that can establish rapid clock synchronization. In addition, as one configuration example of the demodulation device of the present invention, the clock phase detection means, when the polarity of the first sample value and the second sample value that are continuous in time is different,
The result of the exclusive OR of the polarity of the first sample value and the polarity of the intermediate point between the first and second sample values is output as the phase information of the sampling clock.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION [First Embodiment] Next, an embodiment of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing the configuration of a demodulation device according to a first embodiment of the present invention. The demodulator is I (in phas
e), Q (quadrature phase) analog-digital converter (hereinafter referred to as ADC) 1 that samples and quantizes modulated analog signals of two series, and band limitation of each digital signal of I, Q2 series output from ADC1 Roll-off filter (Roll O
ff Filtter (hereinafter, referred to as ROF) 2 and an endless phase shifter (hereinafter, referred to as “ROF2”) that controls the phase of each of the I and Q2 series digital signals output from the ROF 2 and absorbs the phase difference from the transmission carrier. , EPS)
3 and a numerical control oscillator (Numeric Control Oscillat) for controlling the rotation phase amount of EPS3 to establish transmission carrier synchronization.
or, hereinafter referred to as NCO) 4, an orthogonal control circuit 5 serving as an orthogonal error correction means for removing an orthogonal error component of a transmission modulation wave from each demodulated signal of the I and Q2 sequences output from the EPS 3, and an orthogonal control. An equalizer 6 that removes waveform distortion due to fading or the like generated in the propagation path from each of the I and Q2 demodulated signals output from the circuit 5, and an equalizer 6
The error from the normal signal point position of each demodulated signal of the I and Q2 series outputted from
Carrier wave phase detection circuit 7 for outputting as O4 control signal
And a selection circuit 8 which selects and outputs either the output signal of the EPS 3 or the output signal of the orthogonal control circuit 5 in accordance with an alarm signal described later, and the reproduction clock of the reproduction clock based on the signal output from the selection circuit 8. A clock phase detector 9 for detecting phase information, and a low pass filter (Low Pass Filter) that operates as an integrating circuit by removing harmonic components of the clock phase information detected by the clock phase detector 9.
tter (hereinafter referred to as LPF) 10 and a voltage controlled oscillator 11 that outputs to the ADC 1 a sampling clock having a frequency corresponding to the control voltage output from the LPF 10.

In the present embodiment, QPSK (Quadtratur)
e Phase Shift Keying) is used as an example, and quasi-coherent detection is used as the detection method. The demodulation device of FIG. 1 is included in a reception device (not shown) that receives a signal from the transmission side and performs various processes such as demodulation, frame synchronization establishment, and descrambling. Further, in this receiving device, a frame synchronization circuit (not shown) that compares the demodulated signal with a predetermined synchronization pattern and performs synchronization protection is provided at the subsequent stage of the demodulation device of FIG. The frame synchronization circuit outputs an alarm signal indicating whether the receiving device is in the frame synchronization pull-in process or in the frame synchronization established state.

FIG. 2 is a block diagram showing the configuration of the selection circuit 8. When the alarm signal indicates that the synchronization pull-in process is in progress, the selection circuit 8 receives the signals 1A and 1B shown in FIG.
Side, that is, the I, Q2 series demodulated signal output from EPS3 is selected and output, and when the alarm signal indicates that the synchronization is established, it is output from the 0A, 0B side, that is, the orthogonal control circuit 5. The I and Q2 series demodulated signals are selected and output.

The operation of the demodulator of this embodiment will be described below. First, a case will be described in which the clock phase determination is performed in an ideal state where the transmitted modulated wave has no quadrature error component. The ADC 1 converts the modulated analog signal to the modulation frequency f
Sampling is performed with a sampling clock of s (fs = 1 / Ts, where Ts is the symbol period), and is converted into a digital signal. In the present embodiment, the modulation frequency f
Although the case of the sampling clock of s has been described, a sampling clock having a frequency twice the modulation frequency fs may be used. The ROF 2 shapes the waveform of each digital signal of the I and Q2 series output from the ADC 1. The EPS 3 establishes transmission carrier synchronization by controlling the phase of each of the I and Q2 series digital signals output from the ROF 2.

The quadrature control circuit 5 removes the quadrature error component of the transmitted modulated wave from the demodulated signals of the I and Q2 series output from the EPS 3. Various configurations of the quadrature control circuit 5 are known, for example, Japanese Patent Laid-Open No. 06-0.
As disclosed in Japanese Patent Laid-Open No. 85864 or Japanese Patent Laid-Open No. 07-212427, an orthogonal error is detected from a demodulated signal of an I, Q2 sequence, and I, Q2 is set so that the orthogonal error becomes zero.
One of the signals in the series may be phase-corrected by a variable capacitor, or, as disclosed in Japanese Patent Laid-Open No. 09-247228, the demodulated signals of the I and Q2 series are positioned on the theoretical orthogonal axis. A correction calculation may be performed.

The equalizer 6 removes the waveform distortion due to fading or the like generated in the propagation path from the demodulated signals of the I and Q2 sequences output from the orthogonal control circuit 5. In this way, the demodulated digital signal of the I and Q2 series is obtained from the output of the equalizer 6. Next, the carrier phase detection circuit 7
Detects an error from the normal signal point position of each demodulated signal of the I and Q2 series output from the equalizer 6, and outputs this error as a control signal of the NCO 4. In the case of QPSK, the regular signal point position is the position of the white circle shown in FIG.

The NCO 4 converts the phase error signal output from the carrier wave phase detection circuit 7 into a frequency error signal θ, and the frequency error signal θ is converted into rotation angle signals sin θ and cos θ.
And output to EPS3. Since the frequency is obtained by integrating the phase, the frequency error signal θ is obtained by integrating the phase error signal. The EPS 3 controls the phase of each of the I and Q2 series digital signals output from the ROF 2 by performing the calculation shown in the following equation, for example.

Iout = Iin × cos θ−Qin × sin θ (1) Qout = Iin × sin θ + Qin × cos θ (2) In the equations (1) and (2), Iin is an I series input to the EPS 3. , Iout is an I-series signal output from EPS3, Qin is a Q-series signal input to EPS3,
Qout is a Q-series signal output from EPS3.
The input signals Iout and Qout are rotated by the angle θ by performing rotational symmetric transformation of the vector as shown in the equations (1) and (2). In this way, the phase error at the output of the equalizer 6 is controlled so as to approach zero.

Next, the operation of the clock phase detector 9 will be described with reference to FIG. FIG. 4 is a diagram for explaining the optimum sampling phase, and is a diagram showing an eye pattern of a QPSK signal. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the polarity of sample values sampled by the ADC1. Further, the first and second sample values which are continuous in time are referred to as signals B and A in order from the earliest in time.

Signals B and A, which are two time-continuous sample values, have a symmetrical positional relationship with respect to the zero point which is the center of each convergence point. When the phase of the sampling clock supplied to the ADC 1 is optimum, the polarities of the temporal midpoints of the two signals B and A are almost equal to “1” and “0” when viewed at arbitrary time intervals. Occurs in. However, when the phase of the sampling clock is delayed or advanced, the polarities of the midpoints of the signals B and A are biased.

For example, in the case of the phase delay shown in FIG. 4A, the midpoint between the signals B and A occurs above the boundary line between the polarities "1" and "0" (polarity "1"). There are two kinds of signal transitions that satisfy the condition that the polarities of the signals B and A are different. In FIG. 4A, the polarity of the signal A is “0” and the polarity of the signal B is “1”. When the polarity of the signal A is "1" and the polarity of the signal B is "0", the polarity of the midpoint between the signals B and A occurs below the boundary line (polarity "0"). Here, in the case of the phase delay, the exclusive OR output of the polarity of the signal B and the polarity of the midpoint between the signals B and A becomes "0" in any of the above two cases.

On the other hand, in the case of the phase lead shown in FIG.
The midpoint between the signals B and A occurs below the boundary line of polarities "1" and "0" (polarity "0"). Similar to FIG. 4A, FIG. 4B is a case where the polarity of the signal A is “0” and the polarity of the signal B is “1”, and conversely, the polarity of the signal A is “1” and the polarity of the signal B. Is "0", the polarity of the midpoint between the signals B and A occurs above the boundary line (polarity "1"). In the case of phase advance, the exclusive OR output of the polarity of the signal B and the polarity of the midpoint between the signals B and A is “1” in any of the two cases.

The clock phase detector 9 includes a first signal B and a second signal A which are two time-sequential sample values.
And the polarity of signal B is different from that of signal B,
The result of the exclusive OR of the polarities of the intermediate points of A is output as the phase information of the sampling clock. The determination of the clock phase described above is the method disclosed in Japanese Patent Laid-Open No. 9-247229. It should be noted that such determination of the clock phase is performed by the first signal B and the second signal A which are temporally continuous.
It suffices to satisfy the condition that the polarities are different, and either one of the I and Q2 series signals output from the selection circuit 8 may be used.

Subsequently, the LPF 10 removes the harmonic component of the clock phase information detected by the clock phase detector 9. The voltage controlled oscillator 11 outputs a sampling clock having a frequency and a phase according to the control voltage output from the LPF 10, to the ADC 1. In this way, the sampling clock output from the voltage controlled oscillator 11 is controlled to the optimum phase for sampling the modulated analog signal by the ADC 1.

Next, a description will be given of the clock phase determination in the case where the transmitted modulated wave has an orthogonal error component. The operations of the clock phase detector 9, the LPF 10 and the voltage controlled oscillator 11 are exactly the same as those described above. However, there is a difference in the signal waveform input to the clock phase detector 9. Differences in signal waveforms will be described with reference to FIGS. 5, 6, and 7.

First, in order to make it easier to understand what kind of waveform the orthogonal error on the transmitting side appears in the received signal, the I and Q signals input to the clock phase detector 9 are two-dimensionally coordinated. Shown above is FIG. It is shown that the signal point becomes a rhombus when the transmitted modulation wave has an orthogonal error, and the signal point becomes a square when there is no orthogonal error. Since the clock phase detector 9 handles a one-dimensional signal, the points obtained by projecting the respective signal points on the I and Q axes are the actual signal points.

FIG. 6 shows a one-dimensional waveform of each of the I and Q signal points. An analog change waveform is also shown to show that it is a continuous waveform, but since the actual signal is a signal that has already been analog / digital converted, the digital value sampled at the time point of the up arrow in FIG. Is represented by a multi-bit signal. As shown in FIG. 6B, when the transmission modulation wave has a quadrature error component, the error component is added to the data, so that the degree of convergence at the sampling time pointed by the up arrow is deteriorated.

FIG. 7 shows the effect of the clock phase detector 9 when the clock phase is detected from such a signal waveform whose degree of convergence is deteriorated. FIG. 7 shows a state in which there is no delay in the phase of the sampling clock. The reference numerals shown in FIG. 7 are the same as those in FIG. Since the convergence point of the signal A and the signal B deteriorates, the signal B
The case where the polarity of the intermediate point of the signal A and the signal A has a unique value of "1" or "0" is shown by the dotted locus in FIG. In the case of this dotted line, the result of the exclusive OR of the polarities of the signal B and the polarities of the intermediate points of the signals B and A becomes the unique values of "1" and "0", and therefore the clock phase detector 9 outputs them. In the process of integrating the phase information by the LPF 10, mutual signals cancel each other out. Therefore, when a quadrature error component is present in the transmitted modulated wave, the signal capable of detecting the phase of the sampling clock is only the data of the locus represented by the solid line in FIG. 7, and the problem of reducing the gain of clock phase detection occurs. is there.

Therefore, in the present invention, when the receiving device is in the steady state, that is, when the alarm signal indicates that the frame synchronization is established, the I and Q2 demodulated signals output from the orthogonal control circuit 5 are selected. Let the circuit 8 choose
This signal is input to the clock phase detector 9. As a result, the signal from which the quadrature error component has been removed can be input to the clock phase detector 9, and the decrease in the gain of clock phase detection can be suppressed.

When the receiving device is in the process of pulling in the synchronization, the receiving device is required to promptly establish the clock synchronization. Therefore, when the alarm signal indicates that it is in the process of pulling in the frame synchronization, the signal before passing through the orthogonal control circuit 5, that is, I, Q2 output from the EPS 3
A series signal is selected by the selection circuit 8 and this signal is input to the clock phase detector 9. As a result, the unstable operation of the orthogonal control circuit 5 in the process of pulling in the clock synchronization and the delay time of the orthogonal control circuit 5 are controlled by the clock synchronization control loop (ADC1, ROF2, EPS3, selection circuit 8, clock phase detector 9, LPF 10 and voltage controlled oscillator 1
1) can be eliminated, the clock control can be stabilized, the in-loop delay time of the control loop can be minimized, and the clock phase synchronization can be quickly established.

In this embodiment, a signal indicating whether frame synchronization is established is used as an example of the alarm signal. However, when the error of the demodulator increases and the error rate exceeds an arbitrary error rate. Alternatively, a signal emitted to the computer may be used.

[Second Embodiment] Next, as another embodiment of the present invention, a multivalued QAM (Quadrature Amplitude) will be described.
Application to Modulation) is explained. The present invention is based on QPS
Not only K but also multi-level QAM can be applied.
Also when applied to multi-level QAM, the configuration of the demodulation device shown in FIG. 1 and the operation of the clock phase detector 9 described in FIG. 4 are the same as in the first embodiment.

In the first embodiment, each of I and Q is illustrated and described in binary in the case of QPSK, but in the case of multi-level QAM, I and Q signal points are two-dimensional. Figure 5 represented
In FIGS. 6 and 7, which represent the I and Q signal points one-dimensionally, the sample data is m ² QAM (m is 2,
4, 8 and 16) may be expanded to be considered. That is, in the case of 2 ⁸ QAM = 64 QAM, the number of I and Q signal points may be expanded from 2 to 8.

[0028]

According to the present invention, when the receiving device is in the synchronization established state and in the stable state, the selecting means selects and outputs two demodulated signals which are orthogonal to each other and which are output from the orthogonal error correcting means. As a result, the input signal of the clock phase detection means is obtained from the output of the quadrature error correction means, so that the influence of the quadrature error caused by the incompleteness of the transmission modulator is removed and the gain of the clock phase detection is optimized. It is possible to suppress the jitter of the reproduction sampling clock, and it is possible to achieve stable clock synchronization even in a situation where it is difficult to maintain clock synchronization of the demodulator due to fading in the propagation path. To be Further, when the receiving device is in an unstable state due to the synchronization pull-in process, the selecting means selects and outputs two demodulated signals which are orthogonal to each other and which are output from the infinite phase shifting means, thereby outputting the clock phase detecting means. Since the input signal is obtained from the signal that does not pass through the quadrature error correction means, the delay time in the clock control loop is minimized, and the unstable operation until the quadrature error correction means is stabilized can be avoided, which results in quicker operation. Clock synchronization can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a demodulation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a selection circuit.

FIG. 3 is a diagram showing a normal signal point position of a demodulated signal.

FIG. 4 is a diagram for explaining an optimum sampling phase.

FIG. 5 is a diagram showing a signal input to a clock phase detector on two-dimensional coordinates.

6 is a diagram showing each signal point in FIG. 5 in one dimension.

FIG. 7 is a diagram for explaining the influence of the clock phase detector when a quadrature error component is present in the transmitted modulated wave.

FIG. 8 is a block diagram showing a configuration of a conventional clock synchronization circuit.

[Explanation of symbols]

1 ... Analog-digital converter, 2 ... Roll-off filter, 3 ... Infinite phase shifter, 4 ... Numerically controlled oscillator, 5 ... Quadrature control circuit, 6 ... Equalizer, 7 ... Carrier phase detection circuit, 8
... selection circuit, 9 ... clock phase detector, 10 ... low pass filter, 11 ... voltage controlled oscillator.

─────────────────────────────────────────────────── ─── Continued Front Page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 27/00-27/38 H04L 7/00

Claims (2)

(57) [Claims] 1. A demodulator provided in a receiver for receiving a modulated signal subjected to quadrature modulation on a transmitting side, the A / D converting means sampling a modulated analog signal in synchronization with a sampling clock and converting the sampled digital signal into a digital signal. An infinite phase shift means for obtaining a demodulation signal by performing phase rotation control on two mutually orthogonal digital signals output from the A / D conversion means, and two mutually orthogonal demodulation signals output from the infinite phase shift means. When the quadrature error correction means for removing the quadrature error component from the receiver and the receiving device are in the synchronization established state, two demodulated signals output from the quadrature error correction device which are orthogonal to each other are selected and output, and the receiving device is synchronized. When in the pulling process, the two orthogonal signals output from the infinite phase shifting means
Selecting means for selecting and outputting two demodulated signals, clock phase detecting means for detecting phase information of the sampling clock based on the signal output from the selecting means, and integrating the clock phase information detected by the clock phase detecting means A demodulator, comprising: an integrating means for performing the above operation; and a voltage controlled oscillating means for outputting to the A / D converting means a sampling clock having a frequency and a phase corresponding to the control voltage output from the integrating means. 2. The demodulator according to claim 1, wherein the clock phase detection means is configured such that when the first sample value and the second sample value that are temporally consecutive have different polarities,
A demodulator which outputs the result of the exclusive OR of the polarity of the first sample value and the polarity of the intermediate point between the first and second sample values as the phase information of the sampling clock.