CN111343125B - 32APSK modulation system receiver synchronization method - Google Patents
32APSK modulation system receiver synchronization method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
- H04L27/3836—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers in which the carrier is recovered using the received modulated signal or the received IF signal, e.g. by detecting a pilot or by frequency multiplication
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention provides a 32APSK modulation system receiver synchronization system, and belongs to the technical field of wireless communication. The method aims to provide an all-digital receiver synchronization scheme with high synchronization precision and low algorithm complexity. The invention is realized by the following scheme: the high-speed ADC module is used for carrying out high-speed sampling on the received intermediate frequency analog signals, and the digital quadrature down-conversion module is used for completing quadrature down-conversion and low-pass filtering of the intermediate frequency digital signals to obtain IQ quadrature signals; the matched filtering module completes matched filtering of the receiving end filter and the sending filter; the bit synchronization module completes timing synchronization of signals; the carrier synchronization module extracts the local oscillation of the same frequency and the same direction of the carrier, removes the carrier, and performs the phase ambiguity resolution operation by using the phase ambiguity information fed back by the frame synchronization module; the frame synchronization module gives out phase ambiguity information, and after carrier synchronization and bit synchronization signals are equalized by the equalization module, the phase ambiguity information is fed back to the carrier synchronization module to be subjected to phase ambiguity demodulation, and synchronous bit streams are demodulated and output.
Description
Technical Field
The invention belongs to the field of high-order modulation and demodulation in wireless digital transmission, and particularly relates to a full digital receiver synchronization scheme suitable for a 32APSK modulation system.
Technical Field
With the continuous progress of information technology, more and more new situations of application are rapidly emerging, for example: the system comprises the internet of things, unmanned, high-definition satellite digital televisions, artificial intelligence and the like. While stable operation of these services must be ensured by high-speed and efficient communication systems, the requirements for information processing transmission rates are increasing as the demands for communication of these devices/applications continue to increase. As known from shannon theorem, to increase the information transmission rate, two modes of increasing the transmission bandwidth and increasing the spectrum utilization can be adopted. With the increasing number of communication devices, various devices need to occupy a certain spectrum bandwidth, so that available spectrum resources become extremely precious. In order to improve the communication capacity of the system, the scholars have studied a number of higher order modulation schemes, such as 16QAM, 16APSK, 32APSK, etc., by fully utilizing limited spectrum resources. Because the traditional rectangular QAM modulation mode has more amplitude than the APSK modulation mode under the condition of the same modulation order, the method has poor linearity of the channel condition, and is particularly used in a satellite communication system with limited transmitting power. More serious nonlinear distortion may be caused, deteriorating the performance of the system. Therefore, 16APSK and 32APSK, particularly 32APSK, play an increasingly important role in communication systems, particularly satellite communication systems, as a signal modulation scheme commonly used in the DVB-S2X standard.
In digital communication systems, synchronization is a critical component, which is a precondition for proper demodulation of signals. The synchronization mainly comprises carrier synchronization and timing synchronization, and the main function of the timing synchronization is to keep the clocks of the receiving and transmitting ends consistent so as to ensure that the receiving end samples and judges at the optimal moment. Bit synchronization can be divided into two ways, data-based assistance and non-data-based assistance, depending on whether a specialized training sequence is utilized. The bit synchronization method based on non-data assistance is divided into a feedback-oriented closed-loop algorithm and a feedforward-oriented open-loop algorithm. Carrier synchronization is also one of the key parts of a communication demodulation system, and early carrier synchronization is achieved by inserting pilot frequency information (or called carrier component) at a specific position while transmitting useful information, and a narrow-band filter and a phase-locked loop are directly used at a receiving end to capture, track and extract carrier information, so that the frequency band utilization rate of a channel is definitely reduced. The DVB-S2X standard puts higher demands on symbol timing synchronization, frame synchronization and carrier recovery at the demodulation end. In software defined radio receivers, the delay of the signal during propagation is generally unknown and the received signal is not synchronized with the local clock signal due to noise, multipath effects, etc. during transmission. The quality of the bit synchronization performance directly affects the performance of the overall communication system. The phase error errors of different bit synchronization algorithms are different, so that the variety of the bit synchronization algorithms is very large, and the bit synchronization algorithms can be divided into an analog mode, a half digital mode and a full digital mode according to different processing modes. The full analog bit synchronization realizing technology calculates a bit synchronization timing control signal of an input signal in an analog domain to control a local clock, and synchronously samples the signal. In the all-digital bit synchronization algorithm model, a fixed local sampling clock cannot guarantee that sampling can be realized at an extreme point of a signal, and sampling at the extreme point needs to be realized by changing a resampling clock or an input signal. The semi-analog synchronous model extracts the deviation value of the input signal and the local clock through a series of digital processing on the sampled signal, and changes the phase of the local clock through the deviation to achieve bit synchronization. Both modes need to change the phase of the local clock timely, which is unfavorable for the realization of high-speed digital signals and has lower integration degree.
Since satellite communication transmission rates often reach above Gbps, too slow locking can result in the loss of significant amounts of useful information, and the receiver must perform fast and stable synchronization in a short period of time. In digital communication systems, the euclidean distance between adjacent constellation points decreases dramatically as the modulation order increases, so the accuracy requirements for timing synchronization and carrier synchronization are much higher than those of MPSK modulated signals. Thus, the method is applicable to a variety of applications. An accurate carrier and bit synchronization scheme for a 32APSK modulation scheme, which is easy to implement by engineering, must be found to ensure correct operation of the entire communication system.
Disclosure of Invention
The invention aims at providing a 32APSK all-digital receiver synchronization scheme which has high synchronization precision, low algorithm complexity, easy engineering realization and effectiveness and is used for a 32APSK communication system commonly used in a satellite communication system in the technical background.
The above object of the present invention can be achieved by the following technical scheme, which is a synchronization system of a receiver of a 32APSK modulation system, comprising: the device comprises a high-speed ADC module, a digital quadrature down-conversion module, a matched filtering module, and a bit synchronization module, a carrier synchronization module, an equalization module, a frame synchronization module and a decoding module which are connected in sequence, and is characterized in that: the high-speed ADC module performs high-speed sampling on the received intermediate frequency analog signals, and the digital quadrature down-conversion module performs quadrature down-conversion and low-pass filtering on the intermediate frequency digital signals to obtain I, Q quadrature signals; the matched filtering module completes matched filtering of a receiving end filter and a transmitting filter, and improves demodulation performance of the receiver; the bit synchronization module adopts a Gardner timing synchronization algorithm, performs periodic sampling judgment at the middle moment of each code element based on an interpolated bit synchronization mode to recover a binary signal, completes timing sampling and timing synchronization of the signal, ensures sampling judgment of the signal at the optimal moment, and utilizes a built-in bit synchronization locking indication module to give a locking indication signal; the carrier synchronization module comprises a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of the same frequency and the same direction of a signal carrier, removes the carrier, gives out a carrier synchronization locking indication signal, and performs phase ambiguity resolution operation by utilizing phase ambiguity information fed back by the frame synchronization module; the equalization module equalizes the signals subjected to carrier synchronization and bit synchronization, so that the influence of channel transmission characteristics and channel noise on transmission performance is reduced; the frame synchronization module performs frame synchronization on the synchronized signals, gives out phase fuzzy information, feeds the phase fuzzy information back to the carrier synchronization module, and the carrier synchronization module performs phase fuzzy demodulation of demodulation signals by adopting a feedback-oriented closed-loop synchronization algorithm to obtain reliable and stable synchronization and gives out frame synchronization locking indication signals; the decoding module completes the decoding of the signal and outputs the demodulated synchronous bit stream.
Compared with the prior art, the invention has the following beneficial effects:
(1) And the engineering implementation is easy. The invention adopts a high-speed ADC module, a digital quadrature down-conversion module and a matched filtering module, and a synchronous system circuit form of a 32APSK modulation system receiver is formed by a bit synchronous module, a carrier synchronous module, an equalization module, a frame synchronous module and a decoding module which are connected in sequence, so that the structure is simple, and the engineering realization is easy.
(2) The synchronous precision is high, and the convergence is fast. According to the invention, the demodulation performance of the receiver is improved through the matched filtering module; the equalization module is used for equalizing the signals subjected to carrier synchronization and bit synchronization, so that the influence of channel transmission characteristics and channel noise on transmission performance is reduced; the data demodulation of the 32APSK modulation signal can be realized under the condition of low signal-to-noise ratio, and the influence of multipath distortion on the signal can be well resisted. The method has the advantages of fast convergence, good synchronization performance and improved synchronization precision; a feedback-oriented closed-loop synchronization algorithm is adopted to obtain reliable and stable synchronization, and simulation shows that the method has the characteristics of quick synchronization time, no need of adding any hardware equipment, simplicity and convenience and obvious performance improvement.
(3) The algorithm is simple. The invention aims at realizing a 32APSK modulation signal demodulation framework. The bit synchronization module adopts a Gardner timing synchronization algorithm to complete timing sampling timing synchronization of the signals, and ensures sampling judgment of the signals at the optimal moment. The timing synchronization efficiency of the Gardner algorithm is utilized, and the method is applied to the timing synchronization in a receiver synchronization system, does not adjust a local sampling clock and is not affected by carrier Doppler. The sampling value at the optimal sampling time is obtained by interpolating the input baseband signal, so that digital code element synchronization is realized, and the time for synchronizing the baseband signal can be greatly saved. The method is simple to implement, small in calculated amount, good in demodulation algorithm performance and easy to implement. The algorithm not only has fast convergence and good synchronization performance, but also has high synchronization precision. The carrier synchronization module is internally provided with a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of the same frequency and the same direction of a signal carrier, removes the carrier, performs frame synchronization on the synchronized signal by using the frame synchronization module, gives out phase ambiguity information, feeds back the phase ambiguity information to the carrier synchronization module for demodulating the signal, has simple algorithm, and has the advantages of short synchronization establishment time and real-time adjustment.
The invention is suitable for carrier and bit synchronization in the 32APSK all-digital receiver under various environments.
Drawings
For a clearer understanding of the invention, the invention will now be described with reference to the accompanying drawings, in which:
fig. 1 is a schematic block diagram of a synchronization scheme of an all-digital receiver of the 32APSK modulation system of the present invention.
Fig. 2 is a schematic block diagram of a bit sync loop of the present invention.
Fig. 3 is a schematic block diagram of a carrier loop of the present invention.
Fig. 4 is a functional block diagram of a second order loop filter of the present invention.
The practice of the invention will be described in further detail below with reference to the accompanying drawings.
Detailed Description
See fig. 1. In the preferred embodiments described below, a 32APSK modulation system receiver synchronization system comprises: the system comprises a high-speed ADC module, a digital quadrature down-conversion module, a matched filtering module, and a bit synchronization module, a carrier synchronization module, an equalization module, a frame synchronization module and a decoding module which are connected in sequence, wherein: the high-speed ADC module performs high-speed sampling on the received intermediate frequency analog signals, and the digital quadrature down-conversion module performs quadrature down-conversion and low-pass filtering on the intermediate frequency digital signals to obtain I, Q quadrature signals; the matched filtering module completes matched filtering of a receiving end filter and a transmitting filter, and improves demodulation performance of the receiver; the bit synchronization module adopts a Gardner timing synchronization algorithm, performs periodic sampling judgment at the middle moment of each code element based on an interpolated bit synchronization mode to recover a binary signal, completes timing sampling and timing synchronization of the signal, ensures sampling judgment of the signal at the optimal moment, and utilizes a built-in bit synchronization locking indication module to give a locking indication signal; the carrier synchronization module comprises a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of the same frequency and the same direction of a signal carrier, removes the carrier, gives out a carrier synchronization locking indication signal, and performs phase ambiguity resolution operation by utilizing phase ambiguity information fed back by the frame synchronization module; the equalization module equalizes the signals subjected to carrier synchronization and bit synchronization, so that the influence of channel transmission characteristics and channel noise on transmission performance is reduced; the frame synchronization module performs frame synchronization on the synchronized signals, gives out phase fuzzy information, feeds the phase fuzzy information back to the carrier synchronization module, and the carrier synchronization module performs phase fuzzy demodulation of demodulation signals by adopting a feedback-oriented closed-loop synchronization algorithm to obtain reliable and stable synchronization and gives out frame synchronization locking indication signals; the decoding module completes the decoding of the signal and outputs the demodulated synchronous bit stream.
The 32APSK modulation system receiver adopts the 32APSK all-digital receiver synchronization, and the synchronization comprises the following steps:
intermediate frequency analog signal fed into all-digital receiver is first high-speed analog-to-digital AD sampling and cosw is utilized c t generates two paths of orthogonal local oscillation signals, sends the two paths of orthogonal local oscillation signals to a rear-end multiplier to output two paths of orthogonal signals, then filters high-frequency components and other frequency components through a low-pass filter (LPF), sends the high-frequency components and other frequency components to a rear-end Matched Filtering (MF) module, and the matched filtering module performs matched filtering on the digital baseband signals to obtain a filtered baseband signal I 1 、Q 1 The method comprises the steps of carrying out a first treatment on the surface of the The bit synchronization module matches the filtered digital baseband signal I 1 、Q 1 Performing bit synchronization, completing timing sampling and timing synchronization of signals, ensuring sampling judgment of the signals at the optimal time, and giving out digital baseband I after bit synchronization 2 、Q 2 A lock indication signal; digital baseband signal I after bit synchronization 2 、Q 2 The carrier synchronization module sent into the carrier ring performs carrier synchronization to complete bit synchronization and signal I after carrier synchronization 3 、Q 3 Sending the data to an equalization module for digital equalization, and reducing the influence of inter-code crosstalk on the system performance; the equalized signal is sent to a back-end frame synchronization module for frame synchronization, and phase ambiguity information is provided and fed back to a carrier synchronization module; the carrier synchronization module performs phase ambiguity resolution operation by utilizing the phase ambiguity information fed back by the frame synchronization module; and sending the signals after frame synchronization by the frame synchronization module to the decoding module for decoding and judging to obtain a demodulated bit stream.
The complete timing recovery algorithm comprises a timing error detector, a loop filter, a numerical control oscillator and an interpolation filter. The loop filter is the same as the loop filter design method of the carrier synchronization algorithm, the timing error detector adopts a non-data-aided error detection algorithm (Gardner timing error detection algorithm), and the interpolation filter is utilized to recover the maximum value of the signal and then resample, so as to obtain a synchronous output signal y (kTi).
The value obtained by the interpolation filter is sent to a timing error detector to obtain the phase error tau (n) of the input signal and the local clock, then the noise and the high-frequency component in the phase error tau (n) are filtered by a loop filter, and the obtained value e (n) is sent to a numerical control oscillator to calculate the integer sampling moment mk and the interpolation point position uk of the interpolation filter, so that the timing output y (kTi) is obtained.
The Gardner timing recovery algorithm has a symbol rate that satisfies the nyquist's basic sampling law, namely, x (T) of the analog input signal T and a local fixed clock period Ts, and becomes a discrete signal x (mTs) after being sampled by the local fixed clock period Ts, and after bit synchronization is achieved, the decimal interpolation point uk is stabilized on a fixed waveform.
After passing through the interpolation filter module, the Gardner timing recovery algorithm samples and extracts timing errors by using a local clock generated by an original voltage-controlled oscillator NCO, then, after passing through the loop filter module LF, the error value is calculated, the value of a decimal interpolation point uk is fed back to control the decimal interpolation point of interpolation filtering, the phase of an output signal is changed, and the phase of the local clock is adjusted to be consistent with the phase of an input signal so as to realize synchronization. So that the phase of the input signal after passing through the interpolation filter is consistent with the phase of the local clock, and synchronization is achieved.
See fig. 2. The bit synchronization module adjusts the optimal sampling time according to the calculated timing error, and the process can be realized by correcting the A/D variable sampling clock by using a feedback structure or by interpolating a resampling method. In order to simplify the system calculation and realize the integration of the system, the present embodiment adopts a bit synchronous loop interpolation filtering mode. The bit synchronization module mainly comprises a bit synchronization module connected in series with the receiving end I 1 Output end I 2 Interpolation filter module, timing error detector module, loop filter module and digital voltage control oscillator NCO module in carrier ring, timing error detector utilizes receiving terminal I 1 The self phase information of the signal is used for carrying out the difference on adjacent symbol points through iteration, detecting the timing deviation in real time, removing the interference through a loop filter based on a phase-locked loop after finishing the real-time detection of the deviation,
in the I/Q channel mixer, a voltage-controlled oscillator NCO moves an input carrier signal to a frequency point designated by a frequency control word through configuration of the frequency control word of the NCO to generate orthogonal sine and cosine samples, sine and cosine values of phases are calculated according to phases of various sine and cosine waves in advance, the sine and cosine values of the phases are stored according to phase angles as addresses, under the control of a system clock, the input frequency word is continuously accumulated by a phase accumulator to obtain a digital phase taking the frequency word as a step, initial phase offset is carried out by a phase adding module to obtain a current phase to be output, and timing errors are compensated by interpolation technology of an interpolation filter module to obtain an optimal symbol point.
See fig. 3. The carrier synchronization module includes: the system mainly comprises a phase rotation module, a phase discriminator, a loop filter, a digital voltage-controlled oscillator NCO and a carrier synchronization locking indication module, and has the main functions of enabling a local carrier at a receiving and transmitting end to keep the same frequency and the same phase, removing the carrier, providing carrier synchronization locking indication signals and simultaneously utilizing phase ambiguity information fed back by a frame synchronization module to conduct phase ambiguity resolution operation.
The phase rotation module receives the baseband signal I after bit synchronization 2 、Q 2 Performing phase compensation and phase ambiguity resolution according to the phase error extracted by the carrier loop and the phase ambiguity information fed back by the frame synchronization module, feeding the phase compensated signal into a phase discriminator, and extracting the phase error and the residual phase error e by the phase discriminator in a decision feedback or M-th way d The extracted phase error is sent into a loop filter, so that the local carrier wave of a receiving end is kept in the same frequency and phase, the carrier wave is removed, and the digital voltage-controlled oscillator NCO outputs the error V of the loop filter d Performing feedback control, performing phase compensation on the input signal, providing carrier synchronization locking indication signal by carrier synchronization locking indication module, iterating, and outputting baseband signal I 3 、Q 3 。
See fig. 4. The loop filter corresponds to a low-pass filter, and in view of system performance and hardware implementation complexity, the present embodiment uses a second-order digital loop filter based on control with proportional and integral branches. Wherein the proportional branch has a certain phase locking capability, so is also called a phase tracking branch, but notFrequency error can be captured; the integrating branch is composed of a delay unit for integrating the input error and an adder, and has certain frequency tracking capability, so that the integrating branch is also called a frequency tracking branch. Phase error e generated by phase rotation module to phase discriminator d Digital processing is carried out, and the phase error e d Loop filter parameter C1, loop filter parameter C generated by proportional and integral branches 2 After the integral link and the proportional link are adjusted, the Z is delayed by a delay unit -1 The phase discrimination error V after filtering is obtained by adding the phase discrimination errors by an adder fed back to a frequency tracking branch d To the vco NCO module.
What has been described above is merely a preferred embodiment of the present invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the principles of the present invention, such as by adjusting the actual structure, and such modifications and changes should be considered as being within the scope of the present invention.
Claims (10)
1. A 32APSK modulation system receiver synchronization system, comprising: the device comprises a high-speed ADC module, a digital quadrature down-conversion module, a matched filtering module, and a bit synchronization module, a carrier synchronization module, an equalization module, a frame synchronization module and a decoding module which are connected in sequence, and is characterized in that: the high-speed ADC module performs high-speed sampling on the received intermediate frequency analog signals, and the digital quadrature down-conversion module performs quadrature down-conversion and low-pass filtering on the intermediate frequency digital signals to obtain I, Q quadrature signals; the matched filtering module completes matched filtering of a receiving end filter and a transmitting filter, and improves demodulation performance of the receiver; the bit synchronization module adopts a Gardner timing synchronization algorithm, based on an interpolated bit synchronization mode, periodically samples and judges at the middle moment of each code element to recover a binary signal, completes the timing synchronization of the signal, ensures the sampling and judging of the signal at the optimal moment, and utilizes the built-in bit synchronization locking indication module to give a bit synchronization locking indication signal; the carrier synchronization module comprises a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of the same frequency and the same direction of a signal carrier, removes the carrier, gives out a carrier synchronization locking indication signal, and performs phase ambiguity resolution operation by utilizing phase ambiguity information fed back by the frame synchronization module; the equalization module equalizes the signals subjected to carrier synchronization and bit synchronization, so that the influence of channel transmission characteristics and channel noise on transmission performance is reduced; the frame synchronization module performs frame synchronization on the synchronized signals, gives out phase fuzzy information, feeds the phase fuzzy information back to the carrier synchronization module, and the carrier synchronization module performs phase fuzzy demodulation of demodulation signals by adopting a feedback-oriented closed-loop synchronization algorithm to obtain reliable and stable synchronization and gives out frame synchronization locking indication signals; the decoding module completes the decoding of the signal and outputs the demodulated synchronous bit stream.
2. The 32APSK modulation system receiver synchronization system of claim 1, wherein: the 32APSK modulation system receiver is an all-digital receiver, and the intermediate frequency analog signal fed into the all-digital receiver is firstly high-speed analog-to-digital AD sampling and uses cosw c t generates two paths of orthogonal local oscillation signals, sends the two paths of orthogonal oscillation signals to a rear-end multiplier to output two paths of orthogonal signals, then filters high-frequency components and other frequency components through a low-pass filter (LPF), and sends the high-frequency components and other frequency components to a rear-end Matched Filtering (MF) module.
3. The 32APSK modulation system receiver synchronization system of claim 2, wherein: the matched filtering module performs matched filtering on the digital baseband signal to obtain a filtered baseband signal I 1 、Q 1 The method comprises the steps of carrying out a first treatment on the surface of the The bit synchronization module matches the filtered digital baseband signal I 1 、Q 1 Performing bit synchronization, completing timing sampling and timing synchronization of signals, ensuring sampling judgment of the signals at the optimal time, and giving out digital baseband I after bit synchronization 2 、Q 2 Locking the indication signal.
4. A 32APSK modulation system receiver synchronization system according to claim 3, wherein: digital baseband signal I after bit synchronization 2 、Q 2 Carrier synchronization module fed into carrier ring for carrier synchronizationStep, signal I after completing bit synchronization and carrier synchronization 3 、Q 3 And the data are sent to an equalization module for digital equalization, so that the influence of inter-code crosstalk on the system performance is reduced.
5. The 32APSK modulation system receiver synchronization system of claim 4, wherein: the equalized signal is sent to a back-end frame synchronization module for frame synchronization, and phase ambiguity information is provided and fed back to a carrier synchronization module; the carrier synchronization module performs phase ambiguity resolution operation by utilizing the phase ambiguity information fed back by the frame synchronization module; and sending the signals after frame synchronization by the frame synchronization module to the decoding module for decoding and judging to obtain a demodulated bit stream.
6. The 32APSK modulation system receiver synchronization system of claim 1, wherein: the bit synchronization module adjusts the optimal sampling time according to the calculated timing error, and is realized by an interpolation resampling method.
7. The 32APSK modulation system receiver synchronization system of claim 1, wherein: the bit synchronization module comprises a bit synchronization module connected in series with the receiving end I 1 Output end I 2 Interpolation filter module, timing error detector module, loop filter module and digital voltage control oscillator NCO module in carrier ring, timing error detector utilizes receiving terminal I 1 The self phase information of the signal is subjected to iterative difference on adjacent symbol points, the timing deviation is detected in real time, and after the real-time detection of the deviation is completed, the interference is removed through a loop filter based on a phase-locked loop.
8. The 32APSK modulation system receiver synchronization system of claim 7, wherein: in the I/Q channel mixer, the voltage-controlled oscillator NCO module moves the input carrier signal to the frequency point appointed by the frequency control word through the configuration of the frequency control word of the NCO, generates orthogonal sine and cosine samples, calculates the sine and cosine values of the phase according to the phase of each sine and cosine wave in advance, stores the sine and cosine values of the phase according to the phase angle as the address, under the control of the system clock, the phase accumulator continuously accumulates the input frequency word to obtain the digital phase taking the frequency word as the step, the phase adding module carries out initial phase offset to obtain the current phase to be output, and the interpolation filter module compensates the timing error to obtain the optimal symbol point.
9. The 32APSK modulation system receiver synchronization system of claim 1, wherein: the carrier synchronization module includes: phase rotation module, phase discriminator, loop filter, digital voltage controlled oscillator NCO, and carrier synchronization locking indication module, phase rotation module receives baseband signal I after bit synchronization 2 、Q 2 Performing phase compensation and phase ambiguity resolution according to the phase error extracted by the carrier loop and the phase ambiguity information fed back by the frame synchronization module, feeding the phase compensated signal into a phase discriminator, and extracting the phase error and the residual phase error e by the phase discriminator in a decision feedback or M-th way d The extracted phase error is sent into a loop filter, so that the local carrier wave of a receiving end is kept in the same frequency and phase, the carrier wave is removed, and the digital voltage-controlled oscillator NCO outputs the error V of the loop filter d Performing feedback control, performing phase compensation on the input signal, providing carrier synchronization locking indication signal by carrier synchronization locking indication module, iterating, and outputting baseband signal I 3 、Q 3 。
10. The 32APSK modulation system receiver synchronization system of claim 9, wherein: the loop filter uses a second-order digital loop filter based on control with a proportional branch and an integral branch, wherein the proportional branch is also called a phase tracking branch, the integral branch is also called a frequency tracking branch, the loop filter is composed of a delay unit for carrying out integral operation on input errors and an adder, and the phase rotation module generates a phase error e for a phase discriminator d Digital processing is carried out, and the phase error e d Loop filter parameter C1, loop filter parameter C generated by proportional and integral branches 2 Through integration link andafter the proportion link is regulated, delay Z is performed by a delay unit -1 The phase discrimination error V after filtering is obtained by adding the phase discrimination errors by an adder fed back to a frequency tracking branch d To the vco NCO module.
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