CN114338304B - Parallel baseband demodulator system for high-speed communication - Google Patents
Parallel baseband demodulator system for high-speed communication Download PDFInfo
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- CN114338304B CN114338304B CN202111636435.1A CN202111636435A CN114338304B CN 114338304 B CN114338304 B CN 114338304B CN 202111636435 A CN202111636435 A CN 202111636435A CN 114338304 B CN114338304 B CN 114338304B
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Abstract
The invention discloses a parallel baseband demodulator system for high-speed communication, which is a two-path parallel signal processing architecture and comprises: the system comprises an ADC sampling unit, a matched filter, a timing synchronization module, an IQ imbalance correction module, an IQ self-adaptive exchange module, a frame synchronization module, a digital gain control module, a carrier synchronization module, an equalizer, a demapping unit and a decoding unit which are sequentially arranged according to the signal transmission direction. The invention provides a parallel baseband demodulator system for high-speed communication, which adopts an algorithm-level full-parallel mode, compared with the traditional serial demodulation, the system can break through the rate limit of an FPGA device, greatly improve the demodulation rate with less hardware resource increment under the lower device clock frequency, and solve the algorithm hardware realization problem under the high transmission capacity.
Description
Technical Field
The invention belongs to the field of wireless communication, and particularly relates to a parallel baseband demodulator system for high-speed communication.
Background
As one of high-speed communications, terahertz communications is a key underlying technology for implementing 6G landscape, and compared with the current 5G technology supporting a maximum operating bandwidth of 800MHz, the operating bandwidth available for terahertz communications can be as high as tens or even tens of GHz.
High speed modems are key devices for achieving high speed communications, the performance of which determines the data transmission capabilities of the communication system. The current high-speed modems basically adopt serial demodulation frameworks, the demodulation rate of which depends on the rate of the main clock frequency of digital devices such as FPGA, DSP and the like, however, the clock frequency of the current digital devices such as FPGA, DSP and the like is low, the clock frequency is low, the speed of the current digital devices such as FPGA, DSP and the like cannot be improved basically, and the like, so that the requirements of high-speed data transmission of terahertz communication cannot be met, and the application of the current modems in high-speed communication is limited.
Therefore, in order to further increase the demodulation rate of the modem, a new demodulation architecture is needed to provide theoretical basis and implementation means for reliable transmission of ultra-high-speed data of terahertz communication, so as to meet the increasing real-time and mass data transmission requirements in communication.
Disclosure of Invention
In view of this, the present invention provides a parallel baseband demodulator system for high-speed communication, which adopts an algorithm level full parallel mode, and compared with the traditional serial demodulation, the system can break through the limitation of device rate, greatly improve the demodulation rate with less hardware resource increment under the lower device clock frequency, and solve the algorithm hardware implementation problem under the high transmission capacity.
To achieve the purpose, the invention adopts the following technical scheme: a parallel baseband demodulator system for high-speed communications, the system being a two-way parallel signal processing system, the system comprising: the system comprises an ADC sampling unit, a matched filter, a timing synchronization module, an IQ imbalance correction module, an IQ self-adaptive exchange module, a frame synchronization module, a digital gain control module, a carrier synchronization module, an equalizer, a demapping unit and a decoding unit which are sequentially arranged according to the signal transmission direction, and further comprises two EVM calculation modules and an error rate calculation module, wherein the two EVM calculation modules are respectively connected with the frame synchronization module and the equalizer, and the error rate calculation module is connected with the decoding unit.
Preferably, the sampling frequency of the ADC sampling unit is 10Gsps, the sampling bit width is 8 bits, and the ADC sampling unit adopts a 156.25MHz system clock to sample and output 64 paths of parallelized signals.
Preferably, the matched filter is a multichannel parallel root raised cosine filter based on a fast FIR filter.
Preferably, the timing synchronization module adopts a timing synchronization algorithm based on a Gardner algorithm; the timing synchronization module includes: the device comprises a rate conversion unit, a data selection unit, an interpolator, a timing error detection unit, a loop filter and a digital oscillator which are sequentially arranged according to the signal processing sequence.
Preferably, the interpolator is a cubic Lagrange interpolator based on a Farrow structure.
Preferably, the IQ-imbalance correction module uses a multi-path parallel IQ-imbalance correction algorithm.
Preferably, the frame synchronization module adopts a multi-channel parallel frame structure based on a plurality of symbols of a constant envelope zero autocorrelation sequence, and the digital gain control module adopts a digital AGC algorithm of power smoothing filtering.
Preferably, the carrier synchronization module adopts a multipath parallel carrier frequency offset estimation algorithm based on decision feedback and a second-order phase-locked loop; the carrier synchronization module includes: the phase compensation unit, the hard decision unit, the phase discrimination unit, the annular filter and the digital oscillator are sequentially connected according to the signal transmission direction.
Preferably, the equalizer adopts a multipath parallel least mean square algorithm based on hard decisions and known information; the equalizer comprises a multipath parallel fast FIR filter, a hard decision unit and a coefficient updating unit which are sequentially arranged according to the signal transmission direction.
Preferably, the demapping unit adopts a multi-path parallel Gray code demapping algorithm; the decoding unit adopts a PRBS 31-based demapping algorithm with multiple paths in parallel.
The beneficial effects of the invention are as follows: the invention provides a parallel baseband demodulator system for high-speed communication, which adopts an algorithm-level full-parallel mode, compared with the traditional serial demodulation, the system can break through the limitation of device rate, greatly improve the demodulation rate with less hardware resource increment under lower device clock frequency, solve the problem of algorithm hardware realization under high transmission capacity, and the demodulator system can realize demodulation of 20Gbps and 16QAM data under the clock frequency of 156.25MHz through the test on an actual hardware platform.
Drawings
FIG. 1 is a schematic diagram of a parallel baseband demodulator system for high-speed communication according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a timing synchronization module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a carrier synchronization module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an equalizer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the output results of hardware platform testing using the present invention;
in the figure: ADC sampling unit 102, matched filter 103, timing synchronization module 104, IQ imbalance correction module 105, IQ adaptive switching module 106, frame synchronization module 107, digital gain control module 108, carrier synchronization module 109, equalizer 110, demapping unit 120, decoding unit 130, error rate calculation module 140, EVM calculation module 1031, rate conversion unit 1032, data selection unit 1033, interpolator 1034, timing error detection unit 1035, loop filter I1036, digital oscillator I1081, phase compensation unit 1082, hard decision unit I1083, phase discrimination unit 1084, loop filter II 1085, digital oscillator II 1091.32, parallel fast FIR filter 1092, hard decision unit II 1093, coefficient update unit.
Detailed Description
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
The invention will now be described in detail with reference to the drawings and specific examples.
As an embodiment, as shown in fig. 1, a parallel baseband demodulator system for high-speed communication is implemented by an FPGA pipeline in an algorithm stage full parallel manner, and the system includes: the system comprises an ADC sampling unit 101, a matched filter 102, a timing synchronization module 103, an IQ imbalance correction module 104, an IQ self-adaptive switching module 105, a frame synchronization module 106, a digital gain control module 107, a carrier synchronization module 108, an equalizer 109, a demapping unit 110 and a decoding unit 120 which are sequentially arranged according to the signal transmission direction, and further comprises two EVM calculation modules 140 and an error rate calculation module 130, wherein the two EVM calculation modules 140 are respectively connected with the frame synchronization module 106 and the equalizer 109, and the error rate calculation module 130 is connected with the decoding unit 120.
The sampling frequency of the ADC sampling unit 101 is 10Gsps, the sampling bit width is 8 bits, the ADC sampling unit 101 adopts a system clock of 156.25MHz to sample, and samples and outputs 64 paths of signals subjected to parallelization, and the ADC sampling unit 101 is mainly used for sampling two paths of signals of I (in-phase) and Q (quadrature phase) respectively;
the matched filter 102 is a 64-way parallel root raised cosine filter based on a fast FIR filter.
The timing synchronization module 103 is implemented by using a Gardner algorithm-based timing synchronization algorithm with parallel input 64 and parallel output 32, and the implementation block diagram is shown in fig. 2, where the processed signal sequentially passes through a rate conversion unit 1031, a data selection unit 1032, an interpolator 1033, a timing error detection unit 1034, a loop filter i 1035, and a digital oscillator i 1036, where the interpolator 1033 is a cubic Lagrange interpolator based on a Farrow structure.
The IQ-imbalance correction module 104 employs 32 parallel IQ-imbalance correction algorithms.
The frame synchronization module 106 uses a 128 symbol frame structure based on a constant envelope zero auto-correlation sequence in parallel with 32.
The 32 parallel data output by the frame synchronization module 106 is passed through a digital gain control module (AGC) 107, which employs a 32 parallel power smoothing filtered digital AGC algorithm.
The carrier synchronization module 108 adopts a carrier frequency offset estimation algorithm based on decision feedback and a second-order phase-locked loop in parallel with 32; as shown in fig. 3, the carrier synchronization module 108 further includes: phase compensation unit 1081, hard decision unit i 1082, phase discrimination unit 1083, loop filter ii 1084, and digital oscillator ii 1085 are connected in this order in the signal transmission direction.
The equalizer 109 adopts a 32 parallel minimum mean square algorithm based on hard decisions and known information, as shown in fig. 4, the equalizer 109 includes 32 parallel fast FIR filters 1091, a hard decision unit ii 1092 and a coefficient update unit 1093, which are sequentially arranged according to the signal transmission direction, wherein the coefficient update unit 1093 selects 8 paths of the 32 paths of decision information for calculation and update, which not only ensures the robustness of the algorithm, but also reduces implementation resources.
The demapping unit 110 adopts a 32-parallel gray code demapping algorithm; the decoding unit 120 employs a 32 parallel PRBS 31-based demapping algorithm.
As shown in FIG. 5, the Xilinx XCKU115-FLVD1924 FPGA is selected as a hardware implementation platform, the modulation mode is 16QAM, the hardware clock frequency is 156.25MHz, the symbol-level parallelism is 32, and the terahertz high-speed communication signal transmission with the bit rate of about 24Gbps can be realized by using the method.
Claims (7)
1.A parallel baseband demodulator system for high-speed communications, the system being a two-way parallel signal processing architecture, the system comprising: the system comprises an ADC sampling unit, a matched filter, a timing synchronization module, an IQ imbalance correction module, an IQ self-adaptive exchange module, a frame synchronization module, a digital gain control module, a carrier synchronization module, an equalizer, a demapping unit and a decoding unit which are sequentially arranged according to the signal transmission direction, and further comprises two EVM calculation modules and an error rate calculation module, wherein the two EVM calculation modules are respectively connected with the frame synchronization module and the equalizer, and the error rate calculation module is connected with the decoding unit;
the ADC sampling unit outputs multipath parallelized signals; the matched filter is a multipath parallel root raised cosine filter; the timing synchronization module adopts a multi-path parallel timing synchronization algorithm based on a Gardner algorithm; the IQ imbalance correction module adopts a multipath parallel IQ imbalance correction algorithm; the frame synchronization module adopts a multi-channel parallel frame structure based on a plurality of symbols of a constant envelope zero autocorrelation sequence; the digital gain control module adopts a digital AGC algorithm of multipath parallel power smoothing filtering; the carrier synchronization module adopts a multipath parallel carrier frequency offset estimation algorithm based on decision feedback and a second-order phase-locked loop; the equalizer adopts a multipath parallel minimum mean square algorithm based on hard decisions and known information; the demapping unit adopts a multi-path parallel Gray code demapping algorithm; the decoding unit adopts a PRBS 31-based demapping algorithm with multiple paths in parallel.
2. The parallel baseband demodulator system for high-speed communication according to claim 1, wherein the ADC sampling unit has a sampling frequency of 10Gsps and a sampling bit width of 8 bits.
3. The parallel baseband demodulator system for high-speed communication according to claim 1, wherein the matched filter is a multi-path parallel root-raised cosine filter based on a fast FIR filter.
4. The parallel baseband demodulator system for high-speed communication according to claim 1, wherein the timing synchronization module comprises: the device comprises a rate conversion unit, a data selection unit, an interpolator, a timing error detection unit, a loop filter and a digital oscillator which are sequentially arranged in the order of signal processing.
5. The parallel baseband demodulator system for high-speed communications according to claim 4, wherein the interpolator is a cubic Lagrange interpolator based on a Farrow structure.
6. The parallel baseband demodulator system for high-speed communications according to claim 1, wherein the carrier synchronization module comprises: the phase compensation unit, the hard decision unit, the phase discrimination unit, the annular filter and the digital oscillator are sequentially connected according to the signal transmission direction.
7. The parallel baseband demodulator system for high-speed communication according to claim 1, wherein the equalizer comprises a plurality of parallel fast FIR filters, a hard decision unit, and a coefficient update unit, which are sequentially arranged in the signal transmission direction.
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