CN115996162A - Time domain O & M timing synchronization method for serial high-efficiency communication - Google Patents

Time domain O & M timing synchronization method for serial high-efficiency communication Download PDF

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CN115996162A
CN115996162A CN202211474592.1A CN202211474592A CN115996162A CN 115996162 A CN115996162 A CN 115996162A CN 202211474592 A CN202211474592 A CN 202211474592A CN 115996162 A CN115996162 A CN 115996162A
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timing
time domain
timing error
signal
filter
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王皓月
张金波
刘丽哲
乔健
巩乃成
张延洞
宋祥宇
张豪
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CETC 54 Research Institute
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Abstract

The invention discloses a serial high-efficiency communication time domain O & M timing synchronization method, and belongs to the field of terahertz millimeter wave high-speed communication. The method uses ADC to complete signal sampling, and extracts complex sequences to a timing synchronization module for processing after data capture; calculating the pilot sequence model, namely the envelope amplitude, and sending the result to an IQ two-way to finish DFT operation; calculating to obtain a timing error estimated value by using a real part and an imaginary part after DFT operation; and (3) calculating the tap positions of the filter according to the timing error calculation result, and indexing the coefficients of the polyphase filter, wherein the polyphase filter completes timing error compensation and signal data rate conversion in the time domain. The invention adopts open loop IQ two-path parallel and symbol non-integer multiple sampling design, each path of IQ serially processes sample data, and performs timing error compensation on a time domain, thereby avoiding DFT and IDFT operations and simultaneously further reducing occupation of hardware resources.

Description

Serial high-efficiency communication time domain O & M timing synchronization method
Technical Field
The invention relates to the field of terahertz millimeter wave communication, in particular to a serial efficient time domain O & M timing synchronization method for communication bit synchronization.
Background
In the field of software radio, the received signal is biased due to the existence of transmission delay and clock offset of a transceiver when the signal passes through a channel. The data after the signal receiving end is processed by sampling down-conversion is a string of code element sequence, and the sampling clock of the receiving end is adjusted to be consistent with the frequency phase of the received code element, so that the sampling decision can be carried out on the received code element at the optimal sampling moment of the received code element.
Bit synchronization can be divided into two major categories, namely data assistance and non-data assistance according to the presence of data assistance, and the latter does not need additional assistance sequences, so that compared with a data assistance method, the method has higher spectrum utilization rate and wider application in engineering. The Gardner algorithm and the O & M algorithm are representative of the non-data aided bit synchronization algorithm. The O & M algorithm is an algorithm proposed by OerderM and Meyr H in 1988 for estimating timing errors using square-law nonlinear transformation.
However, conventional O & M timing synchronization algorithms do not meet the high rate, large bandwidth data transmission requirements.
Disclosure of Invention
The invention aims to provide a serial high-efficiency communication time domain O & M timing synchronization method, which can compress the use of hardware logic resources from an operation framework, reduce the resource consumption while guaranteeing the transmission of ultra-high speed modulation rate and shorten the timing synchronization time.
The technical scheme adopted by the invention is as follows:
a serial high-efficiency communication time domain O & M timing synchronization method comprises the following steps:
step 1, sampling signals, completing frame synchronization of sampled data, and performing timing synchronization processing on a complex sequence after frame synchronization to obtain a complex timing synchronization sequence;
step 2, performing I, Q two paths of serial input timing processing on the complex timing synchronization sequence, multiplying each path by a binary symbol form according to bits, accumulating and summing to obtain a square value, and summing the results obtained from I, Q paths to obtain a receiving signal module;
step 3, the signal envelope value is respectively sent into I, Q two paths, and each path of signal is respectively connected with a corresponding rotation factor W nI and Wnq Multiplying and summing to finish DFT operation;
step 4, timing error estimation is carried out by utilizing the real part and the imaginary part of the signal after DFT operation, and the frequency domain phase offset, namely the timing error estimation result, is calculated;
step 5, loop filtering smoothing is carried out according to the timing error estimation result, timing synchronization time domain delay is calculated, and the time domain delay corresponds to the tap position of the filter for subsequent processing;
step 6, storing filter coefficients corresponding to different timing error estimation results in ROM, taking the tap position of the filter output in step 5 as ROM index address, and dynamically controlling ROM to output the filter coefficients;
and 7, inputting the filter coefficient output by the ROM into a multiphase filter module to finish the timing error compensation of the sampling signal.
Further, in the specific mode of step 1, an analog-to-digital conversion module connected with an FPGA baseband board is used for sampling signals, frame synchronization is completed on the sampled signals in the baseband board, and an output result includes a pilot sequence extracted from received sampled data and is used for timing error estimation.
Further, in the DFT operation in step 3, the signal is in complex form with a sampling rate satisfying the nyquist sampling theorem, and the DFT operation is expressed as:
Figure BDA0003959091350000021
wherein ,xk Is the receiving signal module; x is X m Is x k K is the sample number, L is the symbol accumulation length, and m is the sample segment number; I. the Fourier transform rotation factors of the Q paths are respectively represented as W nI ＝Im[e -j2kπ/N] and Wnq ＝Re[e -j2kπ/N ]The method comprises the steps of carrying out a first treatment on the surface of the N is the number of DFT points.
Further, in step 4, X m The real part of (2) corresponds to the sampling point modulus and the twiddle factor W nI Product of X m The imaginary part of (2) corresponds to the sampling point modulus and the twiddle factor W nq The product of the two paths of the sign accumulation length L and I, Q is processed in series respectively; x is X m The real part and the imaginary part of (a) are respectively expressed as:
Figure BDA0003959091350000031
Figure BDA0003959091350000032
wherein Re [ X ] m] and Im[Xm ]Respectively represent X m Real and imaginary parts of I k and Qk The real part and the imaginary part of the received sample signal respectively;
the DFT operation is represented by the real part and the imaginary part of the received signal, and the timing error estimated value of L symbols is
Figure BDA0003959091350000033
Wherein the error estimate
Figure BDA0003959091350000034
Is an unbiased estimate of epsilon.
Further, in step 5, the filter coefficient tap position for timing error compensation is calculated by
Figure BDA0003959091350000035
wherein ,
Figure BDA0003959091350000036
for timing error estimation, f us Is the up-sampling multiple of the root cosine filter symbol.
Further, in the specific mode of step 7, the filter coefficient and the signal sample point are convolved in the time domain, the filter adopts a multiphase structure design, and signal timing error compensation is realized by utilizing the difference of extraction and interpolation multiples of the multiphase filter, and meanwhile, data rate conversion is completed.
The beneficial effects of the invention are as follows:
1. under the gigahertz ultra-large bandwidth and ultra-high speed modulation and demodulation system, the traditional square law timing synchronization algorithm is not applicable any more. The invention adopts IQ path parallel and symbol non-integer multiple sampling design, under the limitation of hardware sampling rate, not only meets the requirement of transmission rate, but also avoids the problem of excessive number of symbol operation points; the open loop timing structure has the advantages of short timing synchronization time, simple algorithm implementation and the like compared with the closed loop structure.
2. The invention solves the problem that the ADC cannot sample at the optimal sampling time of the symbol, and improves the signal-to-noise ratio of the received signal. Compared with the existing algorithm, the structure with control signal feedback tends to increase the time required for synchronization, and the convergence speed is slow, so that the method is not suitable for demodulation of burst signals. According to the invention, only the pilot sequence of part of received data is required to be extracted for processing by a timing synchronization algorithm, so that the instantaneity and the high efficiency of high-speed communication are satisfied; the IQ paths respectively adopt serial processing architecture, so that the use of logic resources in hardware is reduced while the transmission rate is met, and the stability of algorithm performance is ensured. In addition, the invention provides a new error correction mode, the tap position of the filter coefficient is estimated according to the timing error estimation value and the up-sampling multiple of the filter, and the timing error estimation compensation is carried out in the time domain, meanwhile, DFT and IDFT modules are omitted, the occupation of hardware resources is effectively reduced, and the time required by a timing synchronization algorithm is shortened.
Drawings
Fig. 1 is a flow chart of the method of the present invention.
Fig. 2 is a schematic diagram of the method of the present invention.
Fig. 3 is a graph of the input signal mode spectra during processing in accordance with the present invention.
Fig. 4 is a constellation point contrast diagram of QPSK modulation of the pilot sequences before and after processing in accordance with the present invention.
Detailed Description
The objects, technical solutions and advantages of the present invention will become more apparent by the following detailed description of the present invention with reference to the accompanying drawings, in conjunction with the specific embodiments.
A serial high-efficiency communication time domain O & M timing synchronization method, this method uses ADC to finish signal sampling, extract complex sequence to the timing synchronization module to process after the data capture; calculating the pilot sequence model, namely the envelope amplitude, and sending the result to an IQ two-way to finish DFT operation; calculating to obtain a timing error estimated value by using a real part and an imaginary part after DFT operation; and (3) calculating the tap positions of the filter according to the timing error calculation result, and indexing the coefficients of the polyphase filter, wherein the polyphase filter completes timing error compensation and signal data rate conversion in the time domain.
Specifically, the method comprises the following steps:
step 1, an ADC analog-to-digital converter connected with an FPGA baseband board card is used for completing signal sampling, the sampled signals are firstly subjected to data acquisition synchronization, the captured signals determine frame heads, a complex pilot sequence is extracted, and the complex pilot sequence is output to a timing synchronization module for timing error estimation.
Step 2, samples obtained after the received signal r (t) is up-sampled by N times by the receiving end are:
Figure BDA0003959091350000051
wherein ,an For transmitting data symbols, g (t) is the total response of the shaping filter, channel and receiving filter and ε is the timing error. After signal sample acquisition, the extracted pilot sequence can be represented as r by an orthogonal complex vector k ＝I k +jQ k Where k=0, 1,2, N, the extracted pilot sequence data is used for timing error estimation.
The complex pilot sequence is inputted into the timing module through I, Q two paths of serial, each path of sampling binary symbol form is multiplied by bit and accumulated and summed to obtain the square value, the result obtained by I path and Q path is summed to obtain the receiving signal model, the envelope value can be used
Figure BDA0003959091350000052
And (3) representing.
Step 3, the obtained signal envelope squares are respectively sent into I, Q paths, and each path of signal is respectively combined with a corresponding rotation factor W nI and Wnq Multiplying and accumulating the summation to finish the DFT operation. The sampling rate of the method meets the Nyquist sampling theorem, the signal is in a complex signal form, and the DFT conversion can be expressed as follows:
Figure BDA0003959091350000061
/>
wherein WnI ＝Im[e -j2kπ/N] and Wnq ＝Re[e -j2kπ/N ]Respectively, twiddle factors, and N is the number of DFT points.
Step 4, for the signal module x k Calculating DFT to obtain X m Real and imaginary parts of X m The real part of (2) corresponds to the sampling point modulus and the twiddle factor W nI Product of X m The imaginary part of (2) corresponds to the sampling point modulus and the twiddle factor W nq Each path of the product of (a) and the symbol accumulation length L, I, Q is processed in series, then X m The real and imaginary parts of (a) are respectively expressed as
Figure BDA0003959091350000062
Figure BDA0003959091350000063
So far, the DFT operation can be represented by the real part and imaginary part signal operation result of the received signal, and the calculated L symbols of the timing error estimated value are
Figure BDA0003959091350000064
And obtaining the frequency domain phase offset to obtain a timing error estimation result.
Step 5, loop filtering smoothing is carried out according to the timing error estimation result, the timing synchronous time domain delay is obtained by calculation, and the calculation formula of the tap position of the filter coefficient for timing error compensation is as follows
Figure BDA0003959091350000065
wherein />
Figure BDA0003959091350000066
For timing error estimation, f us And for the up-sampling multiple of the root cosine filter symbol, the calculated result corresponds to the storage address of the coefficient in the ROM, and the filter coefficient output by the index is used for subsequent compensation processing.
And 6, storing filter coefficients corresponding to different timing error estimation results in a ROM, and dynamically controlling the ROM to output the filter coefficients by taking the tap positions of the filter output in the step 5 as ROM index addresses.
And 7, inputting the filter coefficient obtained by the index ROM into a polyphase filter module, convoluting the filter coefficient with a received signal sampling result in a time domain, and realizing data rate conversion while completing the timing error compensation of the sampling signal.
The method fully considers the limitation of hardware sampling rate, adopts open-loop IQ path parallel and symbol non-integer multiple sampling design on the premise of meeting the data transmission rate, and the O & M algorithm for serially processing samples in each IQ path is beneficial to saving the internal resources of hardware and realizing high-efficiency stable data transmission. And the O & M timing error result is sent to a filter for time domain timing error compensation, and compared with frequency domain implementation, the time domain compensation omits the steps of DFT and IDFT, and further compresses the quantity of resources required for implementing the algorithm.
The following is a more specific example:
as shown in fig. 1, a serial high-efficiency communication time domain O & M timing synchronization method specifically comprises the following implementation steps:
step 1, an ADC analog-to-digital converter connected with an FPGA baseband board card is used for completing signal sampling, the sampled signals are firstly subjected to data acquisition synchronization, the captured signals determine frame heads, a complex pilot sequence is extracted, and the complex pilot sequence is output to a timing synchronization module for timing error estimation.
Step 2, samples obtained after the received signal r (t) is up-sampled by N times by the receiving end are:
Figure BDA0003959091350000071
wherein ,an For transmitting data symbols, g (t) is the total response of the shaping filter, channel and receiving filter and ε is the timing error. After signal sample acquisition, the pilot sequence can be represented as r by an orthogonal complex vector k ＝I k +jQ k Where k=0, 1,2,..n, taking n=56, extracts part of the pilot sequence for timing error estimation.
As shown in FIG. 2, the complex pilot sequences are respectively inputted into the timing module through I, Q two paths of serial numbers, each path is multiplied by bits in the form of binary symbols and accumulated and summed to obtain the square value thereof, the result obtained by the I path and the Q path is summed to obtain the receiving signal module, and the envelope value thereof is available
Figure BDA0003959091350000072
And (3) representing.
Step 3, the obtained signal envelope values are respectively sent into I, Q paths, and each path of signal is respectively combined with a corresponding rotation factor W nI and Wnq Multiplying and summing to complete DFT operation.
The sampling rate of the method meets the nyquist sampling theorem,the signal being in the form of a complex signal in which the symbol rate f B Signal bandwidth b=2.1 GHz, sampling rate f s =4.8 GHz, the receiving side samples 8/7 times, and then its DFT transform can be expressed as:
Figure BDA0003959091350000081
wherein WnI ＝Im[e -j2kπ/N] and Wnq ＝Re[e -j2kπ/N ]Respectively, twiddle factors, and N is the number of DFT points.
Step 4, for the signal module x k Calculating DFT to obtain X m Real and imaginary parts of X m The real part of (2) corresponds to the sampling point modulus and the twiddle factor W nI Product of X m The imaginary part of (2) corresponds to the sampling point modulus and the twiddle factor W nq The sign accumulation length is l=56, the number of FFT points in the simulation is 64 points, and the result is shown in the power spectrum of fig. 3; I. q each path of serial processing, X m The real and imaginary parts of (a) are respectively expressed as
Figure BDA0003959091350000082
Figure BDA0003959091350000083
So far, the DFT operation can be represented by the real part and the imaginary part of the received signal, and the estimated value of the timing error of the L symbols can be calculated as
Figure BDA0003959091350000084
And calculating the frequency domain phase offset to obtain a timing error estimation result.
Step 5, loop filtering smoothing is carried out according to the timing error estimation result, the timing synchronous time domain delay is obtained by calculation, and the calculation formula of the filter coefficient tap position of the timing error compensation is as follows
Figure BDA0003959091350000085
wherein />
Figure BDA0003959091350000086
For timing error estimation, f us And for the up-sampling multiple of the root cosine filter symbol, the calculated result corresponds to the ROM storage address, and the filter coefficient output by the index is used for subsequent compensation processing.
Step 6, storing the filter coefficients corresponding to different timing error estimation values in ROM, wherein the coefficients are binary numbers with the number of N=64 and the bit width of 8 bits. And (5) dynamically controlling the filter coefficients output by the ROM by taking the tap positions of the filter output by the step (5) as ROM index addresses.
And 7, inputting the filter coefficient obtained by the index ROM into a polyphase filter module, convoluting the filter coefficient with a sampling result of a received signal in a time domain, and realizing data rate conversion while finishing timing error compensation of the sampled signal, wherein the results before and after the timing error compensation are shown in fig. 4.
The simulation results of the method are as follows:
1. conditions (conditions)
Signal modulation mode: QPSK
FFT point number: 64
Root raised cosine filter roll-off factor: 0.25
Up-sampling multiple of root cosine filter symbol: 112
2. Analysis of results
The method completes timing synchronization error estimation and compensation under the conditions, and the result is shown in fig. 4. The left side is the constellation diagram before the timing synchronization error compensation, and the right side is the constellation diagram after the timing synchronization error compensation. Obviously, the method reduces errors generated in the signal transmission process to a certain extent, and improves the signal sampling effect to a certain extent.
In short, the invention calculates the phase delay error by carrying out timing error estimation on the high-speed communication transmission data and sends the phase delay error into the filter, thereby completing the compensation of the time domain timing error. Aiming at the problem that the traditional O & M timing synchronization algorithm is limited in hardware implementation in a high-speed and large-bandwidth transmission system, the invention adopts an open-loop IQ two-path parallel and symbol non-integer multiple sampling design, each path of IQ serially processes sample data, performs timing error compensation on a time domain, avoids DFT and IDFT operation, and simultaneously further reduces the occupation of hardware resources.
The above embodiments are provided to illustrate the technical concept and features of the present invention and are intended to enable those skilled in the art to understand the content of the present invention and implement the same, and are not intended to limit the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.

Claims (6)

1. The serial high-efficiency communication time domain O & M timing synchronization method is characterized by comprising the following steps of:
step 1, sampling signals, completing frame synchronization of sampled data, and performing timing synchronization processing on a complex sequence after frame synchronization to obtain a complex timing synchronization sequence;
step 2, performing I, Q two paths of serial input timing processing on the complex timing synchronization sequence, multiplying each path by a binary symbol form according to bits, accumulating and summing to obtain a square value, and summing the results obtained from I, Q paths to obtain a receiving signal module;
step 3, the signal envelope value is respectively sent into I, Q two paths, and each path of signal is respectively connected with a corresponding rotation factor W nI and Wnq Multiplying and summing to finish DFT operation;
step 4, timing error estimation is carried out by utilizing the real part and the imaginary part of the signal after DFT operation, and the frequency domain phase offset, namely the timing error estimation result, is calculated;
step 5, loop filtering smoothing is carried out according to the timing error estimation result, timing synchronization time domain delay is calculated, and the time domain delay corresponds to the tap position of the filter for subsequent processing;
step 6, storing filter coefficients corresponding to different timing error estimation results in ROM, taking the tap position of the filter output in step 5 as ROM index address, and dynamically controlling ROM to output the filter coefficients;
and 7, inputting the filter coefficient output by the ROM into a multiphase filter module to finish the timing error compensation of the sampling signal.
2. The method for synchronizing time domain O & M timing in serial and efficient communication according to claim 1, wherein step 1 specifically comprises sampling signals by using an analog-to-digital conversion module connected to an FPGA baseband board, and performing frame synchronization on the sampled signals in the baseband board, wherein the output result includes a pilot sequence extracted from the received sampled data, and the sequence is used for timing error estimation.
3. The method of claim 2, wherein the DFT operation in step 3 uses a sampling rate satisfying the nyquist sampling theorem, the signal is in complex form, and the DFT operation is expressed as:
Figure FDA0003959091340000021
wherein ,xk Is the receiving signal module; x is X m Is x k K is the sample number, L is the symbol accumulation length, and m is the sample segment number; I. the Fourier transform rotation factors of the Q paths are respectively represented as W nI ＝Im[e -j2kπ/N] and Wnq ＝Re[e -j2kπ/N ]The method comprises the steps of carrying out a first treatment on the surface of the N is the number of DFT points.
4. A serial, efficient communications time domain O as recited in claim 3&M timing synchronization method, characterized in that in step 4, X m The real part of (2) corresponds to the sampling point modulus and the twiddle factor W nI Product of X m The imaginary part of (2) corresponds to the sampling point modulus and the twiddle factor W nq The product of the two paths of the sign accumulation length L and I, Q is processed in series respectively; x is X m The real part and the imaginary part of (a) are respectively expressed as:
Figure FDA0003959091340000022
Figure FDA0003959091340000023
wherein Re [ X ] m] and Im[Xm ]Respectively represent X m Real and imaginary parts of I k and Qk The real part and the imaginary part of the received sample signal respectively;
the DFT operation is represented by the real part and the imaginary part of the received signal, and the timing error estimated value of L symbols is
Figure FDA0003959091340000024
Wherein the error estimate
Figure FDA0003959091340000025
Is an unbiased estimate of epsilon. />
5. The method of time domain O & M timing synchronization for serial communication of claim 4, wherein in step 5, the filter coefficient tap positions for timing error compensation are calculated by
Figure FDA0003959091340000031
wherein ,
Figure FDA0003959091340000032
for timing error estimation, f us Is the up-sampling multiple of the root cosine filter symbol.
6. The serial high-efficiency communication time domain O & M timing synchronization method according to claim 5, wherein the specific mode of step 7 is that the filter coefficient and the signal sample point are convolved in the time domain, the filter adopts a multiphase structure design, and the difference of the extraction and interpolation multiples of the multiphase filter is utilized to realize the signal timing error compensation, and meanwhile, the data rate conversion is completed.
CN202211474592.1A 2022-11-23 2022-11-23 Time domain O & M timing synchronization method for serial high-efficiency communication Pending CN115996162A (en)

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Publication number Priority date Publication date Assignee Title
CN117792338A (en) * 2024-02-27 2024-03-29 南京朗立微集成电路有限公司 Filter and design method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117792338A (en) * 2024-02-27 2024-03-29 南京朗立微集成电路有限公司 Filter and design method thereof

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