CN106230759B - Point-to-multipoint high-speed burst modulator, demodulator and modulation-demodulation device - Google Patents
Point-to-multipoint high-speed burst modulator, demodulator and modulation-demodulation device Download PDFInfo
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- CN106230759B CN106230759B CN201610832896.9A CN201610832896A CN106230759B CN 106230759 B CN106230759 B CN 106230759B CN 201610832896 A CN201610832896 A CN 201610832896A CN 106230759 B CN106230759 B CN 106230759B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/20—Modulator circuits; Transmitter circuits
- H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
- H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
- H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
- H04L27/2273—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals associated with quadrature demodulation, e.g. Costas loop
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The invention discloses a point-to-multipoint high-speed burst modulator, a demodulator and a modulation and demodulation device, and relates to the field of communication. The modulation and demodulation device comprises a digital optical fiber interface processing unit, a high-speed burst modulator, a D/A converter, an active low-pass filter, a local oscillation module, an IQ modulator, an IQ demodulator, a numerical control AGC, an A/D converter, a high-speed burst demodulator and a hardware phase-locked loop. The invention adopts the fast synchronization technology of peak search and interpolation, the fast time domain channel estimation technology and the frequency domain zero forcing equalization technology, so that the multi-node and high-capacity point-to-multipoint modem can estimate the channel characteristics in real time, greatly shorten the synchronization and equalization time, reduce the overhead of the system and further improve the service throughput of the point-to-multipoint modem. The invention also has the advantages of simple circuit, small volume, reliable performance and the like.
Description
Technical Field
The invention relates to a point-to-multipoint high-speed burst modulation and demodulation device in the field of communication, in particular to a point-to-multipoint modulation and demodulation device which is short in burst communication time, capable of estimating channel characteristics in real time, strong in multipath resistance and applicable to a slow time-varying channel.
Background
The traditional point-to-multipoint modulation and demodulation device is realized by adopting a mode of loop synchronization and time domain equalization, has long synchronization time, slow convergence of an equalizer, incapability of estimating the change characteristic of a channel in real time and limited anti-multipath capability, and can not be applied to a slow time-varying channel environment. When the number of communication nodes is large and the communication capacity of each node is large, the burst communication time of each communication node is very short, and if the modulation and demodulation device is still adopted, the synchronous loop and the time domain equalizer cannot be converged due to insufficient reserved protection time, and the modulation and demodulation device cannot work normally.
Disclosure of Invention
The present invention aims to provide a high-speed burst modem device with strong anti-multipath capability, which can estimate the channel characteristics in real time, and can synchronize and equalize quickly, aiming at the defects of the point-to-multipoint modem device. The invention also has the characteristics of simple circuit, small volume, reliable performance and the like.
The purpose of the invention is realized as follows: a point-to-multipoint high speed burst modulator comprising an RS error correction encoder 15, a cache blocking unit 16, a constellation mapper 17, a preamble insertion unit 18 and a square root digital shaping unit 19;
the RS error correction encoder 15 is configured to receive external valid service data, a data enable and a coding clock, perform forward error correction coding on the valid service data under the control of the coding clock to obtain coded valid service data, and send the coded valid service data and the data enable to the cache blocking unit 16 respectively;
the cache blocking unit 16 is configured to block the encoded effective service data to obtain blocked data, and send the blocked data and the data enable to the constellation mapper 17 respectively;
the constellation mapper 17 is configured to perform constellation mapping on the partitioned data to obtain an I-path constellation symbol and a Q-path constellation symbol, and send the I-path constellation symbol, the Q-path constellation symbol, and the data enable to the preamble insertion unit 18, respectively;
the preamble insertion unit 18 is configured to insert preamble sequences for synchronization into the constellation symbols of the I path and the constellation symbols of the Q path, respectively, to form complete burst frames of the I path and burst frames of the Q path in a one-to-one correspondence manner, and send the burst frames of the I path, the burst frames of the Q path and data enable to the square root digital forming unit 19, respectively;
the square root digital forming unit 19 is configured to perform square root digital forming processing on the I-path burst frame and the Q-path burst frame respectively to obtain an I-path burst frame and a Q-path burst frame after forming processing, and output the I-path burst frame and the Q-path burst frame after forming processing respectively.
A point-to-multipoint high speed burst demodulator includes a digital matched filter 20, a cubic interpolator 21, a peak search synchronizer 22, a phase tracking module 26, a constellation demapping module 27 and an RS decoder module 28,
the digital matched filter 20 is configured to receive an I-path zero intermediate frequency digital signal, a Q-path zero intermediate frequency digital signal, and a demodulation clock, which are input from the outside, respectively, perform matched filtering on the I-path zero intermediate frequency digital signal and the Q-path zero intermediate frequency digital signal under the control of a decoding clock, and equally divide the filtered I-path signal and the filtered Q-path signal into two paths, one path is sent to the peak search synchronizer 22, and the other path is sent to the cubic interpolator 21; the I path of zero intermediate frequency digital signal and the Q path of zero intermediate frequency digital signal both comprise leader sequences;
the peak search synchronizer 22 is configured to calculate a cross-correlation value by using the filtered I-path signal and the filtered Q-path signal, find a maximum point index of a symbol sampling value by searching a cross-correlation peak, generate a data valid enable according to the maximum point index, and then send both the maximum point index and the data valid enable to the cubic interpolator 21;
the cubic interpolator 21 is configured to interpolate an I-path optimal value and a Q-path optimal value respectively according to the buffered filtered I-path signal, the filtered Q-path signal, the maximum point index, and the data enable, and then send the I-path optimal value, the Q-path optimal value, and the data enable to the phase tracking module 26 respectively;
the phase tracking module 26 is configured to perform cross-correlation calculation on the I-path optimal value and the Q-path optimal value according to the effective enable of the data to obtain residual phase offsets, perform corresponding correction respectively, and send the corrected I-path signal, Q-path signal, and the effective enable of the data to the constellation demapping module 27 respectively;
the constellation demapping module 27 is configured to perform demapping on the corrected I-path signals and the corrected Q-path signals respectively according to the data valid enable, so as to convert the signals into serial data streams in a one-to-one correspondence manner, and send the serial data streams and the data valid enable to the RS decoder module 28 respectively;
the RS decoder module 28 is configured to perform forward error correction decoding on the serial data stream and enable the decoded data and the data to be output separately.
The system also comprises a fast time domain channel estimation module 23, a fast Fourier transform module 24 and a frequency domain zero forcing equalization module 25;
the cubic interpolator 21 is configured to interpolate an I-path optimal value and a Q-path optimal value respectively according to the buffered filtered I-path signal, the filtered Q-path signal, the maximum point index, and the data enable, and then send the I-path optimal value, the Q-path optimal value, and the data enable to the fast time domain channel estimation module 23 respectively;
the fast time domain channel estimation module 23 is configured to respectively send the channel parameters of the I path, the channel parameters of the Q path, and the data effective enable to the fast fourier transform module 24 after respectively fast estimating the channel parameters of the I path and the channel parameters of the Q path through the preamble sequence;
the fast fourier transform module 24 converts the channel parameters of the I path and the channel parameters of the Q path into frequency domain data of the I path and frequency domain data of the Q path in a one-to-one correspondence manner, and then effectively enables the frequency domain data of the I path, the frequency domain data of the Q path and the data to be respectively sent to the frequency domain zero-forcing equalization module 25;
the frequency domain zero-forcing equalization module 25 respectively completes the frequency domain equalization of the frequency domain data of the path I and the frequency domain data of the path Q by using a correction algorithm of the zero-forcing equalization, and respectively sends the equalized frequency domain data of the path I, the equalized frequency domain data of the path Q and the effective enabling of the data into the phase tracking module 26;
the phase tracking module 26 is configured to perform inverse fast fourier transform on the equalized I-path frequency domain data and the equalized Q-path frequency domain data, perform cross-correlation on the inverse-transformed I-path frequency domain data and the inverse-transformed Q-path frequency domain data to calculate a residual phase offset and perform corresponding correction, and effectively enable the corrected I-path data, the corrected Q-path data, and the corrected data to be sent to the constellation demapping module 27.
A point-to-multipoint high-speed burst modulation and demodulation device comprises a digital optical fiber interface processing unit 1, a high-speed burst modulator 2, a D/A converter 3, a first active low-pass filter 4, an IQ modulator 5, an up-conversion local oscillator module 6, a numerical control AGC7, an IQ demodulator 8, a down-conversion local oscillator module 9, a second active low-pass filter 10, an A/D converter 11, a high-speed burst demodulator 12 and a hardware phase-locked loop 13;
the digital optical fiber interface processing unit 1 is used for separating high-speed optical fiber data streams input from the outside, and respectively outputting the separated effective service data and data to the high-speed burst modulator 2 after enabling the effective service data and the data; the system is also used for merging the received service data with the service data enable to obtain a new high-speed optical fiber data stream;
the high-speed burst modulator 2 is used for sequentially carrying out forward error correction coding, buffering blocking, constellation mapping, leading insertion and square root forming processing on effective service data under the control of a coding clock to generate I baseband digital modulation signals and Q baseband digital modulation signals and then respectively outputting the I baseband digital modulation signals and the Q baseband digital modulation signals to the D/A converter 3;
the D/A converter 3 is used for converting the 2-path baseband digital modulation signals into 2-path analog signals respectively under the control of an analog-to-digital conversion clock and outputting the 2-path analog signals to the first active low-pass filter 4;
the first active low-pass filter 4 is used for filtering out the out-of-band spurious of the 2-path analog signals respectively and outputting the filtered out-of-band spurious to the IQ modulator 5;
the IQ modulator 5 is used for modulating the 2 paths of analog signals with the out-of-band spurious removed and the carrier generated by the up-conversion local oscillation module 6 respectively to obtain analog intermediate frequency output signals and then outputting the analog intermediate frequency output signals;
the digital control AGC7 is used for amplifying an externally received analog intermediate frequency input signal to a preset level and then sending the amplified analog intermediate frequency input signal to the IQ demodulator 8;
the IQ demodulator 8 is configured to mix the amplified analog intermediate frequency input signal with a local oscillation signal generated by the down-conversion local oscillation module 9 to obtain an I-path signal and a Q-path signal, and send the signals to the second active low-pass filter 10;
the second active low-pass filter 10 is used for filtering the mirror image and the out-of-band spurious of the I path signal and the Q path signal respectively, and outputting the filtered mirror image and the filtered out-of-band spurious to the a/D converter 11;
the a/D converter 11 is configured to perform analog-to-digital sampling on the I-path signal and the Q-path signal after filtering the image and the out-of-band spurious signal under the control of the digital-to-analog conversion clock;
the high-speed burst demodulator 12 is configured to perform burst demodulation on the sampled I-path signal and Q-path signal respectively under the control of a decoding clock to obtain service data and service data enable, and send the output service data and service data enable to the digital optical fiber interface processing unit 1 respectively;
the hardware phase-locked loop 13 is configured to receive an external reference clock, phase-lock and frequency-multiply the reference clock to obtain an encoding clock, a decoding clock, an analog-to-digital conversion clock, and a digital-to-analog conversion clock, and then send the encoding clock, the decoding clock, the analog-to-digital conversion clock, and the digital-to-analog conversion clock to the high-speed burst modulator 2, the high-speed burst demodulator 12, the D/a converter 3, and the a/D converter 11 in a one-to-one correspondence manner.
The physical interface of the digital optical fiber interface processing unit 1 is a single-mode or multi-mode digital optical fiber interface.
Compared with the background technology, the invention has the following advantages:
1. the invention can estimate the channel change characteristics in real time. Since the known preamble sequence is inserted into the high-speed burst modulator 2 and the frame structure is adopted, and the high-speed burst demodulator 12 can estimate the real-time variation characteristic of the channel by using the known information, the point-to-multipoint high-speed modem apparatus can be applied in the slow time-varying channel environment.
2. The invention has the capability of fast synchronization and fast equalization. Since the peak search synchronizer 22 in the high-speed burst demodulator 12 adopts the fast peak search algorithm, fast synchronization can be realized in tens of symbol levels, and the frequency domain zero-forcing equalization module 25 adopts the modified zero-forcing equalization algorithm, and the result of the fast time domain channel estimation module 23 can be utilized to realize fast equalization of the received signal.
3. The invention has stronger anti-multipath capability. By flexibly inserting different multipath resistant preamble sequences in the high-speed burst modulator 2, multipath of the order of microseconds can be resisted.
4. The invention is manufactured by adopting large-scale field programmable logic devices and has the advantages of simple circuit structure, flexible configuration, small volume and reliable performance.
Drawings
Fig. 1 is an electrical schematic block diagram of a high-speed burst modem apparatus of the present invention.
Fig. 2 is an electrical schematic block diagram of an embodiment of the high-speed burst modulator 2 of the present invention.
Fig. 3 is an electrical schematic block diagram of an embodiment of high-speed burst demodulator 12 of the present invention.
Detailed Description
Referring to fig. 1 to 3, the present invention is composed of a digital optical fiber interface processing unit 1, a high-speed burst modulator 2, a D/a converter 3, a first active low pass filter 4, an IQ modulator 5, an up-conversion local oscillation module 6, a numerical control AGC7, an IQ demodulator 8, a down-conversion local oscillation module 9, a second active low pass filter 10, an a/D converter 11, a high-speed burst demodulator 12, a hardware phase-locked loop 13, and a power supply 14. Fig. 1 is an electrical schematic block diagram of a high-speed burst modem apparatus according to the present invention, which is connected to the circuit of fig. 1.
The digital optical fiber interface processing unit 1 separates the high-speed optical fiber data stream input by the external interface A, and the separated effective service data and data enable are output to the high-speed burst modulator 2; the high-speed burst modulator 2 outputs two paths of baseband digital modulation signals by adopting data buffering and blocking and then adopting a mode of inserting a preamble and forming a square root; 2, converting the digital modulation signal of the baseband into 2 paths of analog signals after passing through a D/A converter 3; the 2-path analog signals are sent to a first active low-pass filter 4 to filter out-of-band spurious, and output signals of the analog signals and a carrier generated by an up-conversion local oscillation module 6 are modulated to analog intermediate-frequency output signals output by a port C through an IQ modulator 5; the digital control AGC7 amplifies an analog intermediate frequency input signal received by a port D to a constant level and then sends the amplified analog intermediate frequency input signal to an IQ demodulator 8, the amplified analog intermediate frequency input signal is mixed with a local oscillation signal generated by a down-conversion local oscillation module 9 and then sent to a second active low-pass filter 10, after image and out-of-band spurious are filtered, an output signal is sent to an A/D converter 11 for analog-to-digital sampling, the sampled signal is sent to a high-speed burst demodulator 12 for burst demodulation, finally, the output service data and service data enable energy are sent to a digital optical fiber interface processing unit 1 for processing, and then a high-speed optical fiber data stream is output by a port B; the reference clock is sent to a hardware phase-locked loop 13 for phase locking and frequency multiplication, and then sent to the high-speed burst modulator 2, the high-speed burst demodulator 12, the D/A converter 3 and the A/D converter 11 for providing a processing clock signal for the high-speed burst modulator, the high-speed burst demodulator and the D/A converter.
The digital optical fiber interface processing unit 1 is manufactured by using stratxvi GX chips manufactured by Altera corporation in the united states. The D/a converter 3 is fabricated using an AD9788 chip of AD corporation, usa. The first active low-pass filter 4 and the second active low-pass filter 10 are manufactured by HMC900LP of Hittite corporation. The up-conversion local oscillator module 6 and the down-conversion local oscillator module 9 are manufactured by a Si4133 chip of MINI corporation in usa. The IQ modulator 5 is manufactured by the company TI TRF 370417. The IQ demodulator 8 is manufactured by LT5575 of LINEAR corporation. The a/D converter 11 is manufactured by AD9643 of AD corporation. The hardware phase locked loop 13 is made by an AD9518 chip manufactured by AD corporation.
The high-speed burst modulator 2 of the present invention is used for carrying out error correction coding on the effective data information separated from the digital optical fiber interface processing unit, and then carrying out preamble insertion and digital forming, thereby realizing the band-limited transmission of signals. It is composed of RS error correction encoder 15, cache block unit 16, constellation mapper 17, preamble insertion unit 18 and square root digital shaping unit 19, fig. 2 is an electrical schematic diagram of high speed burst modulator 2 of the present invention, and the embodiment connects the lines according to fig. 2.
The effective service data separated from the digital optical fiber interface processing unit 1 is sent to an RS error correction encoder 15 to complete forward error correction encoding and then sent to a high-speed buffer block unit 16; the cache blocking unit 16 blocks the continuous service data and sends the continuous service data to the constellation mapper 17; the constellation mapper 17 sends the constellation mapping of the signal to the preamble insertion unit 18; the preamble insertion unit 18 completes the formation of a burst frame after inserting a preamble sequence for synchronization into the signal; then the signal is sent to a square root digital shaping unit 19 to complete the square root digital shaping of the signal, thereby improving the utilization rate of the frequency spectrum; after the digital shaping is finished, outputting the digital shaping to a D/A converter 3; the hardware phase-locked loop 13 locks the phase of the external reference clock and multiplies the frequency of the external reference clock, and then sends the external reference clock to the RS error correction encoder 15 to provide an encoding clock signal for the RS error correction encoder. The RS error correction encoder 15, the cache blocking unit 16, the constellation mapper 17, the preamble insertion unit 18, and the square root digital shaping unit 19 are all fabricated by the StratixVI GX series FPGA chip manufactured by Altera corporation of America.
The high-speed burst demodulator 12 of the present invention is used to complete the optimal reception of the zero-if received signal, complete the RS decoding of the signal, and enable the effective service data and service data to the digital optical fiber interface processing unit 1. The device comprises a digital matched filter 20, a cubic interpolator 21, a peak search synchronizer 22, a fast time domain channel estimation module 23, a fast Fourier transform module 24, a frequency domain zero-forcing equalization module 25, a phase tracking module 26, a constellation demapping module 27 and an RS decoder module 28. Fig. 3 is an electrical schematic diagram of the high-speed burst demodulator 12 of the present invention, an embodiment of which is connected to the lines of fig. 3.
The zero intermediate frequency digital sampling signal output by the A/D converter 11 is sent to a digital matched filter 20 to complete the matched filtering of the signal and then divided into two paths, one path is sent to a peak value searching synchronizer 22, and the module finds the maximum point index of a symbol sampling value by searching the peak value of the signal cross-correlation and sends the maximum point index to a cubic interpolator 21; the cubic interpolator 21 interpolates the best point of the signal by using the cached matched data and the maximum point index, and then sends the best point to the fast time domain channel estimation module 23, and the module quickly estimates channel parameters by leading a known sequence and then sends the channel parameters to the fast Fourier transform module 24; the fast fourier transform module 24 converts the cached matched data and the channel parameters into frequency domain data and sends the frequency domain data to the frequency domain zero forcing equalization module 25; the frequency domain zero forcing equalization module 25 completes the frequency domain equalization of the received data by using a correction algorithm of the zero forcing equalization, and the equalized data is sent to the phase tracking module 26; the phase tracking module 26 completes the inverse fast fourier transform of the data, and performs cross-correlation on the inverse transformed data to calculate the residual phase offset and perform corresponding correction, and the corrected data is sent to the constellation demapping module 27; the constellation demapping module 27 performs demapping of the data stream, converts the data stream into a serial data stream, and sends the serial data stream to the RS decoder module 28; the RS decoder module 28 completes the forward error correction decoding of the data and sends the data to the digital optical fiber interface processing unit 1. The embodiment digital matched filter 20, the cubic interpolator 21, the peak search synchronizer 22, the fast time domain channel estimation module 23, the fast fourier transform module 24, the frequency domain zero forcing equalization module 25, the phase tracking module 26, the constellation demapping module 27, and the RS decoder module 28 are all fabricated from the stratix vi GX series FPGA chips manufactured by Altera corporation of america.
The hardware phase-locked loop 13 of the invention is used for receiving a reference clock signal of a clock input port E through an input port 1, after phase-locked frequency multiplication, an output port 2 of the hardware phase-locked loop provides a clock signal for a high-speed burst modulator 2, an output port 3 of the hardware phase-locked loop provides a clock signal for a D/A converter 3, an output port 4 of the hardware phase-locked loop provides a clock signal for a high-speed burst demodulator 12, and an output port 5 of the hardware phase-locked loop provides a clock signal for an A/D converter 11.
The power supply 14 of the present invention provides the dc voltage of the entire modem, which is provided by a general dc power supply module, and its output + V is 3.3V.
The invention has the following brief working principle:
at a transmitting end, a digital optical fiber interface processing unit 1 separates a high-speed optical fiber data stream input by an external interface A, the separated effective service data stream and data can be output to a high-speed burst modulator 2, the high-speed burst modulator adopts data buffer blocking and then outputs two paths of baseband digital modulation signals by adopting a mode of inserting preamble and square root forming, 2 paths of baseband digital modulation signals are converted into 2 paths of analog signals after passing through a D/ A converter 3, 2 paths of analog signals are sent to an active low-pass filter 4 to filter out-of-band spurious signals, and output signals and carrier waves generated by an up-conversion local oscillator module 6 are modulated to analog intermediate-frequency output signals output by a C port through an IQ modulator 5.
At the receiving end, the digital AGC7 amplifies the analog intermediate frequency input signal received by the port D to a constant level and sends it to the IQ demodulator 8, which mixes it with the local oscillation signal generated by the down-conversion local oscillation module 9 and sends it to the active low pass filter 10, after filtering out the image and out-of-band spurious, outputs the signal and sends it to the a/D converter 11 for analog-to-digital sampling, the sampled signal is sent to the high speed burst demodulator 12 for burst demodulation, and finally the output service data and service data enable are sent to the digital optical fiber interface processing unit 1 for processing, and the port B outputs the high speed optical fiber data stream.
The installation structure of the invention is as follows:
all circuit devices in the figures 1, 2 and 3 are arranged on a printed board with the size of 1 block, length, width and height of 220, 115 and 20mm, and three cable sockets, namely an A optical fiber data stream input and output socket, a simulation intermediate frequency output signal port, a simulation intermediate frequency input signal port, a reference clock input port and an external power supply input socket, are arranged on the circuit board.
Claims (5)
1. A point-to-multipoint high speed burst modulator comprising an RS error correction encoder (15), a constellation mapper (17) and a square root digital shaping unit (19), characterized by: further comprising a cache blocking unit (16) and a preamble insertion unit (18);
the RS error correction encoder (15) is used for respectively receiving external effective service data, a data enable and an encoding clock, carrying out forward error correction encoding on the effective service data under the control of the encoding clock to obtain encoded effective service data, and respectively sending the encoded effective service data and the data enable into the high-speed buffer blocking unit (16);
the high-speed buffer blocking unit (16) is used for blocking the coded effective service data to obtain blocked data, and respectively sending the blocked data and the data enable to the constellation mapper (17);
the constellation mapper (17) is used for performing constellation mapping on the partitioned data to obtain an I path of constellation symbols and a Q path of constellation symbols, and respectively sending the I path of constellation symbols, the Q path of constellation symbols and the data enable to a preamble insertion unit (18);
the leading insertion unit (18) is used for inserting leading sequences for synchronization in the I path constellation symbols and the Q path constellation symbols respectively, forming complete I path burst frames and Q path burst frames in a one-to-one correspondence mode, and sending the I path burst frames, the Q path burst frames and the data enable to the square root digital forming unit (19) respectively;
and the square root digital forming unit (19) is used for respectively carrying out square root digital forming processing on the I path burst frame and the Q path burst frame to obtain an I path burst frame and a Q path burst frame which are subjected to forming processing, and respectively outputting the I path burst frame and the Q path burst frame which are subjected to forming processing.
2. A point-to-multipoint high speed burst demodulator comprising a digital matched filter (20), a phase tracking module (26), a constellation demapping module (27) and an RS decoder module (28), characterized by: a cubic interpolator (21) and a peak search synchronizer (22);
the digital matched filter (20) is used for respectively receiving an I path of zero intermediate frequency digital signals, a Q path of zero intermediate frequency digital signals and a demodulation clock which are input from the outside, respectively carrying out matched filtering on the I path of zero intermediate frequency digital signals and the Q path of zero intermediate frequency digital signals under the control of a decoding clock, and equally dividing the filtered I path of signals and the filtered Q path of signals into two paths, wherein one path of signals is sent to the peak search synchronizer (22), and the other path of signals is sent to the cubic interpolator (21); the I path of zero intermediate frequency digital signal and the Q path of zero intermediate frequency digital signal both comprise leader sequences;
the peak search synchronizer (22) is used for calculating a cross-correlation value by utilizing the filtered I path signal and the filtered Q path signal, finding a maximum point index of a symbol sampling value by searching a cross-correlation peak value, generating data effective enable according to the maximum point index, and then sending the maximum point index and the data effective enable to the cubic interpolator (21);
the cubic interpolator (21) is used for respectively interpolating an I path optimal value and a Q path optimal value according to the cached filtered I path signal, the filtered Q path signal, the maximum point index and the data effective enable, and then respectively sending the I path optimal value, the Q path optimal value and the data effective enable to the phase tracking module (26);
the phase tracking module (26) is used for performing cross-correlation calculation on the optimal value of the path I and the optimal value of the path Q according to the effective enabling of the data to obtain residual phase offsets, performing corresponding correction respectively, and sending the corrected signal of the path I, the corrected signal of the path Q and the effective enabling of the data to the constellation demapping module (27) respectively;
the constellation demapping module (27) is used for demapping the corrected I-path signals and the corrected Q-path signals respectively according to the data effective enabling to convert the signals into serial data streams in a one-to-one correspondence mode, and sending the serial data streams and the data effective enabling to the RS decoder module (28) respectively;
and the RS decoder module (28) is used for completing forward error correction decoding of the serial data stream and respectively outputting decoded data and data effective enable.
3. A point-to-multipoint high speed burst demodulator as defined in claim 2, wherein: the system also comprises a fast time domain channel estimation module (23), a fast Fourier transform module (24) and a frequency domain zero-forcing equalization module (25);
the cubic interpolator (21) is used for respectively interpolating an optimal value of the I path and an optimal value of the Q path according to the cached filtered signals of the I path, the filtered signals of the Q path, the maximum point index and the data effective enable, and then respectively sending the optimal value of the I path, the optimal value of the Q path and the data effective enable to the fast time domain channel estimation module (23);
the fast time domain channel estimation module (23) is used for respectively and fast estimating channel parameters of an I path and channel parameters of a Q path through a leader sequence, and then respectively sending the channel parameters of the I path, the channel parameters of the Q path and data effective enabling to the fast Fourier transform module (24);
the fast Fourier transform module (24) respectively converts the channel parameters of the I path and the channel parameters of the Q path into frequency domain data of the I path and the frequency domain data of the Q path in a one-to-one correspondence manner, and then the frequency domain data of the I path, the frequency domain data of the Q path and the data are respectively sent to the frequency domain zero-forcing equalization module (25) in an effective enabling manner;
the frequency domain zero forcing equalization module (25) respectively completes the frequency domain equalization of the I path of frequency domain data and the Q path of frequency domain data by utilizing a correction algorithm of the zero forcing equalization, and respectively sends the equalized I path of frequency domain data, the equalized Q path of frequency domain data and the data effective enable to the phase tracking module (26);
the phase tracking module (26) is used for respectively carrying out fast Fourier inverse transformation on the equalized I-path frequency domain data and the equalized Q-path frequency domain data, respectively carrying out cross correlation on the inversely transformed I-path frequency domain data and the Q-path frequency domain data to calculate residual phase offset and correspondingly correct the residual phase offset, and respectively sending the corrected I-path data, the corrected Q-path data and the data to the constellation demapping module (27) in an effective enabling mode.
4. The utility model provides a high-speed burst modem device of point-to-multipoint, includes digital optical fiber interface processing unit (1), D/A converter (3), first active low pass filter (4), IQ modulator (5), up-conversion local oscillator module (6), numerical control AGC (7), IQ demodulator (8), down-conversion local oscillator module (9), second active low pass filter (10), A/D converter (11) and hardware phase-locked loop (13), its characterized in that: further comprising a high speed burst modulator (2) according to claim 1 and a high speed burst demodulator (12) according to claim 2 or 3;
the digital optical fiber interface processing unit (1) is used for separating high-speed optical fiber data streams input from the outside, and respectively outputting the separated effective service data and the data to the high-speed burst modulator (2) after enabling; the system is also used for merging the received service data with the service data enable to obtain a new high-speed optical fiber data stream;
the high-speed burst modulator (2) is used for sequentially carrying out forward error correction coding, buffer blocking, constellation mapping, leading insertion and square root forming processing on effective service data under the control of a coding clock to generate I baseband digital modulation signals and Q baseband digital modulation signals and then respectively outputting the I baseband digital modulation signals and the Q baseband digital modulation signals to the D/A converter (3);
the D/A converter (3) is used for converting the 2-path baseband digital modulation signals into 2-path analog signals respectively under the control of an analog-to-digital conversion clock and outputting the 2-path analog signals to the first active low-pass filter (4);
the first active low-pass filter (4) is used for filtering out the out-of-band spurious of the 2 paths of analog signals respectively and outputting the filtered out-of-band spurious to the IQ modulator (5);
the IQ modulator (5) is used for modulating the 2 paths of analog signals with the out-of-band spurious removed and the carrier generated by the up-conversion local oscillation module (6) respectively to obtain analog intermediate frequency output signals and then outputting the analog intermediate frequency output signals;
the digital control AGC (7) is used for amplifying an externally received analog intermediate frequency input signal to a preset level and then sending the amplified analog intermediate frequency input signal to the IQ demodulator (8);
the IQ demodulator (8) is used for mixing the amplified analog intermediate frequency input signal with a local oscillator signal generated by the down-conversion local oscillator module (9) to obtain an I path signal and a Q path signal and respectively sending the signals to the second active low-pass filter (10);
the second active low-pass filter (10) is used for filtering images and out-of-band spurs of the I path signal and the Q path signal respectively and outputting the images and the out-of-band spurs to the A/D converter (11);
the A/D converter (11) is used for respectively carrying out analog-to-digital sampling on the I path signal and the Q path signal which are subjected to image filtering and out-of-band spurious elimination under the control of a digital-to-analog conversion clock;
the high-speed burst demodulator (12) is used for respectively carrying out burst demodulation on the I-path signal and the Q-path signal after sampling under the control of a decoding clock to obtain service data and service data enable, and respectively sending the output service data and the service data enable to the digital optical fiber interface processing unit (1);
the hardware phase-locked loop (13) is used for receiving an external reference clock, performing phase locking and frequency multiplication on the reference clock to obtain a coding clock, a decoding clock, an analog-to-digital conversion clock and a digital-to-analog conversion clock, and then sending the coding clock, the decoding clock, the analog-to-digital conversion clock and the digital-to-analog conversion clock to the high-speed burst modulator (2), the high-speed burst demodulator (12), the D/A converter (3) and the A/D converter (11) in a one-to-one correspondence mode.
5. A point-to-multipoint high speed burst modem device according to claim 4, wherein said physical interface of said digital fiber interface processing unit (1) is a single mode or multimode digital fiber interface.
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