CN111343125A - Synchronization method for 32APSK modulation system receiver - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
- H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
- H04L27/38—Demodulator circuits; Receiver circuits
- H04L27/3818—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers
- H04L27/3836—Demodulator circuits; Receiver circuits using coherent demodulation, i.e. using one or more nominally phase synchronous carriers in which the carrier is recovered using the received modulated signal or the received IF signal, e.g. by detecting a pilot or by frequency multiplication
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Abstract
The invention provides a synchronization system of a 32APSK modulation system receiver, belonging to the technical field of wireless communication. The method aims to provide a full digital receiver synchronization scheme with high synchronization precision and low algorithm complexity. The invention is realized by the following scheme: the high-speed ADC module performs high-speed sampling on the received intermediate-frequency analog signal, and the digital quadrature down-conversion module completes quadrature down-conversion and low-pass filtering of the intermediate-frequency digital signal to obtain an IQ quadrature signal; the matched filtering module completes matched filtering of a receiving end filter and a sending filter; the bit synchronization module completes the timing synchronization of the signals; the carrier synchronization module extracts local oscillation of the carrier in the same frequency and direction, removes the carrier, and performs phase ambiguity resolution by using phase ambiguity information fed back by the frame synchronization module; the frame synchronization module gives out phase fuzzy information, after carrier synchronization and bit synchronization signals are balanced by the balancing module, the phase fuzzy information is fed back to the carrier synchronization module for phase fuzzy demodulation, and a synchronous bit stream is demodulated and output.
Description
Technical Field
The invention belongs to the field of high-order modulation and demodulation in wireless digital transmission, and particularly relates to a full digital receiver synchronization scheme suitable for a 32APSK modulation system.
Technical Field
With the continuous progress of information technology, more and more new potential applications are rapidly emerging, such as: the system comprises the Internet of things, unmanned driving, high-definition satellite digital televisions, artificial intelligence and the like. While stable operation of these services must be ensured by high-speed and efficient communication systems, with the ever-increasing demand for communication of these devices/applications, the demand for information processing transmission rates is increasing. From shannon's theorem, to increase the information transmission rate, two ways of increasing the transmission bandwidth and increasing the spectrum utilization rate can be adopted. With the increasing of communication devices, various devices need to occupy a certain spectrum bandwidth, so that available spectrum resources become precious. In order to increase the communication capacity of the system and fully utilize limited spectrum resources, researchers have studied many high-order modulation schemes, such as 16QAM, 16APSK, and 32 APSK. Because the traditional rectangular QAM modulation mode has more amplitude than the APSK modulation mode based on amplitude-phase shift keying under the condition of the same modulation order, the linearity of the channel condition is poor, and particularly in a satellite communication system with limited transmitting power. More severe nonlinear distortion may result, degrading the performance of the system. Therefore, 16APSK and 32APSK, especially 32APSK, as signal modulation methods commonly used in the DVB-S2X standard, play an increasingly important role in communication systems, especially satellite communication systems.
In digital communication systems, synchronization is a very critical part, which is a prerequisite for correct demodulation of the signal. The synchronization mainly comprises carrier synchronization and timing synchronization, and the timing synchronization has the main function of keeping the clocks of the receiving and transmitting ends consistent so as to ensure that the receiving end performs sampling and judgment at the optimal time. Bit synchronization can be divided into two ways based on data assistance and non-data assistance depending on whether a special training sequence is utilized or not. The non-data-aided bit synchronization method is divided into a feedback-oriented closed-loop algorithm and a feedforward-oriented open-loop algorithm. Carrier synchronization is also one of the key parts of a communication demodulation system, and early carrier synchronization is to insert pilot frequency information (or called carrier component) at a special position while transmitting useful information, and capture, track and extract the carrier information by directly using a narrow-band filter and a phase-locked loop at a receiving end, which undoubtedly reduces the frequency band utilization rate of a channel. The DVB-S2X standard places higher demands on symbol timing synchronization, frame synchronization and carrier recovery at the demodulation end. In a software radio receiver, the delay of a signal in the propagation process is generally unknown, and the received signal is not synchronized with a local clock signal due to the influence of noise, multipath effects and the like in the transmission process. The performance of bit synchronization directly affects the performance of the whole communication system. The phase error of different bit synchronization algorithms is different, the types of bit synchronization algorithms are various, and the bit synchronization algorithms can be divided into an analog mode, a semi-digital mode and a full-digital mode according to different processing modes. The full-analog bit synchronization implementation technology calculates a bit synchronization timing control signal of an input signal in an analog domain to control a local clock, and performs synchronous sampling on the signal. In a bit synchronization algorithm model in a full digital mode, a fixed local sampling clock cannot guarantee that sampling can be realized at an extreme point of a signal, and the sampling at the extreme point needs to be realized by changing a resampling clock or an input signal. The semi-analog synchronization model extracts the deviation value of the input signal and the local clock by carrying out a series of digital processing on the sampled signal, and the phase of the local clock is changed by the deviation to achieve bit synchronization. The two modes both need to change the phase of the local clock in due time, are not beneficial to the realization of high-speed digital signals and have lower integration degree.
Since the transmission rate of satellite communication is often as high as Gbps, and too slow locking results in the loss of a large amount of effective information, the receiver must complete fast and stable synchronization in a short time. In the digital communication system, as the modulation order is increased, the euclidean distance between adjacent constellation points is reduced sharply, so that the accuracy requirements of timing synchronization and carrier synchronization are much higher than that of an MPSK modulation signal. Thus. An accurate carrier and bit synchronization scheme which is easy to implement in engineering and aims at the 32APSK modulation mode must be found, so that the correct work of the whole communication system is guaranteed.
Disclosure of Invention
The invention aims to provide an effective 32APSK all-digital receiver synchronization scheme with high synchronization precision, low algorithm complexity, easy engineering realization and high efficiency aiming at the 32APSK communication system commonly used in the satellite communication system mentioned in the technical background.
The above object of the present invention can be achieved by the following technical solutions, wherein a synchronization system of a 32APSK modulation system receiver includes: high-speed ADC module, digital quadrature down conversion module, matched filter module, bit synchronization module, carrier synchronization module, balanced module, frame synchronization module and the decoding module that links to each other in order, its characterized in that: the high-speed ADC module performs high-speed sampling on the received intermediate-frequency analog signal, and the digital orthogonal down-conversion module completes orthogonal down-conversion and low-pass filtering of the intermediate-frequency digital signal to obtain I, Q orthogonal signals; the matched filtering module completes matched filtering of a receiving end filter and a sending filter, and improves the demodulation performance of a receiver; the bit synchronization module adopts a Gardner timing synchronization algorithm, and based on an interpolation bit synchronization mode, the bit synchronization module carries out periodic sampling judgment at the middle moment of each code element to recover a binary signal, completes timing sampling and timing synchronization of the signal, ensures the sampling judgment of the signal at the optimal moment, and gives a locking indication signal by using a built-in bit synchronization locking indication module; the carrier synchronization module comprises a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of signal carriers with the same frequency and direction, removes the carriers, gives out carrier synchronization locking indication signals, and performs phase ambiguity resolution by using phase ambiguity information fed back by the frame synchronization module; the equalization module equalizes the signals subjected to carrier synchronization and bit synchronization, and reduces the influence of non-ideal channel transmission characteristics and channel noise on transmission performance; the frame synchronization module carries out frame synchronization on the synchronized signals, gives out phase fuzzy information, feeds the phase fuzzy information back to the carrier synchronization module, and the carrier synchronization module adopts a feedback-oriented closed-loop synchronization algorithm to demodulate the phase fuzzy of the signals, obtains reliable and stable synchronization and gives out a frame synchronization locking indication signal; the decoding module completes the decoding of the signal and outputs the demodulated synchronous bit stream.
Compared with the prior art, the invention has the following beneficial effects:
(1) and the engineering implementation is easy. The invention adopts a circuit form of a synchronous system of a 32APSK modulation system receiver, which is composed of a high-speed ADC module, a digital quadrature down-conversion module, a matched filtering module, a bit synchronization module, a carrier synchronization module, an equalization module, a frame synchronization module and a decoding module which are connected in sequence, and has simple structure and easy engineering realization.
(2) The synchronization precision is high and the convergence is fast. The invention improves the demodulation performance of the receiver through the matched filtering module; the equalization module is used for equalizing the signals subjected to carrier synchronization and bit synchronization, so that the influence of channel transmission characteristics and channel noise on transmission performance is reduced; the data demodulation of the 32APSK modulation signal can be realized under the condition of low signal-to-noise ratio, and the influence of multipath distortion on the signal can be well resisted. The method has the advantages of fast convergence, good synchronization performance and improved synchronization precision; the feedback-oriented closed-loop synchronization algorithm is adopted to obtain reliable and stable synchronization, and simulation shows that the method is quick in synchronization time, does not need to increase any hardware equipment, and has the characteristics of simplicity and remarkable performance improvement.
(3) The algorithm is simple. The invention aims to realize a 32APSK modulation signal demodulation framework. The bit synchronization module adopts a Gardner timing synchronization algorithm to complete timing sampling timing synchronization of the signals, and ensures that the signals are sampled and judged at the optimal time. The high efficiency of the timing synchronization by using the Gardner algorithm is applied to the timing synchronization in a receiver synchronization system, a local sampling clock is not adjusted, and the influence of carrier Doppler is avoided. The sampling value of the optimal sampling moment is obtained by interpolating the input baseband signal, so that the digital code element synchronization is realized, and the time for synchronizing the baseband signal can be greatly saved. The method has the advantages of simple realization, small calculation amount, good demodulation algorithm performance and easy realization. The algorithm has the advantages of fast convergence, good synchronization performance and high synchronization precision. The carrier synchronization module is internally provided with a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of signal carriers in the same frequency and direction, removes the carriers, performs frame synchronization on the synchronized signals by using the frame synchronization module, gives out phase fuzzy information, and feeds back the phase fuzzy information to the carrier synchronization module for demodulating the phase fuzzy of the signals.
The invention is suitable for carrier and bit synchronization in the 32APSK all-digital receiver under various environments.
Drawings
For a more clear understanding of the present invention, the invention will now be described by reference to the accompanying drawings, in which:
fig. 1 is a schematic block diagram of a synchronization scheme of an all-digital receiver with a 32APSK modulation system according to the present invention.
Fig. 2 is a schematic block diagram of the bit synchronization loop of the present invention.
Fig. 3 is a schematic block diagram of the carrier loop of the present invention.
Fig. 4 is a functional block diagram of a second order loop filter of the present invention.
The following will describe the present invention in further detail with reference to the accompanying drawings.
Detailed Description
See fig. 1. In a preferred embodiment described below, a receiver synchronization system with a 32APSK modulation scheme includes: high-speed ADC module, digital quadrature down conversion module, matched filter module, bit synchronization module, carrier synchronization module, balanced module, frame synchronization module and the decoding module that links to each other in order, wherein: the high-speed ADC module performs high-speed sampling on the received intermediate-frequency analog signal, and the digital orthogonal down-conversion module completes orthogonal down-conversion and low-pass filtering of the intermediate-frequency digital signal to obtain I, Q orthogonal signals; the matched filtering module completes matched filtering of a receiving end filter and a sending filter, and improves the demodulation performance of a receiver; the bit synchronization module adopts a Gardner timing synchronization algorithm, and based on an interpolation bit synchronization mode, the bit synchronization module carries out periodic sampling judgment at the middle moment of each code element to recover a binary signal, completes timing sampling and timing synchronization of the signal, ensures the sampling judgment of the signal at the optimal moment, and gives a locking indication signal by using a built-in bit synchronization locking indication module; the carrier synchronization module comprises a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of signal carriers with the same frequency and direction, removes the carriers, gives out carrier synchronization locking indication signals, and performs phase ambiguity resolution by using phase ambiguity information fed back by the frame synchronization module; the equalization module equalizes the signals subjected to carrier synchronization and bit synchronization, and reduces the influence of non-ideal channel transmission characteristics and channel noise on transmission performance; the frame synchronization module carries out frame synchronization on the synchronized signals, gives out phase fuzzy information, feeds the phase fuzzy information back to the carrier synchronization module, and the carrier synchronization module adopts a feedback-oriented closed-loop synchronization algorithm to demodulate the phase fuzzy of the signals, obtains reliable and stable synchronization and gives out a frame synchronization locking indication signal; the decoding module completes the decoding of the signal and outputs the demodulated synchronous bit stream.
The 32APSK modulation system receiver adopts the 32APSK all-digital receiver synchronization, and the synchronization comprises the following steps:
the intermediate frequency analog signal sent to the full digital receiver is firstly subjected to high-speed analog-to-digital (AD) sampling and cosw is utilizedct generates two paths of orthogonal local oscillation signals, the signals are sent to a rear end multiplier to output two paths of orthogonal signals, high frequency components and other frequency components are filtered by a Low Pass Filter (LPF), the signals are sent to a rear end Matched Filtering (MF) module, the matched filtering module carries out matched filtering on digital baseband signals, and filtered baseband signals I are obtained1、Q1(ii) a The bit synchronization module is used for matching and filtering the digital baseband signal I1、Q1Performing bit synchronization, completing timing sampling and timing synchronization of signals, ensuring sampling judgment of the signals at the optimal time, and providing a digital baseband I after bit synchronization2、Q2A lock indication signal; digital baseband signal I after bit synchronization2、Q2The carrier synchronization module sent into the carrier ring carries out carrier synchronization to complete the bit synchronization and the signal I after the carrier synchronization3、Q3Sending the data to a balancing module for digital balancing to reduce the influence of intersymbol interference on the system performance; the equalized signal is sent to a rear-end frame synchronization module for frame synchronization, phase fuzzy information is provided, and the phase fuzzy information is fed back to a carrier synchronization module; the carrier synchronization module performs phase ambiguity resolution operation by using the phase ambiguity information fed back by the frame synchronization module; and the signal after frame synchronization of the frame synchronization module is sent to a decoding module for decoding and judgment to obtain a demodulated bit stream.
The complete timing recovery algorithm consists of a timing error detector, a loop filter, a numerically controlled oscillator and an interpolation filter. The design method of the loop filter is the same as that of the carrier synchronization algorithm, the timing error detector adopts a non-data-aided error detection algorithm (Gardner timing error detection algorithm), and the maximum value of the signal recovered by the interpolation filter is resampled to obtain a synchronous output signal y (kTi).
The value obtained by the interpolation filter is sent to a timing error detector to obtain the phase error tau (n) of the input signal and the local clock, then a loop filter is used for filtering noise and high-frequency components in the input signal and the local clock, and the obtained value e (n) is sent to a numerical control oscillator to calculate the integer sampling time mk and the interpolation point position uk of the interpolation filter, so that the timing output y (kti) is obtained.
The Gardner timing recovery algorithm has symbol rate of x (T) and local fixed clock period Ts of analog input signal T satisfying nyquist's basic sampling law, and becomes discrete signal x (mts) after sampling by local fixed clock period Ts, and after realizing bit synchronization, decimal interpolation point uk will be stabilized on a fixed waveform.
After passing through an interpolation filter module, the Gardner timing recovery algorithm performs sampling and timing error extraction by using a local clock generated by an original voltage-controlled oscillator NCO, and then after passing through a loop filter module LF, the value of a decimal interpolation point uk is calculated and fed back to the decimal interpolation point for controlling interpolation filtering, the phase of an output signal is changed, and the phase of the local clock is adjusted to be consistent with the phase of an input signal to realize synchronization. Therefore, the phase of the input signal after passing through the interpolation filter is consistent with the phase of the local clock, and synchronization is achieved.
See fig. 2. The bit synchronization module adjusts the optimal sampling time according to the calculated timing error, and the process can be realized by correcting an A/D variable sampling clock by using a feedback structure or by an interpolation resampling method. In order to simplify the system calculation and realize the integration of the system, the present embodiment adopts a bit synchronization loop interpolation filtering method. The bit synchronization module mainly comprises a receiving end I connected in series1An output terminal I2Interpolation filter module, timing error detector module, loop filter module and digital voltage control in a carrier loopOscillator NCO module, timing error detector using receiver I1The self phase information of the signal is subjected to iterative subtraction on adjacent symbol points to detect the timing deviation in real time, after the real-time detection of the deviation is finished, the interference is removed through a loop filter based on a phase-locked loop,
in an I/Q channel mixer, a voltage-controlled oscillator NCO shifts an input carrier signal to a frequency point appointed by a frequency control word through the configuration of the frequency control word of the NCO to generate orthogonal sine and cosine samples, calculates a sine and cosine value of a phase according to each sine and cosine wave phase in advance, stores the sine and cosine value of the phase according to a phase angle as an address, continuously accumulates the input frequency word by a phase accumulator under the control of a system clock to obtain a digital phase taking the frequency word as a step, performs initial phase shift by a phase adding module to obtain a current phase to be output, and compensates a timing error by an interpolation filter module interpolation technology to obtain an optimal symbol point.
See fig. 3. The carrier synchronization module comprises: the phase rotation module, the phase discriminator, the loop filter, the digital voltage controlled oscillator NCO and the carrier synchronization locking indication module have the main functions of keeping local carriers at the receiving and transmitting ends in the same frequency and phase, removing the carriers, giving out carrier synchronization locking indication signals and simultaneously utilizing phase fuzzy information fed back by the frame synchronization module to carry out phase fuzzy solution operation.
The phase rotation module receives a baseband signal I after bit synchronization2、Q2According to the phase error extracted by the carrier loop and the phase fuzzy information fed back by the frame synchronization module, the phase compensation and the phase fuzzy operation are carried out, the signal after the phase compensation is sent to a phase discriminator, and the phase discriminator adopts a decision feedback or M power mode to extract the phase error and the residual phase error edThe extracted phase error is sent to a loop filter to ensure that local carriers at a transmitting end and a receiving end keep same frequency and phase, the carrier is removed, and the digital voltage-controlled oscillator NCO outputs an error V of the loop filterdPerforming feedback control, performing phase compensation on the input signal, providing a carrier synchronization locking indication signal by the carrier synchronization locking indication module, repeating the steps, and outputting a baseband signalNumber I3、Q3。
See fig. 4. The loop filter is equivalent to a low-pass filter, and in consideration of system performance and hardware implementation complexity, the embodiment uses a second-order digital loop filter based on control with a proportional branch and an integral branch. The proportional branch has a certain phase locking capability, so the proportional branch is also called as a phase tracking branch, but cannot capture frequency errors; the integral branch circuit is composed of a delay unit for integral operation of input error and an adder, and has certain frequency tracking capability, so the integral branch circuit is also called as a frequency tracking branch circuit. Phase error e generated by phase rotation module to phase discriminatordPerforming digital processing on the phase error edLoop filter parameter C1 and loop filter parameter C generated by proportional branch and integral branch2After being adjusted by an integral link and a proportional link, the delay Z is delayed by a delay unit-1Feeding back to the adder on the frequency tracking branch circuit for addition, and accumulating by the adder at the output end to obtain the filtered phase discrimination error VdAnd then sent to a voltage controlled oscillator NCO module.
What has been described above is merely a preferred embodiment of the present invention. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the principle of the present invention, such as through adjustment of actual structure, and these variations and modifications should be considered as the protection scope of the present invention.
Claims (10)
1. A synchronization system for a 32APSK modulation system receiver, comprising: high-speed ADC module, digital quadrature down conversion module, matched filter module, bit synchronization module, carrier synchronization module, balanced module, frame synchronization module and the decoding module that links to each other in order, its characterized in that: the high-speed ADC module performs high-speed sampling on the received intermediate-frequency analog signal, and the digital orthogonal down-conversion module completes orthogonal down-conversion and low-pass filtering of the intermediate-frequency digital signal to obtain I, Q orthogonal signals; the matched filtering module completes matched filtering of a receiving end filter and a sending filter, and improves the demodulation performance of a receiver; the bit synchronization module adopts a Gardner timing synchronization algorithm, and based on an interpolation bit synchronization mode, the bit synchronization module carries out periodic sampling judgment at the middle moment of each code element to recover a binary signal, completes the timing synchronization of the signal, ensures the sampling judgment of the signal at the optimal moment, and gives a bit synchronization locking indication signal by using a built-in bit synchronization locking indication module; the carrier synchronization module comprises a carrier synchronization module and a carrier synchronization locking indication module, extracts and receives local oscillation of signal carriers with the same frequency and direction, removes the carriers, gives out carrier synchronization locking indication signals, and performs phase ambiguity resolution by using phase ambiguity information fed back by the frame synchronization module; the equalization module equalizes the signals subjected to carrier synchronization and bit synchronization, and reduces the influence of non-ideal channel transmission characteristics and channel noise on transmission performance; the frame synchronization module carries out frame synchronization on the synchronized signals, gives out phase fuzzy information, feeds the phase fuzzy information back to the carrier synchronization module, and the carrier synchronization module adopts a feedback-oriented closed-loop synchronization algorithm to demodulate the phase fuzzy of the signals, obtains reliable and stable synchronization and gives out a frame synchronization locking indication signal; the decoding module completes the decoding of the signal and outputs the demodulated synchronous bit stream.
2. The system for synchronizing a receiver in the 32APSK modulation system according to claim 1, wherein: the 32APSK modulation system receiver is a full digital receiver, the intermediate frequency analog signal sent to the full digital receiver is firstly subjected to high-speed analog-to-digital (AD) sampling, and cosw is utilizedct generates two paths of orthogonal local oscillation signals, the signals are sent to a rear end multiplier to output two paths of orthogonal signals, high frequency components and other frequency components are filtered by a Low Pass Filter (LPF), and the signals are sent to a rear end Matched Filter (MF) module.
3. The system for synchronizing a receiver in the 32APSK modulation system according to claim 2, wherein: the matched filtering module carries out matched filtering on the digital baseband signal to obtain a filtered baseband signal I1、Q1(ii) a The bit synchronization module is used for matching and filtering the digital baseband signal I1、Q1Bit synchronization is carried out, timing sampling and timing synchronization of signals are completed, sampling judgment of the signals at the optimal time is ensured, and the signals are sent toDigital baseband I after bit-out synchronization2、Q2A lock indication signal.
4. A 32APSK modulation system receiver synchronization system according to claim 3, wherein: digital baseband signal I after bit synchronization2、Q2The carrier synchronization module sent into the carrier ring carries out carrier synchronization to complete the bit synchronization and the signal I after the carrier synchronization3、Q3And sending the data to an equalization module for digital equalization, and reducing the influence of intersymbol interference on the system performance.
5. The system for synchronizing a receiver in the 32APSK modulation system according to claim 4, wherein: the equalized signal is sent to a rear-end frame synchronization module for frame synchronization, phase fuzzy information is provided, and the phase fuzzy information is fed back to a carrier synchronization module; the carrier synchronization module performs phase ambiguity resolution operation by using the phase ambiguity information fed back by the frame synchronization module; and the signal after frame synchronization of the frame synchronization module is sent to a decoding module for decoding and judgment to obtain a demodulated bit stream.
6. The system for synchronizing a receiver in the 32APSK modulation system according to claim 1, wherein: and the bit synchronization module adjusts the optimal sampling moment according to the calculated timing error and realizes the optimal sampling moment by an interpolation resampling method.
7. The system for synchronizing a receiver in the 32APSK modulation system according to claim 1, wherein: the bit synchronization module comprises a serial connection at the receiving end I1An output terminal I2An interpolation filter module, a timing error detector module, a loop filter module and a digital voltage controlled oscillator NCO module in a carrier loop, the timing error detector utilizes a receiving end I1And the self phase information of the signal is subjected to iterative subtraction on adjacent symbol points, the timing deviation is detected in real time, and after the real-time detection of the deviation is finished, the interference is removed through a loop filter based on a phase-locked loop.
8. The system for synchronizing a receiver in the 32APSK modulation system according to claim 7, wherein: in an I/Q channel mixer, a voltage-controlled oscillator NCO module moves an input carrier signal to a frequency point appointed by a frequency control word through the configuration of the frequency control word of the NCO to generate orthogonal sine and cosine samples, calculates a sine and cosine value of a phase according to each sine and cosine wave phase in advance, stores the sine and cosine value of the phase according to a phase angle serving as an address, continuously accumulates input frequency words by a phase accumulator under the control of a system clock to obtain a digital phase taking the frequency words as steps, performs initial phase offset through a phase addition module to obtain a current phase to be output, and compensates a timing error through an interpolation filter module interpolation technology to obtain an optimal symbol point.
9. The system for synchronizing a receiver in the 32APSK modulation system according to claim 1, wherein: the carrier synchronization module comprises: the phase rotation module receives a baseband signal I subjected to bit synchronization2、Q2According to the phase error extracted by the carrier loop and the phase fuzzy information fed back by the frame synchronization module, the phase compensation and the phase fuzzy operation are carried out, the signal after the phase compensation is sent to a phase discriminator, and the phase discriminator adopts a decision feedback or M power mode to extract the phase error and the residual phase error edThe extracted phase error is sent to a loop filter to ensure that local carriers at a transmitting end and a receiving end keep same frequency and phase, the carrier is removed, and the digital voltage-controlled oscillator NCO outputs an error V of the loop filterdPerforming feedback control, performing phase compensation on the input signal, providing a carrier synchronization locking indication signal by a carrier synchronization locking indication module, repeating the steps, and outputting a baseband signal I3、Q3。
10. The system for synchronizing a receiver in the 32APSK modulation system according to claim 1, wherein: the loop filter uses a second-order digital loop filter based on control with a proportional branch and an integral branch, wherein the proportional branchThe phase rotation module is used for phase error e generated by the phase discriminatordPerforming digital processing on the phase error edLoop filter parameter C1 and loop filter parameter C generated by proportional branch and integral branch2After being adjusted by an integral link and a proportional link, the delay Z is delayed by a delay unit-1Feeding back to the adder on the frequency tracking branch circuit for addition, and accumulating by the adder at the output end to obtain the filtered phase discrimination error VdAnd then sent to a voltage controlled oscillator NCO module.
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| CN115834313A (en) * | 2022-12-26 | 2023-03-21 | 成都秀为科技发展有限公司 | GPU parallel computing QPSK coherent demodulation method based on frame structure |
| CN115834313B (en) * | 2022-12-26 | 2024-04-26 | 成都秀为科技发展有限公司 | GPU parallel computing QPSK coherent demodulation method based on frame structure |
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