CN114448455A - High-speed zero intermediate frequency IQ delay compensation system based on Gardner algorithm - Google Patents
High-speed zero intermediate frequency IQ delay compensation system based on Gardner algorithm Download PDFInfo
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Abstract
The invention discloses a high-speed zero intermediate frequency IQ delay compensation system based on a Gardner algorithm, which comprises a variable rate interpolation filter, a matched filter, an IQ delay error extraction module, a first-order loop filter, a timing synchronization error extraction module, a second-order loop filter and a digital oscillator, wherein the variable rate interpolation filter is connected with the matched filter; the invention is suitable for receiving the narrow band signal, the wide band signal and the ultra wide band signal, and has wide symbol rate range and wide application range; the IQ delay correction precision can reach 1/2048 symbol delays, and the IQ delay estimation precision is 0.5ps for signals with the symbol rate of 1 Gsps; the IQ delay correction precision is high, and the correction efficiency is high.
Description
Technical Field
The invention relates to the field of receiver signal compensation technology, in particular to a high-speed zero intermediate frequency IQ delay compensation system based on a Gardner algorithm.
Background
Common communication receivers include both digital intermediate frequency receivers and zero intermediate frequency receivers. In the digital intermediate frequency receiver, the radio frequency front end completes the processing of filtering and amplifying the radio frequency signal, then the radio frequency signal is converted into an intermediate frequency signal, the intermediate frequency signal enters an A/D converter for sampling after passing through an analog band-pass filter, and is sent into an FPGA for digital quadrature down-conversion to restore an orthogonal I/Q baseband signal, and finally the work of demodulation and decoding is carried out. In a zero intermediate frequency receiver, a radio frequency front end finishes the processing of filtering and amplifying a radio frequency signal, then analog quadrature down-conversion is carried out to obtain a quadrature I/Q baseband signal, the baseband signal enters an A/D converter for sampling after passing through an analog low-pass filter, and the baseband signal is sent to an FPGA for demodulation and decoding.
Compared with a digital intermediate frequency receiver, the zero intermediate frequency receiver has the following advantages:
(1) an analog intermediate frequency processing unit is omitted in the zero intermediate frequency receiver, so that the cost and the area of a transceiver are effectively reduced;
(2) the zero intermediate frequency receiver adopts a low-pass filter to complete filtering processing, and compared with a band-pass filter of a digital intermediate frequency receiver, the low-pass filter is easier to design and realize, particularly for ultra-wideband reception above 500M symbol rate;
(3) the requirement of the zero intermediate frequency receiver on the A/D sampling rate can be greatly reduced, the baseband digital signal processing amount is greatly reduced, and the problem that high-performance high-speed A/D devices cannot be purchased can be avoided.
For laser communication, the single-beam transmission rate reaches 10Gbps, the symbol rate reaches 2 Gbps, and a zero intermediate frequency receiver is a relatively good solution. However, the zero intermediate frequency receiver has its own unique technical problems to be solved, such as local oscillator leakage, direct current offset, IQ mismatch, and the like. Wherein the I/Q mismatch comprises phase mismatch, gain mismatch, and delay mismatch. The compensation algorithms for local oscillator leakage, direct current offset, IQ phase mismatch and IQ gain mismatch are widely researched, but the compensation algorithms for IQ delay mismatch are rarely researched. At present, for an analog device, the delay precision can be ensured to be 1ns, for a signal with 10M symbol rate, the symbol interval is 100ns, and the influence of IQ delay can be ignored; for a 2G symbol rate signal, the symbol interval is 0.5ns, and the IQ delay effect may cause the receiver to be inoperable.
For an ultra-high-speed zero intermediate frequency receiver, IQ delay mismatching can be introduced by IQ orthogonal signals through different analog devices, and how to compensate the IQ delay mismatching is a problem to be solved urgently.
Disclosure of Invention
The object of the present invention is to solve at least one of the technical drawbacks mentioned.
Therefore, one objective of the present invention is to provide a high-speed zero-if IQ delay compensation system based on Gardner algorithm, which comprises a variable rate interpolation filter, a matched filter, an IQ delay error extraction module, a first-order loop filter, a timing synchronization error extraction module, a second-order loop filter and a digital oscillator; the output end of the variable rate interpolation filter is connected with the input end of a matched filter, the output end of the matched filter is respectively connected with the input end of an IQ delay error extraction module and the input end of a timing synchronization error extraction module, the output end of the IQ delay error extraction module is connected with the input end of a first-order loop filter, the output end of the first-order loop filter is connected with the input end of the variable rate interpolation filter, the output end of the timing synchronization error extraction module is connected with the input end of a second-order loop filter, the output end of the second-order loop filter is connected with the input end of a digital oscillator, and the output end of the digital oscillator is connected with the input end of the variable rate interpolation filter;
the variable rate interpolation filter adopts a polyphase filtering structure and is used for variable rate extraction recovery symbols and IQ delay correction.
The matched filter adopts a root raised cosine filter and is used for carrying out low-pass filtering on the interpolated signal and synthesizing the low-pass filtering with a forming filter at a sending end into a raised cosine filter.
And the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract delay differences of IQ two paths.
The first-order loop filter is used for smoothing IQ two paths of delay difference signals extracted by the IQ delay error extraction module.
The timing synchronization error extraction module adopts a Gardner algorithm to extract the signal sampling error.
The second order loop filter is used for smoothing the sampling error signal extracted by the timing synchronization error extraction module.
The digital oscillator is used for calculating the phase of the interpolation filter according to the sampling error signal after the second-order loop filter is smoothed, and outputting the indication of the symbol enabling along with the channel.
Preferably, the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract the delay difference extraction formula of the IQ path as follows:
e1(k)＝SI(k-1/2)·[SI(k)-SI(k-1)]-SQ(k-1/2)·[SQ(k)-SQ(k-1)]；
wherein e is1(k) For time delay difference of k, SI(k-1/2) is the real data of the matched filter output at time k-1/2, SI(k) Matched filtering for time kReal part data output by the device; s. theI(k-1) is real part data output by the k-1 moment matched filter; sQ(k-1/2) imaginary data output by the matched filter at the time k-1/2; sQ(k) Imaginary part data output by the matched filter at the time k; sQAnd (k-1) is imaginary data output by the matched filter at the k-1 moment.
In any of the above schemes, preferably, the timing synchronization error extraction module adopts a Gardner algorithm to extract the signal sampling error according to the following formula:
e2(k)＝SI(k-1/2)·[SI(k)-SI(k-1)]+SQ(k-1/2)·[SQ(k)-SQ(k-1)]；
wherein e is2(k) Sampling error for time k, SI(k-1/2) is the real data of the matched filter output at time k-1/2, SI(k) Real part data output by the matched filter at the moment k; sI(k-1) is real part data output by the k-1 moment matched filter; sQ(k-1/2) imaginary data output by the matched filter at the time k-1/2; sQ(k) Imaginary part data output by the matched filter at the time k; sQAnd (k-1) is imaginary data output by the matched filter at the k-1 moment.
Compared with the prior art, the invention has the advantages and beneficial effects that:
1. the invention can be used for all scenes of zero intermediate frequency receiving, including laser communication, satellite-ground remote sensing signal receiving, satellite communication signal receiving and transmitting, ground wireless signal relaying, large-capacity wireless data returning and the like, and has wide application range.
2. The invention is suitable for receiving narrow band signals, wide band signals and ultra wide band signals, and has wide symbol rate range and wide application range.
3. The IQ delay correction precision of the invention can reach 1/2048 symbol delays, and the IQ delay estimation precision is 0.5ps for signals with the symbol rate of 1 Gsps; and IQ delay correction precision is high.
4. The invention is mainly realized by a phase-locked loop algorithm, the required logic realization resources only need partial multiplier resources, a small amount of LUT resources and RAM resources, and the engineering realization is strong.
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The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a block diagram of a high-speed zero-if IQ delay compensation system based on Gardner algorithm according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
As shown in fig. 1, a high-speed zero-if IQ delay compensation system based on Gardner algorithm according to an embodiment of the present invention includes a variable rate interpolation filter 1, a matched filter 2, an IQ delay error extraction module 4, a first-order loop filter 3, a timing synchronization error extraction module 7, a second-order loop filter 6, and a digital oscillator 5; the output end of the variable rate interpolation filter 1 is connected with the input end of the matched filter 2, the output end of the matched filter 2 is respectively connected with the input end of an IQ delay error extraction module 4 and the input end of a timing synchronization error extraction module 7, the output end of the IQ delay error extraction module 4 is connected with the input end of a first-order loop filter 3, the output end of the first-order loop filter 3 is connected with the input end of the variable rate interpolation filter 1, the output end of the timing synchronization error extraction module 7 is connected with the input end of a second-order loop filter 6, the output end of the second-order loop filter 6 is connected with the input end of a digital oscillator 5, and the output end of the digital oscillator 5 is connected with the input end of the variable rate interpolation filter 1.
The variable rate interpolation filter adopts a multiphase filter structure and is used for variable rate extraction recovery symbols and IQ delay correction;
the matched filter adopts a root raised cosine filter and is used for carrying out low-pass filtering on the interpolated signal and synthesizing the low-pass filtering with a forming filter at a sending end into a raised cosine filter.
And the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract delay differences of IQ two paths.
The first-order loop filter is used for smoothing IQ two paths of delay difference signals extracted by the IQ delay error extraction module.
The timing synchronization error extraction module adopts a Gardner algorithm to extract the signal sampling error.
The second order loop filter is used for smoothing the sampling error signal extracted by the timing synchronization error extraction module.
The digital oscillator is used for calculating the phase of the interpolation filter according to the error signal after the second-order loop filter is smoothed, and outputting the indication of the symbol enabling along with the channel.
The embodiment of the invention creatively adds a delay correction loop and provides a realization scheme of the joint work of timing synchronization and delay correction. The variable rate interpolation filter is realized by adopting a multiphase filter structure, is mainly used for correcting IQ decimal delay, has high correction efficiency, high correction precision and strong engineering realization, and solves the problem of unmatched IQ delay of a zero intermediate frequency receiver.
The Gardner algorithm is a classical timing error detection algorithm, which only needs to sample at twice the symbol rate, i.e. 2 sampling points per symbol extract timing error information, and the method is easy to implement and widely applicable.
Further, the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract the delay difference extraction formula of IQ two paths as follows:
e1(k)＝SI(k-1/2)·[SI(k)-SI(k-1)]-SQ(k-1/2)·[SQ(k)-SQ(k-1)]；
wherein e is1(k) For time delay difference of k, SI(k-1/2) is the real data of the matched filter output at time k-1/2, SI(k) Real part data output by the matched filter at the moment k; sI(k-1) is real part data output by the k-1 moment matched filter; s. theQ(k-1/2) imaginary data output by the matched filter at the time k-1/2; sQ(k) Imaginary part data output by the matched filter at the time k; sQAnd (k-1) is imaginary data output by the matched filter at the k-1 moment.
Specifically, the timing synchronization error extraction module adopts a Gardner algorithm to extract a formula of the signal sampling error as follows:
e2(k)＝SI(k-1/2)·[SI(k)-SI(k-1)]+SQ(k-1/2)·[SQ(k)-SQ(k-1)]；
wherein e is2(k) Sampling error for time k, SI(k-1/2) is the real data of the matched filter output at time k-1/2, SI(k) Real part data output by the matched filter at the moment k; sI(k-1) is real part data output by the k-1 moment matched filter; sQ(k-1/2) imaginary data output by the matched filter at the time k-1/2; sQ(k) Imaginary part data output by the matched filter at the time k; sQAnd (k-1) is imaginary part data output by the matched filter at the k-1 moment.
The working principle of the invention is as follows: the IQ signal is input into a variable rate interpolation filter, the variable rate interpolation filter adopts a multi-phase filtering structure to perform variable rate extraction recovery symbol and IQ delay correction, the output end of the variable rate interpolation filter is connected with the input end of a matched filter, the matched filter adopts a root raised cosine filter to perform low-pass filtering on the interpolated signal, and the interpolated signal and a forming filter at a transmitting end are synthesized into a raised cosine filter; the IQ signals output by the output end of the matched filter are divided into three paths, the first path of IQ signals are output as output signals, the second path of IQ signals are output to an IQ delay error extraction module, and the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract delay differences (e) of the two paths of IQ1) And the IQ delay error signal is sent to a first-order loop filter, the first-order loop filter smoothes the error signal extracted by the IQ delay error extraction module, the smoothed delay difference signal is sent to a variable rate interpolation filter, and the variable rate interpolation filter performs delay correction on the IQ signal; sending the third IQ signal to a timing synchronization error extraction module, wherein the timing synchronization error extraction module adopts a Gardner algorithm to extract the signal sampling error (e)2) And the digital oscillator calculates the phase of the interpolation filter according to the sampling error signal smoothed by the second-order loop filter, and sends the phase to the variable-rate interpolation filter for adjustment along with the indication of the enabling of the output symbol of the channel.
The IQ delay correction precision of the invention can reach 1/2048 symbol delays, and the IQ delay estimation precision is 0.5ps for signals with the symbol rate of 1 Gsps; IQ delay correction precision is high, the required logic implementation resources only need partial multiplier resources, a small amount of LUT resources and RAM resources, and engineering realizability is strong.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It will be understood by those skilled in the art that the present invention includes any combination of the summary and detailed description of the invention described above and those illustrated in the accompanying drawings, which is not intended to be limited to the details and which, for the sake of brevity of this description, does not describe every aspect which may be formed by such combination. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (3)
1. A high-speed zero intermediate frequency IQ delay compensation system based on Gardner algorithm is characterized in that: the device comprises a variable rate interpolation filter, a matched filter, an IQ delay error extraction module, a first-order loop filter, a timing synchronization error extraction module, a second-order loop filter and a digital oscillator; the output end of the variable rate interpolation filter is connected with the input end of the matched filter, the output end of the matched filter is respectively connected with the input ends of the IQ delay error extraction module and the timing synchronization error extraction module, the output end of the IQ delay error extraction module is connected with the input end of the first-order loop filter, the output end of the first-order loop filter is connected with the input end of the variable rate interpolation filter, the output end of the timing synchronization error extraction module is connected with the input end of the second-order loop filter, the output end of the second-order loop filter is connected with the input end of the digital oscillator, and the output end of the digital oscillator is connected with the input end of the variable rate interpolation filter;
the variable rate interpolation filter adopts a multiphase filter structure and is used for variable rate extraction recovery symbols and IQ delay correction;
the matched filter adopts a root raised cosine filter and is used for carrying out low-pass filtering on the interpolated signal and synthesizing the root raised cosine filter with a forming filter at a sending end;
the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract delay differences of IQ two paths;
the first-order loop filter is used for smoothing IQ two paths of delay difference signals extracted by the IQ delay error extraction module;
the timing synchronization error extraction module adopts a Gardner algorithm to extract signal sampling errors;
the second-order loop filter is used for smoothing the sampling error signal extracted by the timing synchronization error extraction module;
and the digital oscillator is used for calculating the phase of the interpolation filter according to the sampling error signal after the second-order loop filter is smoothed, and outputting the indication of the symbol enabling along with the channel.
2. A high-speed zero-if IQ delay compensation system based on Gardner algorithm as claimed in claim 1, wherein: the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract IQ delay difference extraction formulas as follows:
e1(k)＝SI(k-1/2)·[SI(k)-SI(k-1)]-SQ(k-1/2)·[SQ(k)-SQ(k-1)]；
wherein e is1(k) For time delay difference of k, SI(k-1/2) is the real data of the matched filter output at time k-1/2, SI(k) Real part data output by the matched filter at the moment k; s. theI(k-1) is real part data output by the k-1 moment matched filter; sQ(k-1/2) imaginary data output by the matched filter at the time k-1/2; sQ(k) Imaginary part data output by the matched filter at the time k; sQAnd (k-1) is imaginary data output by the matched filter at the k-1 moment.
3. A high-speed zero-if IQ delay compensation system based on Gardner algorithm as claimed in claim 1, wherein: the timing synchronization error extraction module adopts a Gardner algorithm to extract a formula of signal sampling errors as follows:
e2(k)＝SI(k-1/2)·[SI(k)-SI(k-1)]+SQ(k-1/2)·[SQ(k)-SQ(k-1)]；
wherein e is2(k) Sampling error for time k, SI(k-1/2) is the real data of the matched filter output at time k-1/2, SI(k) Real part data output by the matched filter at the moment k; sI(k-1) is real part data output by the k-1 moment matched filter; s. theQ(k-1/2) imaginary data output by the matched filter at the time k-1/2; sQ(k) Imaginary part data output by the matched filter at the time k; sQ(k-1) imaginary data output by the matched filter at the time of k-1。
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