CN114448455B - Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/12—Neutralising, balancing, or compensation arrangements
- H04B1/123—Neutralising, balancing, or compensation arrangements using adaptive balancing or compensation means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D30/00—Reducing energy consumption in communication networks
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Abstract
The invention discloses a Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system, which comprises a variable rate interpolation filter, a matched filter, an IQ delay error extraction module, a first-order loop filter, a timing synchronization error extraction module, a second-order loop filter and a digital oscillator; the invention is applicable to the reception of narrowband signals, wideband signals and ultra wideband signals, and has wide symbol rate range and wide application range; the IQ delay correction precision can reach 1/2048 symbol delay, and for a signal with a symbol rate of 1Gsps, the IQ delay estimation precision is 0.5ps; the IQ delay correction precision is high, and the correction efficiency is high.
Description
Technical Field
The invention relates to the field of receiver signal compensation, in particular to a high-speed zero intermediate frequency IQ delay compensation system based on a Gardner algorithm.
Background
Common communication receivers include both digital intermediate frequency receivers and zero intermediate frequency receivers. In the digital intermediate frequency receiver, the radio frequency front end completes the filtering and amplifying treatment of radio frequency signals, then the radio frequency signals are converted into intermediate frequency signals, the intermediate frequency signals enter an A/D converter for sampling after passing through an analog band-pass filter, the intermediate frequency signals are sent into an FPGA for digital quadrature down-conversion and reduction to obtain quadrature I/Q baseband signals, and finally demodulation and decoding are carried out. In the zero intermediate frequency receiver, the radio frequency front end completes the filtering and amplifying treatment of radio frequency signals, then carries out analog quadrature down conversion to obtain quadrature I/Q baseband signals, and the baseband signals enter an A/D converter for sampling after passing through an analog low-pass filter and are sent to an FPGA for demodulation and decoding.
The zero intermediate frequency receiver has the following advantages relative to the digital intermediate frequency receiver:
(1) The zero intermediate frequency receiver omits an analog intermediate frequency processing unit, and effectively reduces the cost and the area of a transceiver;
(2) The zero intermediate frequency receiver adopts a low-pass filter to complete the filtering process, and compared with a band-pass filter of the digital intermediate frequency receiver, the low-pass filter is easier to design and realize, especially for ultra-wideband receiving with the symbol rate of more than 500M;
(3) The requirement of the zero intermediate frequency receiver on the A/D sampling rate can be greatly reduced, and the problem that high-performance high-speed A/D devices cannot be purchased can be avoided while the processing amount of baseband digital signals is greatly reduced.
For laser communication, the single beam transmission rate reaches 10Gbps, the symbol rate reaches 2Gsps, and a zero intermediate frequency receiver is a relatively preferable solution. However, the zero intermediate frequency receiver has own specific technical problems to be solved, such as local oscillator leakage, direct current bias, IQ mismatch and the like. Wherein the I/Q mismatch includes a phase mismatch, a gain mismatch, and a delay mismatch. The compensation algorithm for local oscillation leakage, direct current bias, IQ phase mismatch and IQ gain mismatch is widely studied, but the compensation algorithm for IQ delay mismatch is less studied. At present, for an analog device, the delay precision can be guaranteed to be 1ns, for a signal with a 10M symbol rate, the symbol interval is 100ns, and the influence of IQ delay can be ignored; for a 2G symbol rate signal, the symbol interval is 0.5ns, and iq delay effects can cause the receiver to fail.
For the ultra-high-speed zero intermediate frequency receiver, IQ delay mismatch can be introduced into IQ quadrature signals through different analog devices, and how to compensate for the IQ delay mismatch is an urgent problem to be solved.
Disclosure of Invention
The object of the present invention is to solve at least one of the technical drawbacks.
Therefore, an object of the present invention is to provide a Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system, which comprises a variable rate interpolation filter, a matched filter, an IQ delay error extraction module, a first-order loop filter, a timing synchronization error extraction module, a second-order loop filter and a digital oscillator; the output end of the variable rate interpolation filter is connected with the input end of the matched filter, the output end of the matched filter is respectively connected with the input end of the IQ delay error extraction module and the input end of the timing synchronization error extraction module, the output end of the IQ delay error extraction module is connected with the input end of the first-order loop filter, the output end of the first-order loop filter is connected with the input end of the variable rate interpolation filter, the output end of the timing synchronization error extraction module is connected with the input end of the second-order loop filter, the output end of the second-order loop filter is connected with the input end of the digital oscillator, and the output end of the digital oscillator is connected with the input end of the variable rate interpolation filter;
the variable rate interpolation filter adopts a polyphase filter structure for variable rate extraction and recovery of symbols and IQ delay correction.
The matched filter adopts a root raised cosine filter and is used for carrying out low-pass filtering on the interpolated signal and synthesizing the root raised cosine filter with a shaping filter at a transmitting end.
The IQ delay error extraction module adopts an adaptive updating algorithm to extract the delay difference of two IQ paths.
The first-order loop filter is used for smoothing the delay difference signals of the two paths of IQ extracted by the IQ delay error extraction module.
The timing synchronization error extraction module adopts Gardner algorithm to extract the sampling error of the signal.
The second-order loop filter is used for smoothing the sampling error signal extracted by the timing synchronization error extraction module.
The digital oscillator is used for calculating the phase of the interpolation filter according to the sampling error signal smoothed by the second-order loop filter and outputting an indication of symbol enabling along with the path.
Preferably, the IQ delay error extraction module extracts the delay difference extraction formula of two paths of IQ by adopting a self-adaptive updating algorithm, wherein the delay difference extraction formula is as follows:
e 1 (k)＝S I (k-1/2)·[S I (k)-S I (k-1)]-S Q (k-1/2)·[S Q (k)-S Q (k-1)]；
wherein e 1 (k) For the delay difference of k time, S I (k-1/2) real part data of the matched filter output at time k-1/2, S I (k) Matching real part data output by the filter for the k moment; s is S I (k-1) is real part data output by the k-1 time matched filter; s is S Q (k-1/2) is the imaginary data output by the k-1/2 time matched filter; s is S Q (k) Matching the imaginary part data output by the filter for the k moment; s is S Q (k-1) is the imaginary data of the k-1 time matched filter output.
In any of the above schemes, preferably, the timing synchronization error extraction module uses the Gardner algorithm to extract the signal sampling error as follows:
e 2 (k)＝S I (k-1/2)·[S I (k)-S I (k-1)]+S Q (k-1/2)·[S Q (k)-S Q (k-1)]；
wherein e 2 (k) For sampling error at time k, S I (k-1/2) real part data of the matched filter output at time k-1/2, S I (k) Matching real part data output by the filter for the k moment; s is S I (k-1) is real part data output by the k-1 time matched filter; s is S Q (k-1/2) is the imaginary data output by the k-1/2 time matched filter; s is S Q (k) Matching the imaginary part data output by the filter for the k moment; s is S Q (k-1) is the imaginary data of the k-1 time matched filter output.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the invention can be used for all zero intermediate frequency receiving scenes, including laser communication, satellite-ground remote sensing signal receiving, satellite communication signal receiving and transmitting, ground wireless signal relay, large-capacity wireless data returning and the like, and has wide application range.
2. The invention is applicable to the reception of narrowband signals, wideband signals and ultra wideband signals, and has wide symbol rate range and wide application range.
3. The IQ delay correction precision can reach 1/2048 symbol delay, and for a signal with a symbol rate of 1Gsps, the IQ delay estimation precision is 0.5ps; the IQ delay correction precision is high.
4. The invention is realized mainly by the phase-locked loop algorithm, and the required logic realization resource only needs partial multiplier resource, a small amount of LUT resource and RAM resource, and the engineering realization is strong.
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The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a block diagram of a Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
As shown in fig. 1, the Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system according to the embodiment of the present invention comprises a variable rate interpolation filter 1, a matched filter 2, an IQ delay error extraction module 4, a first-order loop filter 3, a timing synchronization error extraction module 7, a second-order loop filter 6 and a digital oscillator 5; the output end of the variable rate interpolation filter 1 is connected with the input end of the matched filter 2, the output end of the matched filter 2 is respectively connected with the input end of the IQ delay error extraction module 4 and the input end of the timing synchronization error extraction module 7, the output end of the IQ delay error extraction module 4 is connected with the input end of the first-order loop filter 3, the output end of the first-order loop filter 3 is connected with the input end of the variable rate interpolation filter 1, the output end of the timing synchronization error extraction module 7 is connected with the input end of the second-order loop filter 6, the output end of the second-order loop filter 6 is connected with the input end of the digital oscillator 5, and the output end of the digital oscillator 5 is connected with the input end of the variable rate interpolation filter 1.
The variable rate interpolation filter adopts a multiphase filtering structure and is used for variable rate extraction and recovery of symbols and IQ delay correction;
the matched filter adopts a root raised cosine filter and is used for carrying out low-pass filtering on the interpolated signal and synthesizing the root raised cosine filter with a shaping filter at a transmitting end.
The IQ delay error extraction module adopts an adaptive updating algorithm to extract the delay difference of two IQ paths.
The first-order loop filter is used for smoothing the delay difference signals of the two paths of IQ extracted by the IQ delay error extraction module.
The timing synchronization error extraction module adopts Gardner algorithm to extract the sampling error of the signal.
The second-order loop filter is used for smoothing the sampling error signal extracted by the timing synchronization error extraction module.
The digital oscillator is used for calculating the phase of the interpolation filter according to the error signal smoothed by the second-order loop filter and outputting an indication of symbol enabling along with the path.
The embodiment of the invention creatively increases a delay correction loop and provides an implementation scheme of joint work of timing synchronization and delay correction. The variable rate interpolation filter is realized by adopting a multiphase filter structure, is mainly used for correcting the IQ decimal delay, has high correction efficiency and correction precision, is strong in engineering realization, and solves the problem of mismatch of the IQ delay of the zero intermediate frequency receiver.
The Gardner algorithm is a classical timing error detection algorithm that only requires sampling at twice the symbol rate, i.e. 2 samples per symbol to extract the timing error information, which is easy to implement and widely used, and the algorithm in the present invention is shown to be based on the Gardner algorithm, but not belonging to the existing formula algorithm.
Furthermore, the IQ delay error extraction module extracts the delay difference extraction formula of two paths of IQ by adopting a self-adaptive updating algorithm, wherein the delay difference extraction formula is as follows:
e 1 (k)＝S I (k-1/2)·[S I (k)-S I (k-1)]-S Q (k-1/2)·[S Q (k)-S Q (k-1)]；
wherein e 1 (k) For the delay difference of k time, S I (k-1/2) real part data of the matched filter output at time k-1/2, S I (k) Matching real part data output by the filter for the k moment; s is S I (k-1) is real part data output by the k-1 time matched filter; s is S Q (k-1/2) is the imaginary data output by the k-1/2 time matched filter; s is S Q (k) Matching the imaginary part data output by the filter for the k moment; s is S Q (k-1) is the imaginary data of the k-1 time matched filter output.
Specifically, the timing synchronization error extraction module adopts a Gardner algorithm to extract a formula for signal sampling errors as follows:
e 2 (k)＝S I (k-1/2)·[S I (k)-S I (k-1)]+S Q (k-1/2)·[S Q (k)-S Q (k-1)]；
wherein e 2 (k) For sampling error at time k, S I (k-1/2) is the matched filter output at time k-1/2Real part data, S I (k) Matching real part data output by the filter for the k moment; s is S I (k-1) is real part data output by the k-1 time matched filter; s is S Q (k-1/2) is the imaginary data output by the k-1/2 time matched filter; s is S Q (k) Matching the imaginary part data output by the filter for the k moment; s is S Q (k-1) is the imaginary data of the k-1 time matched filter output.
The working principle of the invention is as follows: the IQ signal is input into a variable rate interpolation filter, the variable rate interpolation filter adopts a multiphase filtering structure to carry out variable rate extraction recovery symbols and IQ delay correction, the output end of the variable rate interpolation filter is connected with the input end of a matched filter, the matched filter adopts a root raised cosine filter to carry out low-pass filtering on the interpolated signal, and the low-pass filtering is synthesized with a forming filter of a transmitting end to form a raised cosine filter; the IQ signal output by the output end of the matched filter is divided into three paths, the first path of IQ signal is output as an output signal, the second path of IQ signal is output to an IQ delay error extraction module, and the IQ delay error extraction module adopts an adaptive updating algorithm to extract the delay difference (e 1 ) The error signal extracted by the IQ delay error extraction module is smoothed by the first-order loop filter, the smoothed delay difference signal is sent to the variable-rate interpolation filter, and the variable-rate interpolation filter carries out delay correction on the IQ signal; the third IQ signal is sent to a timing synchronization error extraction module, and the timing synchronization error extraction module adopts Gardner algorithm to extract the signal sampling error (e) 2 ) The extracted sampling error signal is sent to a second-order loop filter, the extracted sampling error signal is smoothed in the second-order loop filter, the smoothed sampling error signal is sent to a digital oscillator, the digital oscillator calculates the phase of an interpolation filter according to the smoothed sampling error signal of the second-order loop filter, and an instruction of enabling a symbol is output along with the path and is sent to a variable rate interpolation filter for adjustment.
The IQ delay correction precision can reach 1/2048 symbol delay, and for a signal with a symbol rate of 1Gsps, the IQ delay estimation precision is 0.5ps; the IQ delay correction precision is high, the required logic realization resources only need partial multiplier resources, a small amount of LUT resources and RAM resources, and the engineering realization performance is strong.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It will be readily understood by those skilled in the art that the present invention, including any combination of parts described in the summary and detailed description of the invention above and shown in the drawings, is limited in scope and does not constitute a complete description of the various aspects of these combinations for the sake of brevity. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives, and variations may be made in the above embodiments by those skilled in the art without departing from the spirit and principles of the invention. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (3)
1. A Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system is characterized in that: the system comprises a variable rate interpolation filter, a matched filter, an IQ delay error extraction module, a first-order loop filter, a timing synchronization error extraction module, a second-order loop filter and a digital oscillator; the output end of the variable rate interpolation filter is connected with the input end of the matched filter, the output end of the matched filter is respectively connected with the input end of the IQ delay error extraction module and the input end of the timing synchronization error extraction module, the output end of the IQ delay error extraction module is connected with the input end of the first-order loop filter, the output end of the first-order loop filter is connected with the input end of the variable rate interpolation filter, the output end of the timing synchronization error extraction module is connected with the input end of the second-order loop filter, the output end of the second-order loop filter is connected with the input end of the digital oscillator, and the output end of the digital oscillator is connected with the input end of the variable rate interpolation filter;
the variable rate interpolation filter adopts a multiphase filtering structure and is used for variable rate extraction and recovery symbols and IQ delay correction;
the matched filter adopts a root raised cosine filter and is used for carrying out low-pass filtering on the interpolated signal and synthesizing the raised cosine filter with a shaping filter at a transmitting end;
the IQ delay error extraction module adopts a self-adaptive updating algorithm to extract the delay difference of two IQ paths;
the first-order loop filter is used for smoothing delay difference signals of two paths of IQ extracted by the IQ delay error extraction module;
the timing synchronization error extraction module adopts a Gardner algorithm to extract signal sampling errors;
the second-order loop filter is used for smoothing the sampling error signal extracted by the timing synchronization error extraction module;
the digital oscillator is used for calculating the phase of the interpolation filter according to the sampling error signal smoothed by the second-order loop filter and outputting a sign enabling indication along with the path.
2. The Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system according to claim 1 wherein: the delay difference extraction formula of the IQ two paths extracted by the IQ delay error extraction module by adopting a self-adaptive updating algorithm is as follows:
e 1 (k)＝S I (k-1/2)·[S I (k)-S I (k-1)]-S Q (k-1/2)·[S Q (k)-S Q (k-1)]；
wherein e 1 (k) For the delay difference of k time, S I (k-1/2) real part data of the matched filter output at time k-1/2, S I (k) Matching real part data output by the filter for the k moment; s is S I (k-1) is real part data output by the k-1 time matched filter; s is S Q (k-1/2) is the imaginary data output by the k-1/2 time matched filter; s is S Q (k) Matching the imaginary part data output by the filter for the k moment; s is S Q (k-1) is the imaginary data of the k-1 time matched filter output.
3. The Gardner algorithm-based high-speed zero intermediate frequency IQ delay compensation system according to claim 1 wherein: the timing synchronization error extraction module adopts a Gardner algorithm to sample the signal and extracts the error according to the formula:
e 2 (k)＝S I (k-1/2)·[S I (k)-S I (k-1)]+S Q (k-1/2)·[S Q (k)-S Q (k-1)]；
wherein e 2 (k) For sampling error at time k, S I (k-1/2) real part data of the matched filter output at time k-1/2, S I (k) Matching real part data output by the filter for the k moment; s is S I (k-1) is real part data output by the k-1 time matched filter; s is S Q (k-1/2) is the imaginary data output by the k-1/2 time matched filter; s is S Q (k) Matching the imaginary part data output by the filter for the k moment; s is S Q (k-1) is the imaginary data of the k-1 time matched filter output.
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| DE10133898C1 (en) * | 2001-07-12 | 2002-10-17 | Infineon Technologies Ag | Receiver with integrated clock phase detector has outputs of matched filter and frequency-matched filter combined by multiplier to provide clock phase disparity detection signal |
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