KR20030032550A - Timing lock detector of quadrature amplitude modulation receiver - Google Patents

Abstract

PURPOSE: A timing lock detector of a QAM(Quadrature Amplitude Modulation) receiver is provided to correctly control a loop bandwidth of a loop filter by using a timing lock signal, thereby improving performance of a clock recovery system with stability. CONSTITUTION: A lock detector(50) delays a receiving signal of a baseband divided into an I channel and a Q channel, squares the delayed signal to operate the signal, and outputs the operated signal. An averager(70) obtains an average of the output signal of the lock detector(50) passing through a decimator(65) for performing a down-sampling process at a symbol rate, and outputs the signal. A comparator/determiner(80) compares the output signal of the averager(70) with a threshold value, and generates a lock signal if the output signal is bigger than the threshold value.

Description

TIMING LOCK DETECTOR OF QUADRATURE AMPLITUDE MODULATION RECEIVER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to timing recovery in a QAM receiver, which is a cable broadcasting receiving chip of a high definition television (HDTV), and generates a timing lock signal for controlling the loop bandwidth of a loop filter to improve the performance of the timing recovery. A timing lock detector of an improved QAM receiver is provided.

In general, a transmission system of a high definition television (HDTV) transmits data having a high data rate of about 20 Mbps or more through a limited bandwidth of 6 MHz, and thus requires a bandwidth efficient modulation scheme.

QAM (Quadrature Amplitude Modulation) method has the advantage of maximizing signal aggregation on two-dimensional constellation, while transmitting the signal divided into I (In-Phase) and Q (Quadrature-Phase) signals. Therefore, it is difficult to implement compared to VSB (Vestigial SideBand) method that transmits only I signal.

1 is a block diagram showing the configuration of a QAM receiver, a tuner that lowers a radio frequency (RF) to an intermediate frequency (IF), and converts a digital frequency by sampling an intermediate frequency output from the tuner. An analog receiver 10 comprising an analog to digital converter (ADC); A synchronization detector 20 that receives the digital signal and detects timing and carrier, a channel equalizer 30 that compensates for channel distortion of the signal output from the synchronization detector 20, and a coding gain It consists of a demodulator comprising a channel encoder for correcting the error of the signal output from the channel equalizer (30).

The synchronization detector 20 may include a carrier recovery for downsing the digital signal to a baseband and forming a long loop; Timing recovery is performed by receiving a signal downlink to the baseband by the carrier recovery and performing a clock recovery.

Here, in the clock recovery method using a resampler among the methods used for the timing recovery, the timing recovery uses the offset received from the interpolation controller by receiving the A / D converted digital sample as shown in FIG. 2. An interpolator 21 for interpolating and outputting a value between samples; A matching filter 22 for extracting a desired signal from the signal output from the interpolator 21 to maximize the signal-to-noise ratio; A decimator (23) for down sampling the signal output from the matched filter (22); A pre-filter 24 for receiving a signal output from the decimator 23 and filtering a spectral edge portion having timing information; A timing error extractor (25) which receives a signal output from the prefilter (24) and generates a timing error using a timing extraction algorithm of a Gardner method; The signal output from the timing error extractor 25 passed through the loop filter 26 is input, that is, the symbol clock is estimated using the timing error to calculate a time difference between the current A / D sample and the actual symbol sample. The operation of timing recovery composed of an interpolation controller (NCO: Number Controlled Oscillator) 27 for outputting an offset, which is a difference value, to the interpolator 21 will be described.

The resampler is composed of an interpolator 21 and an interpolation controller 27, and the interpolator 21 receives an A / D converted digital sample using an offset input from the interpolation controller 27. Interpolate and output the values between samples.

The data passed through the resampler is input to the prefilter 24 after passing through the matching filter 22 and the decimator 23.

The prefilter 24 filters a spectral edge portion including timing information and includes two taps of Infinite Impulse Response (IIR).

The timing error extractor 25 receives the data passed through the prefilter 24 and generates a timing error using a timing extraction algorithm of the Gardner method.

The timing extraction algorithm of the Gardner method cancels the phase error by the timing detector characteristic even when carrier synchronization is not completed, that is, when a phase error exists.

Therefore, the timing extraction algorithm of the Gardner method has an advantage in that timing capturing proceeds in parallel with the carrier recovery since the effect from the carrier recovery is ignored.

Since the timing error extractor 25 can obtain timing information in both I and Q channels, the timing error extractor 25 sums the timing errors obtained in each of the two channels and outputs the sum of the timing errors to the loop filter 26.

The interpolation controller 27 estimates the symbol clock using the timing error through the loop filter 26 to calculate a time difference between the current A / D sample and the actual symbol sample, and calculates an offset that is the difference value. 21).

The operation of the timing recovery has been described above, and the characteristics of the timing recovery are as follows.

The signal recovered to the baseband by carrier recovery is subjected to clock recovery by timing recovery.

The clock recovery method using a resampler performs A / D conversion at a fixed frequency and digitally handles all clock recovery, thus simplifying implementation and eliminating device noise by eliminating the need for an analog device other than a converter.

In addition, the clock recovery method may digitally implement a loop filter of a phase-locked loop (PLL) to adjust a loop bandwidth for determining a convergence characteristic of a clock recovery system.

In addition, the clock recovery method may use a method of direct sampling down to the first intermediate frequency band without using an analog mixer required for frequency conversion from the first intermediate frequency (44 MHz) to the second intermediate frequency. There is an advantage.

Finally, the clock recovery method requires only the controller of the resampler to support various symbol clocks in the clock recovery of the QAM system, and thus does not require the addition of a special device.

The background of the present invention has been described above, and the necessity of the present invention will be described.

The symbol synchronization circuit has a PLL structure, and a loop filter 26 that serves as a low pass filter (LPF) after the timing error extractor 25 is essential.

The number of integrators in the loop filter 26 determines the order of the PLL. In most cases, the second order PLL is selected in consideration of tracking capability or system stability.

At this time, the loop filter 26 has one integrator, and the Laplace transformation model is as follows.

Here, the coefficients K1 and K2 of the loop filter determine the characteristics of the loop filter and further determine the characteristics of the entire PLL loop.

If the values of K1 and K2 are large, the timing jitter may be large instead of increasing the convergence characteristic of the system.

On the contrary, when the values of K1 and K2 are small, the convergence speed is slowed, but the stable characteristics are shown.

Therefore, in the initial stage of timing recovery, the values of K1 and K2 are increased to induce convergence quickly, and when timing recovery is completed to some extent, the values of K1 and K2 are reduced to stably and completely capture timing jitter.

In this case, the TLD (Timing Lock Detector) is required. The timing lock detector plays a decisive role in adjusting the loop bandwidth by outputting a timing lock signal when the timing characteristics converge. .

In addition, when the IIR filter characteristic is not good in the Decision-Feedback Equalizer, the timing lock signal serves to adjust the IIR filter of the equalizer.

Accordingly, the present invention has been made in view of the above necessity, and improves the performance of the clock recovery system by properly adjusting the loop bandwidth of the loop filter by using the timing lock signal, thereby improving the performance of the clock receiver. The purpose is to provide a timing lock detector.

It is also an object of the present invention to provide a timing lock detector of a QAM receiver, which is designed to have a configuration similar to that of a timing error extractor.

1 is a block diagram showing the configuration of a conventional QAM receiver.

FIG. 2 is a block diagram illustrating a configuration of timing recovery in the synchronization detector of FIG. 1. FIG.

Figure 3 is an exemplary view showing the output characteristics of the timing error extractor for explaining the present invention.

Figure 4 is an exemplary view showing the output characteristics of the timing lock detector of the present invention.

Fig. 5 is a block diagram showing the construction of the timing lock detector of the present invention.

6 is a block diagram showing the configuration of the lock detector of FIG.

7 is a block diagram showing the configuration of the averager of FIG. 5;

8 is an exemplary view showing a convergence characteristic of timing errors in a QAM receiver to which the present timing lock detector is applied.

9 is an exemplary view showing a symbol average output value of the timing lock detector according to the present invention.

** Description of the symbols for the main parts of the drawings **

50: lock detector 51, 52, 56, 57: delay

53, 54, 58, 59: squarer 55, 60: subtractor

61: adder 65: decimator

70: average 71: accumulator

72: cutter 73: counter

80: comparator / determiner

The present invention for achieving the above object, the lock detector for delaying and squared the baseband received signal divided into I and Q channels and then calculates and outputs; An averager for averaging the output signal of the lock detector after down-sampling at a symbol rate; The output signal of the averager is compared with a threshold, and when the value is large, the comparator / determiner generates a lock signal.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

First, the timing lock detector is designed to have a structure similar to the timing error extractor of the Gardner method.

Assuming that the communication channel is an ideal noise-free channel, the received signal sampled at the symbol rate will always show a nonzero value when clock recovery is complete.

When a window is defined around the signal constellation, it counts the case where the received signal is within this window, and assumes that the lock is locked when it is less than a predefined threshold. The opposite case is unlocked. Assume

When the received baseband complex signal is x (t), it may be represented by Equation 2 below.

Where g (t) is the channel impulse response, a _i is the data symbol, T is the symbol period, τ is the phase of the symbol clock, n (t) is noise, and x (t) Is the received baseband complex signal.

In addition, the timing error extractor of the Gardner method requires two samples per symbol period, and the output value at kT + τ, which is the determination moment, is expressed by Equation 3 below.

Where r stands for real, i stands for imaginary, x (t) is the received baseband complex signal, and e _k is the output of the timing error extractor.

In addition, the output of the timing lock detector is expressed by Equation 4 below.

Where r stands for real, i stands for imaginary, x (t) is the received baseband complex signal, and v _k is the output of the timing lock detector.

The average of the phase error of the output of the timing error extractor implemented by the Gardner method is expressed by Equation 5 below.

4

Where E (e _k ) is the average of the output of the timing error extractor, τ _e is the phase error of the symbol clock, and θ is the offset of the phase.

An average of the phase error of the output of the timing error extractor is shown as a sine curve as shown in FIG. 3.

In addition, the average of the phase error of the output of the timing lock detector is expressed by Equation 6 below.

Where E (v _k ) is the average of the output of the timing lock detector, τ _e is the phase error of the symbol clock, and Ψ is the phase offset.

The average of the phase error of the output of the timing lock detector is shown as a cosine curve as shown in FIG. 4.

As described above, the timing error extractor and the timing lock detector are assumed to be locked when the timing error extractor reaches a stable equilibrium state, and the average output value of the timing lock detector maintains the maximum value.

On the contrary, when the synchronization detector is unlocked, the timing error increases and the average output value of the timing lock detector shows zero.

Therefore, whether to lock or unlock the synchronization detector can be determined by comparing the average output value of the timing lock detectors. Implementing such characteristics of the timing lock detector is as follows.

5 is a block diagram showing the configuration of the timing lock detector of the QAM receiver of the present invention, comprising: a lock detector 50 for delaying, squaring, and calculating a baseband received signal divided into I and Q channels; An averager (70) which averages the output signal of the lock detector (50) passed through the decimator (65) for down-sampling at a symbol rate and outputs the average; It is composed of a comparator / determinator 80 which produces a lock signal when the output signal of the averager 70 is compared with a threshold.

As shown in FIG. 6, the lock detector 50 includes delayers 51, 52, 56, 57 for delaying and outputting baseband samples divided into I and Q channels; A squarer (53, 54, 58, 59) for squaring and outputting samples delayed or not by the delayers (51, 52, 56, 57); A subtractor (55, 60) for obtaining and outputting a difference of the samples squared by the squarers (53, 54, 58, 59); And an adder 61 for adding and outputting the samples calculated by the subtractors 55 and 60.

As shown in FIG. 7, the averager 70 includes an accumulator 71 which receives a signal output from the lock detector 50 and calculates and outputs the signal; A cutter 72 which deletes a portion exceeding the allocated number of digits among the results calculated by the accumulator 71 and outputs the result to the comparator / determinator 80 when the average flag is set; The operation of the timing lock detector of the UE of the present invention, which comprises a counter 73 for outputting a clear signal to the accumulator 71 and outputting an average flag to the cutter 72 when a predetermined count is reached, will be described below. same.

The lock detector 50 uses two samples per symbol and calculates two baseband signals according to the I and Q channels and outputs them to the averager 70.

Here, it is very important to determine the number of symbols averaged in the averager 70.

In general, as the number of averaged symbols decreases, the range of error decreases. However, as the interval in which the timing lock signal is updated becomes too long, the time for tuning the loop bandwidth may be lengthened.

For example, if the simulation sets the number of symbols to 8192, this is equal to 2 ^ 13, to replace the truncation 72 without using a divider.

Thereafter, the signal output from the averager 70 is input to the comparator / determinator 80 to be compared with a threshold, and if it is larger than this threshold, the timing lock signal is output by the comparator / determinator 80.

FIG. 8 is an exemplary diagram showing convergence characteristics of timing errors when the entire QAM communication system is simulated with a floating point, showing an initial overshoot and stable convergence after a steep descent.

9 is an exemplary view showing a symbol average output value of a timing lock detector, and it can be seen that the characteristics of the timing lock detector described above theoretically coincide with actual convergence characteristics.

As described in detail above, the present invention is a timing lock detector that plays a decisive role in tuning the loop bandwidth of the loop filter, thereby generating an accurate timing lock signal and improving the performance of timing recovery.

In addition, the present invention is designed in a structure similar to the timing error extractor has an effect that can be easily implemented.

Claims (3)

A lock detector for delaying, squaring, and calculating a baseband received signal divided into I and Q channels; An averager for averaging the output signal of the lock detector after down-sampling at a symbol rate; And a comparator / determiner configured to generate a lock signal when the output signal of the averager is large compared with a threshold value. 2. The apparatus of claim 1, wherein the lock detector comprises: a delay unit for delaying and outputting baseband samples divided into I and Q channels; A squarer for squaring and outputting samples delayed or not by the delayer; A subtractor for calculating and outputting a difference of the squared samples by the squarer; And a adder configured to add and output the sample calculated by the subtractor. The accumulator of claim 1, wherein the average unit comprises: an accumulator configured to receive a signal output from a lock detector, calculate and output the received signal; A cutter for deleting a portion exceeding an allocated number of results calculated by the accumulator and outputting the average flag to a compare / determiner when the average flag is set; And a counter for outputting a clear signal to the accumulator and outputting an average flag to the cutter side when a predetermined count is reached.