JP3479882B2 - Demodulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for demodulating a quadrature-modulated input signal, and more particularly to a demodulator for digital signal processing.

[0002]

2. Description of the Related Art With the rapid progress of LSI technology, attempts have been made to apply digital signal processing technology to demodulators in the field of high-speed communication systems with a modulation rate of, for example, 10 MHz. The demodulator to which digital signal processing technology is applied (hereinafter referred to as "digital demodulator") has a stable quality compared with a demodulator composed of analog circuits. Can be realized, 2) it can be made into an LSI, 3) no adjustment is required, and the specification can be easily changed, which has various advantages.

[0003]

In order to realize the main function of the demodulator including the roll-off filter by digital signal processing, according to the sampling theorem, the sampling frequency is more than twice the highest frequency component of the sampled signal. And have to. That is, the modulation speed is 1
If 0 MHz, the sampling rate must be 20 MHz or higher, and similarly, if the modulation rate is 20 MHz, the sampling rate must be 40 MHz or higher.

In order to perform digital demodulation processing at the same speed as such a sampling rate, the digital demodulator must be composed of a very high speed device, and it is required that pipeline processing be performed. To be done.

However, if the sampling rate becomes higher along with the increase in the modulation rate, there is a possibility that the operating speed of the device cannot keep up with the sampling rate. For example, the modulation speed is 50MH
Once z is exceeded, current technology makes it very difficult to realize such a device.

Further, as the sampling rate increases, the number of stages of pipeline processing also increases. This means increased "delay" in the pipeline process. If the delay increases in this way, the circuit scale is inevitably increased, and the feedback control characteristic, especially the carrier recovery loop characteristic, is deteriorated.

Therefore, an object of the present invention is to provide a digital demodulator applicable to a higher speed communication system in order to solve the above problems.

[0008]

According to the present invention, an A / D converted signal is converted into a serial / parallel signal (hereinafter referred to as S / P conversion).
Then, the demodulation processing speed is set to the modulation speed to solve the above problem. In addition, the present invention is configured such that each unit that performs digital demodulation processing can also perform parallel processing. Specifically, the present invention provides the demodulator and the like shown below.

According to the present invention, a quadrature-modulated IF signal is received, analog quadrature detection is performed using a predicted carrier frequency having a frequency substantially the same as an actual carrier frequency, and the first and second orthogonal signals are orthogonal to each other. An analog quadrature detector that outputs a second quadrature detection signal and the first and second quadrature detection signals are received, and A / D conversion is performed at a speed twice or more the modulation speed, respectively. And a first and a second A / D converter for outputting a second serial signal, and a plurality of signal trains having the same data rate as the modulation rate for the first and second serial signals, respectively. First and second serial-parallel converters for converting into first and second parallel signals, and a first parallel signal for filtering the first parallel signal at the modulation speed in parallel to form a second filter signal. First parallel processing type FI operating as a roll-off filter for outputting a pair of filter signals
And R filter, the second parallel signals by filtering parallel by the modulation rate, the second parallel processing operating as a roll-off filter for outputting a second filtered signal pair comprising two filters signal Type FIR filter and the first and second filter signal pairs,
Using a carrier signal that shows the phase error with respect to the carrier,
Note of the remaining phase in the processing of the analog quadrature detector
The phase shift processing for removing the shift is performed at the above-mentioned modulation speed, and
And a parallel phase shifter for outputting a second demodulated signal, and the first and second
And the second demodulated signal are monitored to generate the carrier signal.
And a carrier wave signal generator for generating a demodulator.

Further, according to the present invention, the quadrature-modulated first IF signal is received, and the difference between the actual carrier frequency and the predicted carrier frequency having substantially the same frequency is the predetermined modulation speed. An analog detector that performs detection using a frequency and outputs a second IF signal having a modulation speed as a pseudo carrier frequency; and a speed that is four times the modulation speed when receiving the second IF signal. And an A / D converter that performs A / D conversion to output a serial signal, and first and second signals including a plurality of signal trains that receive the serial signal and perform quadrature detection and have the same data rate as the modulation rate. And a roll-off filter for filtering the first parallel signal in parallel at the modulation speed and outputting a first filter signal pair consisting of two filter signals. A first parallel processing type FIR filter operating as a filter, said second parallel signal by filtering parallel by the modulation rate, two second roll for outputting a filtered signal pairs of filter signal Second parallel processing type F that operates as an off filter
An IR filter and the first and second filter signal pairs
Receive and use a carrier signal that shows the phase error with respect to the carrier
And the remaining amount in the processing of the analog detector.
The phase shift processing to remove the phase shift is performed at the modulation speed, and the
A parallel phase shifter for outputting first and second demodulated signals;
The carrier signal is monitored by monitoring the first and second demodulated signals.
A carrier signal generator for generating the demodulator is provided.

Here, the above-mentioned first and second parallel processing type FIR filters are any one of the following first to third when the A / D conversion is performed at a speed twice the modulation speed. The parallel processing type FIR filter may be used. It should be noted that each of the first to third parallel processing type FIR filters illustrated here receives an odd data signal and an even data signal obtained by performing serial-parallel conversion on a serial data signal, and filters them in parallel. , A parallel roll-off filter that outputs an odd filter signal and an even filter signal.

Specifically, according to the present invention, as the first parallel processing type FIR filter, the first to sixth delay devices and the first to tenth multiplication coefficients, respectively, are defined.
To 10th multipliers and 1st to 6th adders, wherein the 1st to 6th delay devices are:
Each has a predetermined time as a delay time,
The first, fifth, sixth and tenth multiplication factors are equal to each other, and the second, fourth, seventh and ninth multiplication factors are:
They are equal to each other, the third and eighth multiplication coefficients are equal to each other, and the first and fourth delay devices receive the odd data signal and the even data signal, respectively, and the second and fifth delay signals are respectively received. Of the first delay device and the fourth delay device, respectively, and the third and sixth delay devices receive the outputs of the second and fifth delay devices, respectively. The first and second multipliers receive the output of the first delay device, and the third and fourth multipliers receive the output of the second delay device. The fifth multiplier receives the output of the third delay device, the sixth multiplier receives the output of the fourth delay device, and The seventh and eighth multipliers receive the output of the fifth delay device,
The ninth and tenth multipliers receive the output of the sixth delay device, and the first adder receives the outputs of the first, third and fifth multipliers. And
The second adder receives the outputs of the second and fourth multipliers, and the third adder is the sixth,
The fourth and fifth adders receive the outputs of the eighth and tenth multipliers, the fourth and fifth adders receive the outputs of the seventh and ninth multipliers, respectively. It receives the outputs of the first and fourth adders and outputs the odd filter signal as the output of the fifth adder, and the sixth adder is configured to add the second and third adders. A parallel processing type FIR filter that receives the output of the second adder and outputs the even filter signal is obtained as the output of the sixth adder.

Further, according to the present invention, as the second parallel processing type FIR filter, each of the first and second parallel processing type FIR filters includes a first to a sixth delay device and a first delay device, respectively. Defined first to sixth of the first to sixth multiplication factors
And a first to an eighth adder, wherein each of the first to the sixth delay devices has a predetermined time as a delay time. And the fourth multiplication coefficient are equal to each other, and the second and fifth multiplication coefficients are equal to each other.
Multiplication coefficients are equal to each other, the third and sixth multiplication coefficients are equal to each other, and the first and fourth delay devices are
Receiving the odd data signal and the even data signal, respectively, the second and fifth delay devices receiving the outputs of the first and fourth delay devices, respectively, and The sixth delay device receives the outputs of the second and fifth delay devices, respectively, and the first adder is
Receives the outputs of the first and third delay devices,
The second adder receives the outputs of the first and second delay devices, and the third adder receives the outputs of the fourth and sixth delay devices, The fourth adder receives the outputs of the fifth and sixth delay devices, the first multiplier receives the output of the first adder, and the second adder The multiplier of
Of the third adder, the third multiplier receives the output of the second delay device, and the fourth multiplier outputs the output of the third adder. The fifth multiplier receives the output of the fourth adder, the sixth multiplier receives the output of the fifth delayer, and The fifth adder receives the outputs of the first and third multipliers, the sixth adder receives the outputs of the fourth and sixth multipliers, and The seventh adder receives the outputs of the fifth adder and the fifth multiplier, and outputs the seventh adder.
The output of the odd-numbered filter signal is output as the output of the second adder, and the eighth adder receives the outputs of the sixth adder and the second multiplier and receives the eighth adder. A parallel processing type FIR filter that outputs the even filter signal is obtained as the output of the.

Further, according to the present invention, as the third parallel processing type FIR filter, each of the first and second parallel processing type FIR filters includes a first to a sixth delay device and a first delay device, respectively. 1st to 8th defined 1st to 8th multiplication coefficients
, And first to sixth adders, wherein each of the first to sixth delay devices has a predetermined time as a delay time. ,
The fourth, fifth, and eighth multiplication coefficients are equal to each other, the second, third, sixth, and seventh multiplication coefficients are equal to each other, and the first and fourth delay devices are respectively An odd number data signal and an even number data signal; the second and fifth delay devices receive the outputs of the first and fourth delay devices, respectively; and the third and sixth delay devices, respectively. The delay device receives the outputs of the second and fifth delay devices, respectively, and the first multiplier receives the output of the first delay device, and the second and fifth delay devices, respectively. The third multiplier receives the output of the second delay device, the fourth multiplier receives the output of the third delay device, and the fifth and sixth multipliers. Is for receiving the output of the fifth delay device, and the seventh and eighth multipliers are the sixth delay device. The first adder receives an output, the first adder receives an output of the first and third multipliers, and the second adder receives the outputs of the second and fourth multipliers. The third adder receives the outputs of the fifth and seventh multipliers, and the fourth adder receives the outputs of the sixth and eighth multipliers. An output is received, the fifth adder receives the outputs of the second and third adders, and outputs the odd-numbered filter signal as an output of the fifth adder, The sixth adder receives the outputs of the first and fourth adders and outputs the even filter signal as the output of the sixth adder.
A filter is obtained.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION A demodulator according to an embodiment of the present invention will be described in detail below with reference to the drawings.

(First Embodiment) As shown in FIG. 1, the demodulator according to the first embodiment of the present invention is of a quasi-coherent detection system.

The illustrated demodulator has a quadrature modulated IF.
Upon receiving the signal, first, quadrature detection is performed in an analog manner. I
The F signal is branched into two, one of which is the carrier frequency f output from the local oscillator 12 in the mixer 11.
It is multiplied by a Lo signal having a frequency fc ′ substantially the same as that of c and passed through a low pass filter 21. Further, the other of the branched IF signals is multiplied in the mixer 10 by a signal obtained by phase-shifting the Lo signal output from the local oscillator 12 by π / 2, and is passed through the low-pass filter 20. The signals filtered by the low-pass filters 20 and 21 become baseband (BB) signals that are orthogonal to each other. These signal channels are
Called Pch and Qch. These signals are I
It may be called a component and a Q component, or a real component and an imaginary component.

Here, the frequency fc 'is the predicted carrier frequency, and strictly speaking, the frequency fc and the frequency fc' do not match. Therefore, the output of the analog quadrature detection includes the rotation of the phase corresponding to the difference between the frequencies.

The A / D converters 30 and 31 respectively receive the P-channel and Q-channel quadrature-detected signals,
/ D conversion is performed, and a serial signal having a plurality of bits is output.

Here, the frequency of the sampling clock supplied to the A / D converters 30 and 31 is set in order to configure the roll-off filter by the digital signal processing circuit.
It is determined so as to follow the sampling theorem. The sampling rate in this embodiment is twice the modulation rate fs. When the modulation speed fs is not so high with respect to the operating speed of the circuit, the sampling rate may be 4fs or 8fs.

Whether the S / P converter 40 is the A / D converter 30
Receiving the P-channel serial signal output from
S / P conversion is performed with a data ratio of 2 to obtain an odd number of P-channel data.
A data signal and an even data signal. For example, continuous
Serial data bit D _n(N = 1, 2, 3, ...
・) Is the odd data bit D_2n-1And even data
D2n. These odd data signals and even
Each of the several data signals has the same signal rate as the modulation speed fs.
Have. Similarly, the S / P converter 41 is
Output an odd data signal and an even data signal.

The parallel processing type FIR filter 50 operates as a roll-off filter, filters P channel odd data signals and even data signals in parallel, and
The P channel odd-numbered filter signal and the even-numbered filter signal are output. Similarly, the parallel processing type FIR filter 51 performs the filtering process in parallel with respect to the Q channel odd number data signal and the even number data signal, and outputs the Q channel odd number filter signal and even number filter signal.

As shown in FIG. 2, the parallel processing type FIR filter 50 according to the present embodiment includes first to sixth delay devices 101 to 106 and first to tenth multiplication coefficients (tap coefficients), respectively. ) C-defined first to tenth multipliers (tap) 201 to 210 and first to sixth adders 301 to 306. The first to sixth delay devices 101 to 106 have a delay time equal to the reciprocal of the modulation speed fs (T = 1 / fs).

Since the parallel processing type FIR filter 50 operates as a roll-off filter, the multiplication coefficient becomes a discrete impulse response value of the filter. Specifically, the multiplication coefficients in the first, fifth, sixth and tenth multipliers are equal to each other (C−2 = C + 2), and the multiplication coefficients in the second, fourth, seventh and ninth multipliers are , Equal to each other (C-1 = C + 1). In addition, the multiplication coefficients in the third and eighth multipliers are equal to each other (C0). In addition,
Parallel processing type FIR filter 51 in the present embodiment
Has the same configuration and operates in the same manner as the parallel processing type FIR filter 50.

In more detail, the first and fourth delay devices 10
1, 104 respectively receive the odd data signal D _2n-1 and the even data signal D _2n . Second and fifth delay device 1
02 and 105 are the first and fourth delay devices 101 and 101, respectively.
The output of 104 is received. Third and sixth delay devices 103,
106 denotes second and fifth delay devices 102 and 105, respectively.
Receive the output of.

The first and second multipliers 201 and 202 are
The output of the first delay device 101 is received. The third and fourth multipliers 203 and 204 receive the output of the second delay device 102. The fifth multiplier 205 receives the output of the third delay device 103. The sixth multiplier 206 includes the fourth delay unit 10
Receive the output of 4. Seventh and eighth multipliers 207, 20
8 receives the output of the fifth delay device 105. The ninth and tenth multipliers 209 and 210 receive the output of the sixth delay device 106.

The first adder 301 receives the outputs of the first, third and fifth multipliers 201, 203 and 205. The second adder 302 includes the second and fourth multipliers 202, 2
04 output is received. The third adder 303 receives the outputs of the sixth, eighth and tenth multipliers 206, 208 and 210. The fourth adder 304 receives the outputs of the seventh and ninth multipliers 207 and 209. Fifth adder 305
Receives the outputs of the first and fourth adders 301 and 304, and outputs an odd filter signal as the output of the fifth adder 305. The sixth adder 306 has second and third
And outputs the even filter signal as the output of the sixth adder 306.

In other words, the circuit for processing the odd data signal and the even data signal has five taps 201 to 20 respectively.
It has 5,206-210. Upper taps 201-20
5 has a first set of first, third and fifth taps 201, 203 and 205 and a second set of second and fourth taps 202 and 204 so that the tap interval becomes 2.
It is divided into two groups. Lower taps 206-210
Similarly, the sixth, eighth and tenth taps 206,
It is divided into a third set of 208, 210 and a fourth set of seventh and ninth taps 207, 209. The adders 301, 302, 304, 304 add the outputs of the taps of the corresponding sets of the first to fourth sets. After that, the adders 305 and 306 prevent the taps from overlapping with each other, and adders 301 and 302 on the upper side.
And the outputs of the lower adders 303 and 304 are further added. As a result, when the adder 305 outputs the calculation results for D _{1 to} D ₅ , the adder 306 outputs the calculation results for D _{2 to} D ₆ . That is, the parallel processing type FIR filter calculates the velocity fs by
5 consecutive input data bits D _j , D _{j + 1} , D
Outputs corresponding to _{j + 2} , D _{j + 3} , and D _{j +4} (j is an integer) are generated.

Referring again to FIG. 1, the parallel processing type EPS
(Endless Phase Shifter) 60, carrier phase detector 61, loop filter 62, NCO (Numerical Control)
The red oscillator 63 constitutes a carrier recovery loop. Of these, the phase detector 6 for carrier wave
1, the loop filter 62, and the NCO 63 generate a carrier signal .

Specifically, the parallel processing type EPS 60 is
The odd and even filtered signals of the channel,
Receiving the odd-numbered filter signal and the even-numbered filter signal of the Q channel, the carrier wave signal is used for phase shift, and the first to fourth phase shift signals are output. The first and second phase shift signals are
The P-channel odd-numbered filter signal corresponds to the even-numbered filter signal, and the third and fourth phase shift signals correspond to the Q-channel odd-numbered filter signal and the even-numbered filter signal. In this way, the parallel processing type EPS6
0 is a processing speed equal to the modulation speed fs and removes the phase shift (rotation) remaining in the analog quadrature detection.

Referring to FIG. 3, a parallel processing type EPS 60.
_Comprises two complex multipliers for the odd filtered signal (D _2n-1 ) and the even filtered signal (D _2n ).

The upper complex multiplier is for processing the odd filtered signal (D _2n−1 ) and has a multiplier 2
11 to 214, a subtractor 311, and an adder 312, and using the first digital carrier signal CARR1 input from the NCO 63 as the carrier signal corresponding to the odd filter signal (D2n _-1 ), Remove the gap.

More specifically, the multiplier 211 multiplies the P channel odd filter signal by the Cos component of the first digital carrier signal CARR1, and the multiplier 213 outputs Q.
The odd filter signal of the channel is multiplied by the Sin component of the first digital carrier signal CARR1. The subtractor 311 subtracts the output of the multiplier 213 from the output of the multiplier 211, and outputs the P-channel odd filter signal from which the phase rotation has been removed, as the first phase shift signal. Similarly, the multiplier 214 multiplies the Q channel odd filter signal by the Cos component of the first digital carrier signal CARR1, and the multiplier 212 calculates the first digital carrier signal for the P channel odd filter signal. S of signal CARR1
Multiplies the in component. The adder 312 adds the output of the multiplier 214 and the output of the multiplier 212, and outputs the Q-channel odd-numbered filter signal from which the phase rotation has been removed, as a third phase shift signal.

The lower complex multiplier is for processing the even filtered signal (D _2n ), and the multiplier 215
˜218, a subtractor 313, and an adder 314. This complex multiplier uses the second digital carrier signal CARR2 input as the carrier signal corresponding to the even filter signal (D _2n ) from the NCO 63 to remove the phase shift and to perform the second and fourth phase shifts. Output a signal. Since the operation of the lower complex multiplier is the same as that of the upper complex multiplier, the description is omitted.

In this way, the parallel processing type EPS 60
Outputs first to fourth phase shift signals. These two sets of parallel outputs (first and third phase shift signals or second and fourth phase shift signals)
Signal of the timing corresponding to the opening of the eye pattern becomes the P channel and Q channel demodulation signals. In the present embodiment, the first and third phase shift signals are P channel and Q channel demodulation signals, respectively.

As shown in FIG. 1, the carrier phase detector 63 monitors the P-channel and Q-channel demodulated signals and detects the phase shift of the demodulated signals from the reference point. The operation speed of the carrier phase detector 63 is equal to the modulation speed fs.

The phase shift detected by the carrier phase detector 63 passes through the loop filter 62 and is transmitted to the NCO 63.

As shown in FIG. 4, the loop filter 62 is a quadratic perfect integral type and has two multipliers 221 and
222, two adders 321, 322, and delay device 11
1 and. The multipliers 221 and 222 are respectively
The output of the phase detector 63 is multiplied by α and β which are parameters for determining the loop characteristic. The output of the multiplier 211 is further cumulatively added by the adder 321 and the delay device 111. That is, the adder 321 and the delay device 111 form an integrator. The adder 322 adds the output of the delay device 111 and the output of the multiplier 222 to generate the output of the loop filter 62. In the present embodiment, the processing speed of this loop filter is equal to the modulation speed fs.

As shown in FIG. 5, the NCO 63 has adders 323, 324, delayers 112, 113 and ROM.
It comprises 401 and 402, and is configured to be suitable for parallel processing. Adders 323 and 324 and delay devices 112 and 1
13 forms two accumulators, one output of which influences the other. Loop filter 62
Although the output of is corresponding to the frequency, the output of the loop filter 62 is integrated by this cumulative adder,
It is converted into an amount corresponding to the phase. ROM 120, 121
Stores the phase and the data of the digital carrier signals CARR1 and CARR2 preliminarily calculated corresponding thereto, specifically, the data of the Sin · Cos component in association with each other. Actually, the ROMs 120 and 121 are
They have the same contents as each other. Such ROM 120, 1
When a phase is given to the delay units 112 and 113 from the delay units 21, the ROMs 120 and 121 use the given phases as addresses, and the corresponding digital carrier wave signals CAR
R1 and CARR2 are output. The digital carrier signals CARR1 and CARR2 are, as described above, the NCO6.
3 is supplied.

In FIG. 1, the clock phase detector 70,
Loop filter 71, D / A converter 72, VCO 73,
A / D converters 30, 31, S / P converters 40, 41, parallel processing type FIR filters 50, 51, and parallel processing type EP
S60 constitutes a clock synchronization loop.

More specifically, the clock phase detector 70 includes delay units 121 to 124 and EX-O as shown in FIG.
R gates 501 to 504, OR gate 505 and F / F
It is equipped with 510.

Of these, the delay device 121 and the EX-OR gate 501 mainly play a role of detecting a condition for obtaining a P-channel clock phase. On the other hand, the delay device 123 and the EX-OR gate 503 mainly serve to detect the condition for obtaining the clock phase of the Q channel. Regarding both the P channel and the Q channel, the condition for obtaining the clock phase is that the polarity of the first data signal and the third data signal of the continuous three data signals is opposite. That is, if three consecutive data signals are D1, D2 and D3, D1
And the MSBs of D3 may be different from each other. In the illustrated clock phase detector 70, the condition is determined by referring to the MSBs of the first and / or third phase shift signals corresponding to the odd filter signal.

Delay device 122 and EX-OR gate 502
Together with the delay device 121 mainly serve to detect the clock phase information of the P channel. Similarly, the delay device 124 and the EX-OR gate 504, together with the delay device 123, mainly serve to detect the clock phase information of the Q channel. Specifically, for both the P and Q channels, the clock phase detector 70
If D2 and D1 have the same polarity, it is determined that the phase is advanced, and if D2 and D1 have different polarities, it is determined that the phase is being sent, and the determination result is generated as phase information.

Particularly, in the clock phase detector 70 according to the present embodiment, the OR gate 505 is the EX-OR.
The OR of the outputs of the gates 501 and 503 is output as information indicating whether or not the above condition is satisfied.
As a result, the output of the OR gate 505 indicates "1 (valid)" when the above-described conditions are satisfied for either or both of the P channel and the Q channel.

Referring to FIG. 7, there is shown the relationship between three consecutive data signals D1 to D3 and the eye pattern. D1 to D3 sampled by the A / D converter 30 (31) have sampling periods Ts / 2 (= 1 /
It appears every 2 fs). After that, the S / P converter 40 (4
When serial-parallel conversion is performed by 1), D1 and D2
Are parallel to each other, while the distance between D1 and D3 remains Ts. If the polarities of D1 and D3 are opposite, there is a zero cross point somewhere in between. When clock control is performed using the phase information detected as described above, D2
The clock phase corresponding to is adjusted to be the zero cross point.

The loop filter 71 is set to F / F only when the output of the clock phase detector 70 indicates "valid".
The filter operation is performed according to the phase information output from F510. Since the loop filter 71 itself functions in the same manner as the loop filter 62 in the carrier recovery loop,
It has the circuit configuration shown in FIG. However, since the loop characteristics of the loop filter 71 and the loop filter 62 are different, their coefficients α and β are not necessarily the same.

The VCO 73 receives the output of the loop filter 71 through the D / A converter 72, generates a sampling clock, and supplies it to the A / D converters 30 and 31. As is apparent from the arrangement shown, the VCO 7 shown
3 is an analog circuit. This is because it is necessary to use a clock having a frequency much higher than the modulation speed fs in order to perform clock synchronization by digital signal processing, but if the modulation speed fs exceeds 10 MHz, digitize the VCO. Because it is difficult. If the modulation speed fs has a low frequency, a digital VCO may be used instead of the D / A converter 72 and VCO 73.

In this way, the phase detector 70 detects the phase relationship between the analog baseband signal and the sampling clock, and the oscillation frequency of the VCO 73 is controlled according to the detection result, so that the clock phase is always
Optimal phase for sampling. Such clock phase control is disclosed in, for example, Japanese Patent No. 2848420.

As described above, the demodulator according to the first embodiment performs the demodulation processing at a speed equal to the modulation speed fs instead of the sampling rate 2fs by performing the S / P conversion after the A / D conversion. be able to.

For the sake of clarity, the demodulator shown in FIG. 8 will be described as a comparative example. The demodulator of the comparative example does not perform S / P conversion after A / D conversion. for that reason,
The FIR filters 52 and 53, the EPS 65 and the like operate at a sampling rate of 2fs.

Specifically, as shown in FIG. 9, the FIR filter 52 includes delay units 601-605 and a multiplier 70.
1 to 705 and an adder 801. Delay device 601
The delay time at ˜605 is not the reciprocal of the modulation rate fs, but the reciprocal of the sampling rate 2fs. That is, the FIR filter 52 operates at twice the speed of the parallel processing FIR filter 50 shown in FIG.

The EPS 65 is composed of a single complex multiplier having multipliers 711 to 714, a subtractor 811, and an adder 812, as shown in FIG. The data rate of the input / output signal of this complex multiplier is twice the modulation rate. That is, the EPS 65 operates at twice the speed of the parallel processing type EPS 60 shown in FIG.

Therefore, in order to supply the carrier signal CARR to the EPS 65 at the data rate of 2fs, the NCO 68 needs to operate with a clock of 2fs as shown in FIG. Specifically, the NCO 68 has an adder 813, a delay device 611, and a ROM 410. The adder 813 cumulatively adds the outputs of the delay device 611, and thus the adder 813 and the delay device 611 form an integrator. The information stored in the ROM 410 is the same as the information stored in the ROMs 401 and 402 shown in FIG.

Referring to FIG. 12, there is shown the relationship between the data held in the delay device 611 in FIG. 11 and the data held in the delay devices 112 and 113 shown in FIG. As understood from FIG. 12, the odd-numbered data held by the delay device 611 in FIG. 11 is held by the delay device 112 in FIG. 5, and the even-numbered data held by the delay device 611 in FIG. The delay unit 113 in FIG.

Referring again to FIG. 8, thinning circuits 66 and 67 are provided after the EPS 65. EPS6
The output of No. 5 is decimated by the decimating circuits 66 and 67 for each sample and becomes a demodulated signal.

Referring to FIG. 13, there is shown a configuration of a clock phase detector 74 according to a comparative example. The clock phase detector 74 basically has the same function as the clock phase detector 70. However, since the input to the clock phase detector 74 has a double data rate as compared to the input to the clock phase detector 70, the clock phase detector 74 outputs the positive phase output and the negative phase output of the divide-by-2 circuit 530. , The delay device corresponding to the odd-numbered data signal and the delay device corresponding to the even-numbered data signal are alternately operated to reduce the data rate to the modulation speed, determine the condition, and detect the phase information. ing.

As described above, the demodulator shown in FIG. 8 has components which must be operated at a speed twice the modulation speed in any of the roll-off filter, the carrier recovery loop, and the clock synchronization loop. The demodulator shown in FIG. 1 is capable of operating all components at a rate equal to the modulation rate. Therefore, it is understood that the demodulator shown in FIG. 1 is more suitable for the high speed communication system than the demodulator shown in FIG.

Next, the parallel processing type FIR filters 50, 5
Another example of the first example will be described with reference to FIGS. 14 to 17.

The parallel processing type FIR filter shown in FIG. 14 is a modification of the parallel processing type FIR filter shown in FIG. As described above, in order to operate as the roll-off filter, the coefficient of the multiplier in the parallel processing type FIR filter 50 has been determined to be C + n = C−n. By utilizing the symmetry of this tap coefficient, FIG.
In the parallel processing type FIR filter shown in FIG.
The number of multipliers is reduced by adding in advance the inputs of the multipliers having the same multiplication coefficient among the multipliers shown in FIG. As a result, for example, when a parallel processing type FIR filter having the same function as that of the serial FIR filter having 2n + 1 taps is configured, if the parallel processing type FIR filter shown in FIG. 14 taps are required,
In order to realize it in the same manner as the parallel processing type FIR filter shown in FIG. 1, it is sufficient to have 2n + 2 taps.

Specifically, the parallel processing type FIR filter shown in FIG. 14 includes first to sixth delay devices 101 to 1.
06, the first to sixth multipliers 231-236, and the first
Through 8 th adders 331 to 338. First
The sixth to sixth delay devices 101 to 106 are the same as those shown in FIG. 2, and the delay time thereof is T = 1 / fs. Further, the coefficients of the first and fourth multipliers 231 and 234 are equal to each other, and the second and fifth multipliers 232 and 2
The coefficients of 35 are equal to each other. Furthermore, the coefficients of the third and sixth multipliers 233, 236 are equal to each other.

The first and fourth delay devices 101 and 104 are
_Each receives an odd data signal (D _2n-1 ) and an even data signal (D _2n ) from the S / P converter. The second and fifth delay devices 102 and 105 receive the outputs of the first and fourth delay devices 101 and 104, respectively. The third and sixth delay devices 103 and 106 receive the outputs of the second and fifth delay devices 102 and 105, respectively.

The first adder 331 receives the outputs of the first and third delay devices 101 and 103. Second adder 33
2 receives the outputs of the first and second delay devices 101 and 102. The third adder 333 includes the fourth and sixth delay units 1
04,106 output is received. The fourth adder 334 is
The outputs of the fifth and sixth delay devices 105 and 106 are received.

The first multiplier 231 is the first adder 33.
Receives the output of 1. The second multiplier 232 receives the output of the second adder 332. The third multiplier 233 has a second
Receives the output of the delay device 102. Fourth multiplier 234
Receives the output of the third adder 333. The fifth multiplier 235 receives the output of the fourth adder 334. The sixth multiplier 236 receives the output of the fifth delay device 105.

The fifth adder 335 receives the outputs of the first and third multipliers 231 and 233. Sixth adder 33
6 receives the outputs of the fourth and sixth multipliers 234 and 236.

The seventh adder 337 is the fifth adder 33.
It receives the outputs of the fifth and fifth multipliers 235 and outputs the odd filter signal as the output of the seventh adder 337. The eighth adder 338 receives the outputs of the sixth adder 336 and the second multiplier 232, and outputs an even filter signal as the output of the eighth adder 338.

The parallel processing type FI shown in FIGS. 2 and 14.
The R filter has a type with an odd number of taps, whereas the parallel processing type FIR filter shown in FIG. 15 has a type with an even number of taps. In particular, the parallel processing type FIR filter shown in FIG. 15 calculates four continuous input data bits D _j , D _j by calculating the speed fs.
Outputs corresponding to D _{j + 1} , D _{j + 2} , D _{j + 3} (j is an integer) are generated.

More specifically, the parallel processing type F shown in FIG.
The IR filter includes first to sixth delay devices 101 to 106.
And first to eighth multipliers 241 to 248 and first to sixth adders 341 to 346. The first to sixth delay devices 101 to 106 are the same as those shown in FIG. 2, and the delay time thereof is T = 1 / fs. Also, the first, fourth, fifth and eighth multipliers 241,
The coefficients of 244, 245, 248 are equal to each other, and the second, third, sixth and seventh multipliers 242, 243, 24
The coefficients of 6,247 are equal to each other.

The first and fourth delay devices 101 and 104 are
_Each receives an odd data signal (D _2n-1 ) and an even data signal (D _2n ) from the S / P converter. The second and fifth delay devices 102 and 105 receive the outputs of the first and fourth delay devices 101 and 104, respectively. The third and sixth delay devices 103 and 106 receive the outputs of the second and fifth delay devices 102 and 105, respectively.

The first multiplier 241 is the first delay unit 10
Receives the output of 1. Second and third multipliers 242, 24
3 receives the output of the second delay device 102. The fourth multiplier 104 receives the output of the third delay device 103. Fifth
And the multipliers 105 and 106 of the fifth and sixth delay units 105 and 106, respectively.
Receive the output of. Seventh and eighth multipliers 107, 108
Receives the output of the sixth delay device 106.

The first adder 341 receives the outputs of the first and third multipliers 241 and 243. Second adder 34
2 receives the outputs of the second and fourth multipliers 242, 244. The third adder 343 is connected to the fifth and seventh multipliers 2
It receives the outputs of 45 and 247. The fourth adder 344 is
The outputs of the sixth and eighth multipliers 246 and 248 are received.

The fifth adder 345 receives the outputs of the second and third adders 342 and 343 and receives the fifth adder 34.
As an output of 5, an odd number filter signal is output. The sixth adder 346 includes the first and fourth adders 341 and 344.
And outputs an even filter signal as the output of the sixth adder 346.

The parallel processing type FIR filters shown in FIGS. 2, 14, and 15 perform two parallel processings, and can be adopted, for example, when the sampling rate is twice the modulation rate. Is. On the other hand,
The parallel processing type FIR filter shown in 6 performs four parallel processing, and can be adopted, for example, when the sampling rate is four times the modulation rate.

When the sampling rate is four times the modulation rate, the S / P converter converts one serial signal into four parallel signals D _4n-3 , D with a data ratio of 1: 4.
_4n−2 , D _4n−1 , D _4n .

The parallel processing type FIR filter shown in FIG. 16 has four parallel signals D _{4n −3} , D _{4n −2} ,
Each of D _4n−1 and D _4n has 11 taps. The 11 taps are divided into four groups, respectively. Each set is configured so that the tap interval is 4. A total of 16 sets of tap outputs are added by any of the four adders provided in the final stage.
At this time, the taps of each set are selected so that they do not overlap with each other, and one set of taps is selected from each stage. With this configuration,
From the last four adders, for example, D ₁ to
The calculation results for D ₁₁ , D _{2 to} D ₁₂ , D _{3 to} D ₁₃ , and D _{4 to} D ₁₄ are output. Thus, the parallel processing type FIR filter shown in FIG. 16 produces | generates the output corresponding to 11 continuous input data bits by the calculation of speed fs.

The parallel processing type FIR filter shown in FIG.
There are four outputs of the data. After parallel processing type FIR filter
The EPS provided in the stage has two of these four signals.
If you input a book signal, the clock phase information will be output at the output stage.
Can be obtained. For example, in FIG.
_4n-3And D_4n-1Only or D_4n-2And D_4n
If only inputting into the EPS, EPS is
You can leave the configuration as it is. In this case, do not select
It was D_4n-2And D_4nOr D_4n-3And D
_4n-1The combination of is discarded, for example.

Referring to FIG. 17, another example of the parallel processing type FIR filter is shown. The illustrated parallel processing type FIR filter is a modified example of the parallel processing type FIR filter shown in FIG. 16 under the condition that the outputs of D _4n-3 and D _4n-1 are not selected and discarded. . Figure 1
Parallel Processing FIR filter shown in 7, in the parallel processing type FIR filter shown in FIG. _{16, D 4n-3}
, And the multiplier, adder, and delay device related only to the output of D _4n−1 are omitted. This parallel processing type F
A simplification method as shown in FIG. 14 can also be applied to the IR filter.

The demodulator according to the second embodiment of the present invention will be described below with reference to FIGS. 18 and 19. In the demodulator shown in FIG. 18, the frequency of the signal output from the local oscillator 13 is fc'-fs. This signal is multiplied in the mixer 10 by the IF signal having the carrier frequency fc. As a result, the IF signal having the carrier frequency fc is frequency-converted into an IF signal having the same frequency as the modulation speed fs as a pseudo carrier frequency. Here, the frequency of the signal output from the local oscillator 13 is f
It may be c '+ fs. However, in this case, it is necessary to correct the rotation direction of the phase in the subsequent processing.

IF having such a pseudo carrier frequency fs
The signal is sampled in the A / D converter 30 after passing through the low pass filter 20. As shown in FIG. 18, the sampling rate in the A / D converter 30 is 4fs. The data sequence sampled in this way is input to the quadrature detector 80.

The quadrature detector 80 processes this data sequence and outputs Pch data rates of fs.
_Odd , Pch _Even , Qch _Odd , Qch
_It outputs four parallel baseband signals of _Even .

More specifically, if an IF signal having a frequency of fs is sampled with a clock of 4 fs, Sin, Co
2 fs BB signals of P channel and Q channel can be obtained from the relationship of s. That is, quadrature detection can be performed. Here, within one cycle of the carrier wave, S of the carrier wave
The in component and the Cos component each become “0” twice. At that time, the other shows "1" or "-1".
That is, when sampling is performed at the timing when either the Sin component or the Cos component of the carrier wave becomes “0”, the output is P, Q, P (BAR), Q (BAR), P,
Q, ... Here, (BAR) indicates that the signal is an inverted signal.

Referring to FIG. 19, the quadrature detector 80 is
Digital signal processing is performed based on the principle described above. The illustrated quadrature detector 80 also has an S / P conversion function. The quadrature detector 80 converts the serial data sequence having the data rate of 4fs output from the A / D converter 30 into four parallel data sequences by the delay devices 901 to 904. Of these, delay device 9
Assuming that the outputs of 04 and 902 are P-channel signals, the outputs of the delay devices 903 and 901 are Q-channel signals. The P-channel and Q-channel signals are input to the delay devices 905 and 906, which operate at the speed fs, and the speed is converted. Further, one of the outputs of the delay device 905 is inverted by the inverter 907. Similarly, one of the outputs of the delay device 906 is inverted by the inverter 908. In this way, the quadrature detector 80 outputs two P channel signals and two Q channel signals that are parallel to each other.

The signal processing in the subsequent stage of the quadrature detector 80 is performed in the same manner as the signal processing in the above-described first embodiment. Therefore, the demodulator according to the second embodiment is, for example, a roll-off filter as shown in FIG.
The parallel processing type FIR filter shown in any one of FIG. 4, FIG. 15, FIG. 16 and FIG. 17 can be adopted.

As described above, in the demodulator according to the second embodiment, unlike the demodulator according to the first embodiment, quadrature detection is performed by digital signal processing. In addition, for quadrature detection of digital signal processing,
The sampling frequency is four times the modulation speed,
The subsequent processing including the roll-off filter is performed at the same speed as the modulation speed.

Next, a demodulator according to the third embodiment of the present invention will be described with reference to FIG. The demodulators according to the first and second embodiments described above are of the quasi-coherent detection type, but the demodulator shown in FIG. 20 is not of the quasi-coherent detection type.

The demodulator shown in FIG. 20 is of the synchronous detection type in which the eye pattern is open at the inputs of the A / D converters 30 and 31. Therefore, no EPS is provided in the demodulator shown in FIG. Also in this example, the roll-off filters 50 and 51 and the clock phase detector 70 perform digital signal processing.

It should be noted here that the loop filter 92 in the carrier recovery loop shown in FIG. 20 is formed of an analog circuit. However, the carrier phase detector 91 and the loop filter 92 are digitized,
A D / A converter may be provided after the loop filter 92. For other components and their operation,
This is similar to the above-described first embodiment. Therefore, the demodulator according to the third embodiment may employ, for example, the parallel processing type FIR filter shown in any of FIGS. 2, 14, 15, 16, and 17 as the roll-off filter. it can.

Although the present invention has been specifically described above with reference to the embodiments, these embodiments do not limit the concept of the present invention. For example, in the above-described first and second embodiments, the clock synchronization is performed using the output of the EPS, but the clock synchronization may be performed using the output of the roll-off filter. In this case, the configuration of the loop filter 71, the D / A converter 72, etc. is provided except that the MSBs of the four outputs of the two roll-off filters for the clock phase detector 70 are input to the clock phase detector 70. No need to change.

[0088]

As described above, according to the present invention,
The digital processing speed in the demodulator is the modulation speed fs.
Is equal to Therefore, the demodulator according to the present invention can be applied to a high-speed communication system. In addition, as the digital processing speed in the demodulator decreases, the number of stages in pipeline processing can be reduced, and as a result, in the demodulator, the circuit size and the delay without the control loop are reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a demodulator according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an example of the parallel processing type FIR filter shown in FIG.

FIG. 3 is a block diagram showing an example of the parallel processing type EPS shown in FIG.

4 is a block diagram showing an example of an LPF in the carrier recovery loop shown in FIG.

FIG. 5 is a block diagram showing an example of the NCO shown in FIG.

FIG. 6 is a block diagram showing an example of the clock phase detector shown in FIG. 1.

7 is a diagram used to explain phase detection in the clock phase detector shown in FIG. 6;

FIG. 8 is a block diagram showing a demodulator (comparative example) that performs a demodulation process at a speed twice the modulation speed.

FIG. 9 is a diagram showing a configuration of the FIR filter shown in FIG. 8.

10 is a diagram showing a configuration of the EPS shown in FIG.

11 is a diagram showing a configuration of the NCO shown in FIG.

FIG. 12 is an NCO shown in FIGS. 5 and 11.
It is a figure which shows the relationship of the data stored in the delay device (F / F) contained in FIG.

13 is a diagram showing a configuration of the clock phase detector shown in FIG.

14 is a parallel processing type FIR shown in FIG. 1;
It is a block diagram which shows another example of a filter.

15 is a parallel processing type FIR shown in FIG.
It is a block diagram which shows another example of a filter.

FIG. 16 is a block diagram showing an example of a parallel processing type FIR filter when the sampling rate is 4 times the modulation rate.

17 is a parallel processing type FI shown in FIG.
It is a figure which shows the modification of an R filter.

FIG. 18 is a block diagram showing a schematic configuration of a demodulator according to a second embodiment of the present invention.

FIG. 19 is a diagram showing an example of the quadrature detector shown in FIG. 18.

FIG. 20 is a block diagram showing a schematic configuration of a demodulator according to a third embodiment of the present invention.

[Explanation of symbols]

10 mixer (multiplier) 11 Mixer (multiplier) 12 Local oscillator 20 low-pass filter 21 Low-pass filter 30 A / D converter 31 A / D converter 40 S / P converter 41 S / P converter 50 Parallel processing FIR filter 51 Parallel processing type FIR filter 60 Parallel processing type EPS 61 Carrier Phase Detector 62 loop filter 63 NCO 70 Clock phase detector 71 loop filter 72 D / A converter 73 VCO

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 27/00-27/38 H03H 17/02

Claims (11)

(57) [Claims] 1. A first and a second quadrature orthogonal to each other, receiving an IF signal subjected to quadrature modulation, performing analog quadrature detection using a predicted carrier frequency having a frequency substantially the same as an actual carrier frequency. An analog quadrature detector which outputs a detection signal, and the first and second quadrature detection signals which receive the first and second quadrature detection signals, respectively, perform A / D conversion at a speed twice or more a modulation speed. First and second A / D converters that output serial signals; and first and second serial signals that are composed of a plurality of signal trains each having the same data rate as the modulation rate. First and second serial-parallel converters for converting into two parallel signals, and a first filter signal pair formed of two filter signals by filtering the first parallel signals in parallel at the modulation speed. A first parallel processing type FIR filter operating as a roll-off filter for outputting said second parallel signal by filtering parallel by the modulation rate, the second filter signal consisting of two filter signal in response to the second parallel processing type and FIR filter, the first and second filter signal to operating as a roll-off filter for outputting a pair of carrier signals
Signal in the analog quadrature detector processing.
The phase shift process that removes the phase shift
And a parallel phase shifter that outputs the first and second demodulated signals
And monitoring the first and second demodulated signals to detect the carrier wave.
A carrier signal generator for generating a signal, and a demodulator. 2. The carrier signal generator receives the first and second demodulated signals and receives the first and second demodulated signals.
Carrier phase detector for detecting a phase shift of the demodulated signal from the reference point, a loop filter connected to the carrier phase detector, and the first and second filter signal pairs connected to the loop filter. An NCO for generating corresponding first and second carrier signals , respectively, wherein the parallel phase shifter uses the first and second carrier signals to synchronize the first and second carrier signals with each other. The demodulator according to claim 1 , which outputs two demodulated signals. 3. The parallel phase shifter outputs first to fourth phase shift signals as a result of the phase shift processing, and the first and second phase shift signals are the second phase shift signals. 1 is generated corresponding to the first filter signal pair, the third and fourth phase shift signals are generated corresponding to the second filter signal pair, the first and second The second demodulated signal includes the first and third demodulated signals, respectively.
2. The demodulator according to claim 1 , wherein the demodulator is a phase-shifted signal. 4. M of each of the first to fourth phase shift signals
A clock phase detector for detecting a clock phase by referring to SB, a loop filter connected to the clock phase detector, and a D / A converter for D / A converting the output of the loop filter.
A converter and a V which supplies a sampling clock controlled according to the output of the D / A converter to the A / D converter
The demodulator according to claim 3 , further comprising a CO. 5. A clock phase detector for detecting a clock phase by referring to the MSB of each of a total of four filter signals constituting the first and second filter signal pairs, and a clock phase detector connected to the clock phase detector. A loop filter, a D / A converter for D / A converting the output of the loop filter, and a VCO for supplying a sampling clock controlled according to the output of the D / A converter to the A / D converter. The demodulator according to claim 3 , further comprising: a demodulator. 6. The A / D converter has a modulation rate of 2
The A / D conversion is performed twice, and each of the first and second parallel signals is an odd data signal and an even data signal, and the first parallel processing type FIR filter is an odd data signal. And a first parallel signal composed of an even data signal, filtering in parallel, and outputting the first filter signal pair composed of an odd filter signal and an even filter signal, the second parallel processing The type FIR filter receives a second parallel signal composed of an odd data signal and an even data signal, filters in parallel, and outputs the second filter signal pair composed of an odd filter signal and an even filter signal. The demodulator according to claim 1, wherein the demodulator is present. 7. The quadrature-modulated first IF signal is received, and detection is performed using a predetermined frequency whose modulation speed is a difference between an actual carrier frequency and a predicted carrier frequency having substantially the same frequency. An analog detector that outputs a second IF signal having a modulation carrier frequency as a pseudo carrier frequency and an A / D converter that receives the second IF signal and has a speed four times the modulation speed. A / D to output serial signal
A quadrature detector that receives the serial signal, performs quadrature detection, and outputs first and second parallel signals composed of a plurality of signal sequences having the same data rate as the modulation rate; the parallel signal by filtering parallel by the modulation rate, a first parallel processing type FIR filter operating as a roll-off filter to output a first filtered signal pair comprising two filters signal, the second the parallel signals by filtering parallel by the modulation rate, and a second parallel processing type FIR filter operating as a roll-off filter for outputting a second filtered signal pair comprising two filters signal, said first Receiving the first and second filter signal pairs,
The carrier signal indicating the phase error
Eliminates the remaining phase shift in the processing of the detector.
Phase shift processing is performed at the modulation speed, and the first and second demodulations are performed.
A parallel phase shifter for outputting a signal, and the carrier wave for monitoring the first and second demodulated signals
A carrier signal generator for generating a signal , and a demodulator, comprising: 8. The carrier signal generator receives the first and second demodulated signals and receives the first and second demodulated signals.
Carrier phase detector for detecting a phase shift of the demodulated signal from the reference point, a loop filter connected to the carrier phase detector, and the first and second filter signal pairs connected to the loop filter. An NCO for generating corresponding first and second carrier signals , respectively, wherein the parallel phase shifter includes the first and second carrier signals .
The demodulator according to claim 7 , wherein the first and second demodulation signals synchronized with a carrier wave are output using a carrier wave signal . 9. The parallel phase shifter outputs a set of first to fourth phase shift signals as a result of the phase shift processing, wherein the first and second phase shift signals are: The third and fourth phase shift signals are generated corresponding to the first filter signal pair, the third and fourth phase shift signals are generated corresponding to the second filter signal pair, and The first and second demodulated signals are respectively the first and third demodulated signals.
The demodulator according to claim 7 , wherein the demodulator is a phase-shifted signal. 10. A clock phase detector that detects a clock phase by referring to each MSB of the first to fourth phase shift signals, a loop filter connected to the clock phase detector, and the loop filter. D to D / A convert the output of
The demodulator according to claim 9 , further comprising an A / A converter and a VCO that supplies a sampling clock controlled according to an output of the D / A converter to the A / D converter. 11. A clock phase detector for detecting a clock phase by referring to respective MSBs of a total of four filter signals forming the first and second filter signal pairs, and a clock phase detector connected to the clock phase detector. A loop filter and a D / A converter for D / A converting the output of the loop filter,
The demodulator according to claim 9 , further comprising: a VCO that supplies a sampling clock controlled according to an output of the D / A converter to the A / D converter.