JP2689806B2 - Synchronous spread spectrum modulated wave demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for demodulating a carrier-modulated synchronous spread spectrum (hereinafter abbreviated as "SS") modulated wave, and more particularly to a demodulator which does not require a sync holding function. Type SS modulated wave demodulator (hereinafter also simply referred to as "demodulator"). In the following description, it is assumed that the demodulation device of the present invention is applied to a receiving unit of a communication device, and a transmitting unit (modulation circuit) will be described as needed.

[0002]

BACKGROUND ART In recent years, in SS communication, mobile communication using a multiple access method based on SS technology has reached a practical range. The main reason is that it is necessary to use frequencies effectively because radio resources are finite, whereas SS signals are being proved to be able to contribute to an improvement in frequency use efficiency by technological advances. In particular, the SS signal is spread over a wide frequency band, and the power spectrum density of the modulated wave is very small, so there is little effect on other conventional communication radio waves, etc. Therefore, it can be mixed in existing communication frequency bands. Therefore, there is a great advantage in that respect.
For these reasons, wireless communication by SS is becoming more and more familiar, and in the future, its future potential and developability such as application of communication between mobile bodies mounted on vehicles and the like are expected.

[0003]

2. Description of the Related Art In SS communication, synchronization acquisition and synchronization holding in reception are basically necessary, and various synchronization acquisition and holding methods have been proposed and put into practical use. Among them, PSK (Pha
se Shift Keying) Modulation carrier and secondary modulation S
Synchronous SS modulation and demodulation, in which the SS modulation is performed in synchronization with the spread code clock signal used for the S modulation, are also known as methods that can somewhat simplify the circuit configuration in reception demodulation. Regarding such a conventional technique, FIG.
The description will be made with reference to FIGS.

FIG. 1 shows a circuit configuration of a modulator on the side of a transmission unit for generating a transmission signal for the present demodulator, FIG. 2 shows a circuit configuration of a conventional demodulator for a synchronous SS modulated wave, and FIG. FIG. 4 shows a specific circuit configuration of a signal processing circuit which is a main part of a delay lock loop) type synchronization holding circuit, FIG. 4 shows a synchronization holding characteristic in a DLL type synchronization holding circuit, and FIG. 5 shows a correlation characteristic showing a sliding correlation type synchronization acquisition operation. , Respectively.

First, the SS modulator shown in FIG. 1 will be described. Information signal d such as data from the input terminal In1
(t) is the carrier cos for PSK modulation from the oscillator 19.
ωt is supplied to the multiplier 9 for PSK modulation, where the PSK modulation of the information d (t) is performed, and the PSK modulated wave d (t) cosωt is obtained. Further, the oscillator output is divided by a frequency divider 2
5, a clock signal is generated and a spread code generator (PNG) 48 generates a spread code p (t) based on the clock signal. Therefore, the output spreading code p (t) is kept in synchronization with the carrier cosωt. Spread code p
(t) is supplied to the multiplier 10 for spread modulation, where SS
(Spread spectrum) modulation is performed and SS modulated wave p (t) *
d (t) cosωt is generated, is output from the output terminal Out1 via the BPF (bandpass filter) 11, and is transmitted from an antenna (not shown).

Next, the demodulation operation will be described with reference to FIG. The SS modulated wave is received by an antenna (not shown) on the receiver side, and a multiplier 3 for both sliding correlation and despreading demodulation via a BPF 12 from an input terminal In2 and a DLL-type synchronization holding signal processing circuit. (Hereafter, simply "D
LL signal processing circuit "). The spread code generated by the PNG (spread code generator) 47 is also supplied to the multiplier 3, and the clock signal for this spread code is slightly higher than that at the time of holding the synchronization until the synchronization is acquired. It is set by a VCO (voltage controlled oscillator) 21. Therefore, the sliding correlation and the despread demodulation are performed in time series.

Here, the operation leading to synchronization acquisition (establishment) will be described. Input SS modulated wave p (t) * d (t) cos in which unnecessary frequency band components have been attenuated or removed by BPF 12
ωt is correlated by multiplication with the spread code p (t) from the spread code generator 47 in the multiplier 3. The spreading code p (t) is compared with the spread code p (t) generated by PNG4 8 of the sender, p actually having a delay time τ
(T−τ), which is Λ on the letter p of p (t)
Although it is written with a (hat), it will be represented by "ρ (t)" here because of the restrictions on the characters that can be used in electronic applications. Therefore, the multiplication output from the multiplier 3 is p
(T) * ρ (t) * d (t) cosωt.

The multiplication output is supplied to the multipliers 4 and 5 , and the multiplier 4 reproduces the carrier carrier cos from the VCO 22.
Synchronous detection is performed by multiplication with (ωt−φ). Therefore, from the multiplier 4 , (1/2) p (t) * ρ (t) *
d (t) * {cos φ + cos (2ωt−φ)}
Is output and the LPF (low-pass filter) of the next stage 15
And p (t) * ρ (t) * d (t) cos (2ωt−
φ) / 2 component is removed and p (t) * ρ (t) * d
(T) cos φ. If the value of φ is close to 0, the LPF15 output p (t) * ρ (t) * d (t) co
s φ becomes a level of about 1/2. On the other hand, in the multiplier 5, the reproduction carrier cos (ωt−φ) from the voltage controlled oscillator (VCO) 22 is sm (ωt−−) whose phase is shifted by π / 2 in the π / 2 phase shift circuit 23. φ) carrier is supplied.

Therefore, the output of the multiplier 5 is (-1/2) p (t) *.
ρ (t) d (t) * {sinφ + sin (2ωt-φ)}, and LPF16
Outputs -p (t) * ρ (t) sin φ, but the actual level is close to zero. The outputs of the LPF 15 and LPF 16 are both supplied to the multiplier 6, where multiplication is performed and the output is p ² (t) ρ ² (t) * d ² (t) * (-1/2) sin2φ
Is obtained as an error signal. The error signal is further filtered by a loop filter 24 which determines a response time constant of the loop.
After being converted into an error signal Ksin2φ, it is supplied to the VCO 22 as a control signal. In the carrier reproducing circuit 50 having such a single phase locked loop, the PSK demodulation can be performed simultaneously in synchronization with the input carrier.

[0010] After the power of the receiving section of the communication device is turned on, the carrier recovery circuit 50 starts working first. Therefore, after the carrier recovery, the correlation output p (t) * ρ (t) obtained from the LPF 15, That is, 3 around the point t ₀ in FIG.
The output based on the angular output characteristic is supplied to a threshold level detection circuit 34 for synchronous acquisition of sliding correlation, where after the synchronous acquisition point SHL is detected, it is further supplied to an output (waveform) shaping circuit 35 for synchronization. A constant DC output is obtained from the time of capture. This DC output is supplied to the adder circuit 42, where it is added to the correlation output from the DLL signal processing circuit 36 and then supplied to the VCO 21. The VCO 21 is controlled by the obtained addition output, and the controlled voltage-controlled oscillation output becomes a clock signal for generating a spread code at the time of normal synchronization holding.

Next, the synchronization holding operation will be described. The input SS modulated wave is supplied to the DLL signal processing circuit 36 via the BPF 12. Here, a specific circuit example of the DLL signal processing circuit 36 is shown in FIG. The SS modulated wave is supplied to the multipliers 7 and 8 from the input terminal In3.
Supplied to On the other hand, the input terminal In4 is connected to the multiplier 3
The spread code (a) whose phase is Δt earlier than the regular spread code p (t) supplied to the terminal (a) and the spread code (b) which is Δt late p (t + Δt) are input terminal In5. , PNG47
More individually supplied. In addition, since Δt is the time for one bit of the spread code in the SS method, that is, one chip time,
The output of the multiplier 7 is PSK which is the despreading output during normal operation.
It is a modulated wave, and the narrow band BPF4 that can transmit it.
Absolute value circuit (or envelope detection circuit) 3
8 is supplied.

Similarly, the output of the multiplier 8 is also supplied to the absolute value circuit 39 via the BPF 14 . Therefore, the output of the absolute value circuit 38 becomes a signal in which a component approximately twice the carrier frequency is multiplied by p (t) * p (t-Δt), and the output of the absolute value circuit 39 similarly has the carrier frequency. It is obtained as a signal in which the doubled component is multiplied by p (t) * p (t + Δt). The respective output signals are supplied to the subtraction circuit 40 to be subtracted and calculated, and the characteristic thereof is the inverse S-shaped correlation characteristic shown in FIG. 4, and the point (C) is the synchronization holding point. The correlation output thus obtained is output to the output terminal Out via the loop filter 28 for processing this into a control signal.
3 and is added to the output of the waveform shaping circuit 35 by the adder circuit 42 of FIG. 2 and then supplied to the VCO 21.
Synchronization is maintained.

[0013]

In such a conventional demodulator, the VCO 22 for carrier reproduction and the VCO 22 for clock generation are used.
There is a problem in that it is difficult to operate the circuit stably due to complication of the circuit and increase in the circuit scale, such that an oscillator is required for both the CO 21 and a synchronization holding circuit must be used together. It was happening.

[0014]

In order to solve the above-mentioned problems, the demodulation device of the present invention is a spread spectrum system in which a carrier for PSK modulation and a clock signal for a spread code used for spread modulation are synchronized. In a demodulation device for receiving and demodulating a modulated wave, despreading means for despreading by multiplying an input spread spectrum modulated wave by a spreading code output from a spreading code generator (47) to obtain a despread signal and (3), the despread signal from the despread means (3)
Branch into one and the other, and then split into one despread signal
The regenerated carrier from the voltage controlled oscillator (22)
Multiply each by a carrier obtained by shifting the raw carrier by π / 2
Then, the error signal of both is obtained and the voltage control is performed by this error signal.
The reproduction carrier is controlled by controlling the oscillator (22) in a closed loop.
Carrier regenerating means (50) for obtaining the above , and said despreading means
The despread signal and the voltage control branched from (3) to the other.
Multiply by the reproduction carrier from the oscillator (22)
Synchronous detection for synchronous detection to obtain despread demodulation signal
Means (4) and first frequency dividing means (26) for dividing the reproduction carrier from the voltage controlled oscillator (22) to 1 / N ₁ to generate a clock signal for holding synchronization. And the voltage
1 / N _{1 of the} reproduction carrier from the controlled oscillator (22)
A second frequency dividing means for generating a clock signal for synchronization acquisition be 1 / N ₂ frequency-divided small frequency division number from (27), before
Containing serial in said despread demodulated signal from the synchronous detection means (4)
And suppressing means for suppressing or removing the diffusion noise by taking out the Murrell diffuse noise component is subtracted or <br/> et the despread demodulation signal (41, 49), said suppression means (41 and 49)
And synchronization detection means for synchronizing detection for synchronization acquisition by sliding correlation with the output signal (34), before
Serial synchronous detection means (34) the first as a control signal to the synchronization detection signal from the second frequency dividing means (26, 27) is a clock signal of the clock signal and the synchronization acquisition for the synchronization hold the respective outputs There is provided a synchronous spread spectrum modulated wave demodulating device configured to selectively include switching means (Sw) for switching and outputting to the spread code generator (47) . Also,
In the above invention, the suppressing means is the synchronous detection means.
After removal of the frequency component of the information to be demodulated by the reverse spread demodulation signal split into one (4) high-pass filter (30)
To the spreading code from the spreading code generator (47)
And a component obtained by reciprocating this spread code by the reciprocal number conversion circuit (20) are sequentially multiplied by a multiplier (29, 28),
A diffusion noise reproducing section (4) for correcting and outputting the frequency band part of the information to be demodulated which has been removed by the number characteristic correcting circuit (31).
9) and before branching from the synchronous detection means (4) to the other
From the despread demodulation signal, the spread noise reproducing section (49)
The output signal is subtracted to obtain the frequency component of the information to be demodulated.
And a subtraction circuit (41) for taking out .

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of one embodiment of the demodulation device of the present invention will be described along with the configuration example shown in FIG. 6 together with the spread noise suppressing operation explanation spectrum diagram of FIG. FIG.
In, 19 is a correction filter (usually using LPF),
20 is an inverse circuit, Sw is a changeover switch, 26 and 27 are frequency dividers for dividing the input signal into 1 / N ₁ and 1 / N ₂ , respectively.
Reference numeral 9 is a diffused noise reproducing unit, and the same components as those of the conventional apparatus shown in FIG.

Interference waves that are not removed even by the BPF 12 may sometimes be mixed into the SS signal coming into the input terminal In2 of the demodulator 1 shown in FIG. 6 during transmission {see FIG. 8 (A)}. If such an interference wave is I (t) = cosεt, the input S
The S signal becomes p (t) * d (t) cosωt + cosεt, and the BPF
At 12, the high frequency components of the spread modulated wave are removed and {p (t)-
p ′ (t)} * d (t) cosωt + cosεt, which is supplied to the multiplier 3 for both despreading and sliding correlation.

When synchronization is established in the demodulator 1, the spreading code generated by the PNG 47 is p (t), and the correction filter 19 causes {p (t) -p '(t)}.
Then, in the reciprocal conversion circuit 20, {p (t) -p '
(T)} ⁻¹ and supplied to the multiplier 3. Therefore, the output of the despread signal from the multiplier 3 is d (t) cos
ωt + cosεt / {p (t) -p ′ (t)} {FIG. 8
(B) see} and that Do. This despread signal is
One of the despread signals is split and the carrier is recovered.
The other despread signal, which is supplied to the means 50 and branched, is supplied to the multiplier 4 for synchronous detection. At this time, the carrier
The reproducing means 50 is provided on one side in the same manner as described in the conventional example.
BPF having narrow band pass characteristic for branched despread signal
From the VCO (voltage controlled oscillator) 22
Play carrier and this play carrier were shifted by π / 2
LPF (low frequency range)
Filter 15) and 16) and then the multiplier 6
Signal and VCO (voltage controlled oscillator) with this error signal
22 to obtain a regeneration carrier while controlling the closed loop
is there.

In the multiplier 4, multiplication with the carrier for coherence detection cos (ωt-φ) output from the VCO 22 is performed, and d (t) cosωφ + cos (ωt-εt + φ) / {p (t)-
p ′ (t)} and is output to the diffusion noise reproducing unit 49 and the subtraction circuit 41 via the LPF 17. In addition, LPF17
The cutoff frequency is selected to be a frequency that can sufficiently transmit the spread frequency band. Further, the change in the amplitude in the above signal expression is omitted for convenience.

Here, the specific structure and function of the diffused noise reproducing section 49 will be described with reference to FIG. FIG. 7 is a block diagram showing an example of the configuration of the diffused noise reproducing section 49. The input signals (a) to (c) in FIG. 7 correspond to those shown in FIG. In FIG. 7, reference numeral 30 is a high-pass filter (HPF) for removing demodulation information, and 31 is a frequency characteristic correction circuit including an equalizer and the like.

The output from the LPF 17 is input terminal I
It is supplied to the HPF 30 via n6. In HPF 30, frequency SuNaru partial demodulation should do information is removed {8
(See (C)}, and is output to the multiplier 29. The multiplier 29 multiplies the output of the correction filter 19 {p (t) -p '(t)} (see FIG. 8D) and outputs the result to one input terminal of the multiplier 28. At the other input terminal of the multiplier 28, the inverse spread code {p (t) which has passed through the LPF 14 is transmitted.
-P '(t)} ^-1 is supplied. The LPF 14 is used to remove the high band part and side lobes of the main lobe of the frequency spectrum of the reciprocal spread code. Therefore, the low- and middle-frequency components of the main lobe of the reciprocal spreading code {Fig.
Only the reference (E)} is supplied to the multiplier 28. Therefore, from the multiplier 28, the frequency band component of the demodulation information lost by the HPF 30 is partially restored (FIG. 8). (Refer to (F)} is output.

The partial restoration output is supplied to the frequency characteristic correction circuit 31, where the partial restoration in the required frequency band is corrected to complete restoration, and the restored composite component {FIG. 8 (G).
Reference}. This restored composite component is supplied to the subtraction circuit 41 of FIG. 6 through the output terminal Out4, where it is subtracted from the sliding correlation output from the LPF 17, and the composite component is offset and greatly attenuated. {See FIG. 8 (H)}. That is, a correlation output with a good CN ratio (signal-to-noise ratio) in which spread noise is suppressed is obtained from the correlation output at the time of correlation and the composite component (spread noise) generated in the correlation operation time. Only the frequency component of the information that should be demodulated almost completely
{Refer to FIG. 8 (I)} The signal is output from the terminal Out2 and is also supplied to the synchronization determination circuit (synchronization acquisition threshold level detection circuit) 34.

In the synchronization determination circuit 34, the synchronization acquisition point SHL (see FIG.
(See) and supplies it to the shaping circuit 35,
A constant DC output is obtained from the time of synchronization acquisition. This DC output is used as a switching operation control signal for the changeover switch Sw. When the DC output is generated, the switch Sw is connected to the frequency divider 26 side so that the regular clock signal from the frequency divider 26 is spread-coded. It will be supplied to the generator (PNG) 47. As a result, the spreading code output from the PNG 47 becomes p (t), and the regular despreading is performed in the multiplier 3.

That is, the output signal of the shaping circuit 35 is generated when the SS synchronization is established, and is not generated when the SS synchronization is not established. With such a function, if some kind of strong interference occurs in the SS modulated wave and the process gain of the SS system is exceeded, SS synchronization is not maintained and the level of the interference wave is reduced. SS sync level (sync capture point SHL)
When it goes down, it operates to switch to sliding correlation operation.

Finally, the carrier reproducing operation will be described. The d (t) cosωt or cosωt component is extracted from the output signal of the multiplier 3 of FIG. 6 by the narrow band characteristic BPF 13, and is supplied to the multipliers 2 and 5 for carrier regeneration. Since the oscillation signal is directly supplied from the VCO 22 to the multiplier 2 and the signal whose phase is further shifted by π / 2 by the π / 2 phase shift circuit 23 is supplied to the multiplier 5, multiplication with the output of the BPF 13 is performed. Performed, cos (ωt-φ) and sin (ωt-φ)
After it becomes a signal including components, it is output to the multiplier 6 via the LPFs 15 and 16, respectively. Therefore, the output of the multiplier 6 becomes p ² (t) * ρ ² (t) * d ² (t) sin2φ, which is converted into an error signal voltage of Ksin2φ by the loop filter 24 and VC
It is supplied to O22 and the oscillation frequency is controlled.

The carrier cos (ω) output from the VCO 22
t-φ) is supplied to the frequency dividers 26 and 27 of 1 / N ₁ . As described above, the frequency divider 26 converts the VCO output into a regular clock signal when the spread code synchronization is established. The frequency divider 27 performs a frequency division of 1 / N ₂ .
Since the number of frequency divisions is smaller than that of the frequency divider 26, the frequency of the clock signal output from the frequency divider 27 is higher than that during SS synchronization. The outputs of the frequency dividers 26 and 27 are supplied to the changeover switch Sw, but before the SS synchronization is established, the output of the frequency divider 27 is selected as a clock signal and supplied to the PNG 47.

[0026]

As described above, the demodulator of the present invention is configured to perform carrier regeneration and synchronous detection independently, so that the BPF 13 at the input stage of the carrier regeneration circuit 50 can realize a narrow band, which allows The noise level in the information-modulated wave is reduced, and carrier reproduction can be achieved with almost no influence of jitter due to noise in the input signal. Also,
Since the reproduction carrier is selected from two types of frequency division outputs to obtain the sliding correlation spreading code and the regular despreading spreading code, the synchronization holding circuit typified by the conventional DLL circuit becomes unnecessary, and It can contribute to further stabilization.

Further, if the jitter in the output of the reproduced carrier is small, the jitter of the clock signal supplied to the spread code generator also becomes small, so that a good spread code with little jitter can be generated by PNG. Furthermore, since the despreading circuit section is provided with the spreading noise suppressing circuit including the spreading noise reproducing section 49 and the subtraction circuit 41, even if the level of the interference wave mixed in the SS signal is large, there is a problem of interference. In principle, it contributes to the stability of the operation, the overall circuit configuration is simplified, and it is also advantageous in terms of cost.

[Brief description of the drawings]

FIG. 1 is a block diagram of a synchronous SS modulator that generates a transmission signal.

FIG. 2 is a block configuration diagram of a conventional demodulator for a synchronous SS modulated wave.

FIG. 3 is a specific configuration diagram of a DLL type synchronization maintaining signal processing circuit which is a main part of the conventional device.

FIG. 4 is a characteristic diagram showing a synchronization holding characteristic in a DLL-type synchronization holding signal processing circuit.

FIG. 5 is an explanatory correlation characteristic diagram of a sliding correlation type synchronization acquisition operation.

FIG. 6 is a block diagram showing an embodiment of the demodulation device of the present invention.

FIG. 7 is a specific circuit configuration diagram of a diffused noise reproducing unit in the device of the present invention.

FIG. 8 is a spectrum diagram for explaining diffusion noise suppression (removal) operation in the device of the present invention.

[Explanation of symbols]

1 Demodulator 2-10, 28, 29 Multiplier 11-11, 43, 44 BPF (Band filter) 14-18 LPF (Low-pass filter) 19 Correction filter (LPF) 20 Inverse circuit 21,22 VCO ( Voltage controlled oscillator) 23 π / 2 phase shift circuit 24 Loop filter 25-27 frequency divider 30 HPF (high-pass filter) 31 Frequency characteristic correction circuit 34 Synchronization determination circuit (threshold level detection circuit) 35 Output shaping circuit 36 DLL Type synchronization holding signal processing circuit 38, 39 Absolute value circuit (envelope detection circuit) 40, 41 Subtraction circuit 42 Adder circuit 47, 48 PNG (spreading code generator) 49 Spreading noise reproducing unit 50 Carrier reproducing circuit Sw changeover switch

Claims (2)

(57) [Claims] 1. A demodulator for receiving and demodulating a spread spectrum modulated wave in which a carrier for PSK modulation and a clock signal for spread code used for spread modulation are synchronized, and an input spread spectrum modulated wave is received. the despreading by multiplying the spread code output from the spread code generator reverse
Bifurcation and despreading means for obtaining a spread signal, the despreading signals from the despreading means to one and the other
Then, from the voltage-controlled oscillator to one of the branched despread signals
Of the regenerated carrier and the regenerated carrier of π / 2
The carrier and the carrier are multiplied to obtain the error signals of both
Error-controlled signal of the voltage-controlled oscillator
Carrier reproducing means for obtaining the reproduced carrier, and the despread signal branched from the despreading means to the other.
By multiplying the reproduction carrier from the voltage controlled oscillator
Synchronous detection for synchronous detection to obtain despread demodulation signal
Means and 1 / N _{1 the} regenerated carrier from the voltage controlled oscillator.
First frequency dividing means for generating a clock signal for synchronization holding by frequency division into 1 / N ₁ and the reproduction carrier from the voltage controlled oscillator.
A second frequency dividing means for generating a clock signal of the frequency divider having a small number of 1 / N ₂ frequency-divided to synchronization supplement than included in the despread demodulation signal from said synchronous detection means
That spread and suppression means for suppressing or removing the diffusion noise by the noise component removed is subtracted from the despread demodulation signal, using said output signal suppression means performs synchronization detection for synchronization acquisition by sliding correlation synchronization and detecting means, a synchronous detection signal from said synchronous detection means as a control signal
Said first selectively the second frequency dividing means and the clock signal of the clock signal and the synchronization supplement for synchronization holding for each output
A demodulation device for a synchronous spread spectrum modulated wave, comprising: switching means for switching and outputting to the spread code generator . Wherein said suppression means is one from the synchronous detection means
The despread demodulated signal branched in one direction is removed by the high-pass filter from the frequency component of the information to be demodulated , and then the spread code generator is provided.
Said spreading code from a component inversely <br/> Kazuka the spread code by the inverse circuit sequentially multiplies in multiplier further frequency characteristic
And spreading the noise reproduction unit to output the corrected frequency band part of the information to be demodulated removed by the sex correction circuit, the synchronous detection
From the despread demodulated signal branched from the means to the other.
The output signal of the noise recovery unit is subtracted to obtain the information to be demodulated.
2. A demodulator for a synchronous spread spectrum modulated wave according to claim 1, further comprising a subtraction circuit for extracting a frequency component of the report .