JP3457099B2 - Parallel combination spread spectrum transmission and reception system. - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel combination spread spectrum transmission / reception system, and more particularly to a code synchronization system in the system.

[0002]

2. Description of the Related Art Parallel Combined Spread Spectrum Communication System [Reference] IEICE Technical Report Tanaka, Ota, Marubayashi "ISM Band High Speed S Using Parallel Combined SS Communication System"
S wireless LAN system ”(SST 93-90 to 99)] includes an information spreading sequence for spreading the spectrum and a synchronizing sequence for synchronizing the spreading sequence on the transmitting side and the spreading sequence on the receiving side. In the prior art, as shown in FIG. 4, after the data is serial-parallel converted by the parallel-serial conversion circuit 25a, M parallel output signals are output from the information spreading sequence generation circuit 27 according to the state of the data by the parallel combination mapping circuit 26. Of the information spreading sequences of 1 are selected and linearly added by the adder 29. On the other hand, the synchronization code sequence is output by the synchronization sequence generation circuit 28. The information spreading sequence converted into a multilevel signal by the adder 29 and the synchronization sequence are
The signal is quadrature-modulated by the quadrature modulator 30 and transmitted by the RF transmitter 31 and the antenna 32.

On the receiving side, quadrature demodulation is performed by a quadrature demodulator, but a carrier recovery circuit is required to perform quadrature demodulation.

FIG. 5 shows an example of the receiving side device.
33 is a receiving antenna, 34 is an RF receiver, 35 is a quadrature demodulator for obtaining Q channel output and I channel output, 36, 3
Reference numeral 7 is a waveform shaping circuit for the Q channel and I channel output respectively, 40 is a matched filter, 41 is a clock recovery circuit, 39 is an information spreading sequence generating circuit for generating an information spreading sequence from the output of the clock reproducing circuit 41, and 38 is a matched A multiplication / integration circuit that multiplies / integrates the output of the waveform shaping circuit 36 and the output of the information spreading sequence generation circuit 39 using the output of the filter 40 as a synchronization signal, 42 is an A / D converter, and 43 is A
An absolute value circuit for taking the absolute value of the output of the / D converter 42, 45
Is a polarity determination circuit for determining the polarity of the output of the A / D converter 42,
Reference numeral 44 is a maximum likelihood determination circuit that determines the maximum likelihood of the output of the absolute value circuit 43, and 46 is a parallel combination inverse mapping circuit that obtains a parallel combination inverse mapping from the output of the maximum likelihood determination circuit 44 using the output of the polarity determination circuit 45. , 47 are parallel combination inverse mapping circuits 46.
Is a parallel-serial conversion circuit that extracts demodulated data from the output of the.

[0005]

Generally, for code synchronization, a sliding correlation method for obtaining a synchronization point from a sliding correlation between a reference code word and a received signal, or two reference sequences having a phase difference within 1 chip length are used. Of the correlation power between the received signal and the received signal
DLL (Dela) which feeds back to the oscillator and obtains the chip rate clock and the code synchronization clock from the output of this VCO.
y Locked Loop) method and other techniques are used. However, these have the drawbacks that the circuit scale is large, such as the need for a long series of correlators, and that the synchronization pull-in speed is slow.

An object of the present invention is to provide a parallel combinatory spread spectrum transmission / reception system which solves the circuit complexity and the reduction of the synchronization speed, which occur in the conventional method, and performs a simple and high speed code synchronization operation.

[0007]

In order to achieve this object, a parallel combination spread spectrum transmission / reception system according to the present invention is a parallel combination spread spectrum transmission / reception system including a spread spectrum transmitter and a spread spectrum receiver. In the spread spectrum transmitter, a synchronization sequence for code synchronization having a shorter cycle than the spread code is linearly added to the r information spread sequences mapped by the parallel combination mapping circuit and transmitted, and in the spread spectrum receiver, The linearly added synchronization sequence is subjected to correlation processing and extracted to perform code synchronization. Further, the spread spectrum transmitter according to the present invention includes a serial-parallel conversion circuit for parallelizing serial data to be transmitted, an information spread sequence generation circuit for generating M information spread sequences, and the parallel converted data. A parallel combination mapping circuit for mapping M spreading sequences output from the information spreading sequence generating circuit to r (r <M) sequences according to the above, and a synchronizing sequence generating circuit for generating a synchronizing sequence. An adder for linearly adding the information sequence obtained at the output of the parallel combination mapping circuit and the output of the synchronization sequence generation circuit; and an RF transmission means for transmitting the output of the adder as a spread spectrum wave by a carrier wave And a configuration including and. Further, the spread spectrum receiver according to the present invention receives the spread spectrum wave for receiving the spread spectrum wave by transmitting the output obtained by adding the information series mapped from the M spread series to the r series and the synchronization series by the carrier wave.
An F receiving unit, a carrier wave regenerating circuit, a detector for detecting the output of the RF receiving unit by the output of the carrier wave regenerating unit,
A clock recovery circuit arranged at the output of the detector and a matched filter for sequence synchronization, and information for generating M information diffusion sequences using the output of the clock recovery circuit and the output of the matched filter A spreading sequence generating circuit, a multiplication / integrating circuit for multiplying and integrating a waveform-shaped reception detection output signal and M sequences output from the information spreading sequence generating circuit, and r from the output of the multiplying / integrating circuit. Maximum likelihood determination circuit for determining the number of sequences and the r number (r <
It has a configuration including a parallel combination inverse mapping circuit that inversely maps the sequence of M) to information data, and a parallel-serial conversion circuit that serially converts the inversely mapped data.

[0008]

EXAMPLES Examples of the present invention will be described below. Figure 1
Shows a transmitter of the system of the present invention. The transmission data is converted in parallel by the serial-parallel conversion circuit 1.
The parallel combination mapping circuit 2 selects r sequences from the M sequences generated by the information diffusion sequence generation circuit 3 according to the state of the data converted in parallel. The selected r sequences are linearly added by the adder 5 together with the synchronization sequence output from the synchronization sequence generation circuit 4. what if,
If the information spreading sequence is r = 4, four sets of information spreading sequences, which are binary signals, and a binary synchronizing sequence are added, and a seven-valued signal is obtained as shown in FIG. This signal is modulated by the modulator 7 by the carrier wave from the carrier wave generator 6 and transmitted by the RF transmitter 8 and the antenna 9.

On the receiving side, as shown in FIG. 2, the signal received by the antenna 10 and the RF receiver 11 is quadrature-detected by the detector 12 with the carrier regenerated by the carrier regenerating circuit 13. The received signal is ASK (Amplitude Shif
Since it is a t Keying) signal, it is basically a two-phase signal and a general two-phase PSK (Phase Shift Keying) carrier recovery circuit can be used. After this, the waveform shaping circuit 1
The baseband signal waveform-shaped by 4, 15 is divided into two, one is code-synchronized by the matched filter 18 which receives the output of the clock recovery circuit 17, and the other is information based on the code synchronization. Multiplication / integration is performed by the multiplication / integration circuit 19 with all M sequences output from the spreading sequence generation circuit 16. Since the matched filter 18 only needs to correspond to the length of the synchronizing sequence, the circuit scale can be reduced in the configuration of the present invention in which the synchronizing sequence is set shorter than the spreading code. Thereafter, the maximum likelihood determination circuit 22 determines r sequences, and the parallel combination inverse mapping circuit 24 and the parallel-serial conversion circuit 25 demodulate the transmission data. 20 is an A / D converter, 2
Reference numeral 1 is an absolute value circuit, and 23 is a polarity determination circuit.

[0010]

As described in detail above, according to the present invention, since the synchronizing code sequence is added to the information spreading sequence and transmitted, the transmitter configuration is simple, and the carrier wave recovery is performed in the receiver. In doing so, code synchronization can be performed on the baseband signal after quadrature detection, and the conventional two-phase PSK carrier recovery circuit can be used. Therefore, not only the circuit is simple, but also the synchronization pull-in is performed at high speed. Has the advantage that

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a transmission device of a system of the present invention.

FIG. 2 is a block diagram showing an embodiment of a receiver of the system of the present invention.

FIG. 3 is a diagram for explaining a signal transmitted by the system of the present invention.

FIG. 4 is a block diagram showing an example of a transmission device of a conventional system.

FIG. 5 is a block diagram showing an example of a receiving device of a conventional system.

[Explanation of symbols]

1 Serial-parallel conversion circuit 2 parallel combination mapping circuit 3 Information spreading sequence generation circuit 4 Synchronization sequence generator 5 adder 6 Carrier generator 7 modulator 8 RF transmitter 9 transmitting antenna 10 receiving antenna 11 RF receiver 12 Detector 13 Carrier wave regeneration circuit 14,15 Waveform shaping circuit 16 Information spreading sequence generation circuit 17 Clock recovery circuit 18 Matched Filter 19 Multiplier / integrator circuit 20 A / D converter 21 Absolute value circuit 22 Maximum likelihood determination circuit 23 Polarity judgment circuit 24 Parallel combination inverse mapping circuit 25 Parallel-serial conversion circuit 25a serial-parallel conversion circuit 26 Parallel Combination Mapping Circuit 27 Information spreading sequence generation circuit 28 Synchronous sequence generator 29 adder 30 Quadrature modulator 31 RF transmitter 32 transmitting antenna 33 receiving antenna 34 RF receiver 35 Quadrature demodulator 36,37 Wave shaping circuit 38 Multiplier / Integrator circuit 39 Information spreading sequence generation circuit 40 matched filters 41 Clock recovery circuit 42 A / D converter 43 Absolute value circuit 44 Maximum likelihood determination circuit 45 Polarity judgment circuit 46 Parallel combination inverse mapping circuit 47 Parallel-serial conversion circuit

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Gen Marubayashi 1-104-37 Suzuki-cho, Kodaira-shi, Tokyo (56) References JP-A-8-228168 (JP, A) JP-A-6-204979 (JP , A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 13/00-13/06 H04B 1/69-1/713 H04L 7/00

Claims (3)

(57) [Claims] 1. A parallel combination spread spectrum transmission / reception system comprising a spread spectrum transmitter and a spread spectrum receiver, wherein the spread spectrum transmitter parallelizes a synchronization sequence for code synchronization with a period shorter than a spread code. It is configured such that the r information spreading sequences mapped by the combination mapping circuit are linearly added and transmitted, and that the spread spectrum receiver performs correlation processing and extracts the linearly added synchronization sequence to perform code synchronization. A parallel combination spread spectrum transmission / reception system characterized by the above. 2. A serial-parallel conversion circuit for parallelizing serial data to be transmitted, an information spreading sequence generating circuit for generating M information spreading sequences, and the information spreading according to the parallel converted data. A parallel combination mapping circuit for mapping M spreading sequences output from the sequence generation circuit into r (r <M) sequences, a synchronization sequence generation circuit for generating a synchronization sequence, and the parallel combination map Spread spectrum including an adder that linearly adds the information sequence obtained at the output of the circuit and the output of the synchronization sequence generation circuit, and RF transmitting means for transmitting the output of the adder as a spread spectrum wave by a carrier wave Transmitter. 3. An RF receiving means for receiving a spread spectrum wave for transmitting an output obtained by adding an information sequence mapped from r spread sequences from M spread sequences and a synchronizing sequence by a carrier, and a carrier recovery circuit. A detector for detecting the output of the RF receiving means by the output of the carrier wave regenerating means, a clock regeneration circuit arranged at the output of the detector and a matched filter for sequence synchronization, and an output of the clock regeneration circuit And an output of the matched filter, an information spreading sequence generating circuit for generating M number of information spreading sequences, a reception detection output signal whose waveform has been shaped, and M number of output signals from the information spreading sequence generating circuit. Multiply and multiply sequences /
An integrator circuit, a maximum likelihood determination circuit for determining r sequences from the output of the multiplication / integration circuit, and a parallel combination inverse mapping circuit for inverse mapping from the r (r <M) sequences to information data, A spread spectrum receiver including a parallel-serial conversion circuit that serially converts inversely mapped data.