JP2853728B2 - Digital demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital demodulation circuit used for digital radio communication.

[0002]

2. Description of the Related Art PSK (Phase Shift Key) is a modulation method used in digital wireless communication.
ing) is known. And, as a PSK signal,
For example, there is a 4PSK signal, and a digital demodulation circuit for demodulating the 4PSK signal includes an orthogonal multiplication circuit. This orthogonal multiplication circuit is generally used in a narrow frequency range so as to maintain the orthogonality because it is difficult to maintain the orthogonality over the entire frequency band requiring the orthogonality. That is, π provided in the orthogonal multiplication circuit
Since it is difficult to maintain the phase shift amount of the / 2 phase shift circuit at π / 2 over a wide band, the orthogonal multiplication circuit is used in a narrow frequency range where orthogonality is maintained.

By the way, in order to accurately perform demodulation operation over a wide frequency range, the amount of phase shift of the π / 2 phase shift circuit is corrected, and thereby the orthogonality of the orthogonal multiplication circuit is automatically corrected. A known digital demodulation circuit is known (for example, Japanese Patent Application Laid-Open No. 2-149155).

Here, a conventional digital demodulation circuit will be outlined with reference to FIG.

[0005] The digital demodulation circuit shown in the figure comprises an orthogonal multiplication circuit 10 to which a received modulated signal is applied. As the received modulated signal, for example, there is a QAM signal or a PSK signal. Here, a case where the received modulated signal is a PSK signal (4PSK signal) will be described.

In the orthogonal multiplication circuit 10, the received modulated signal is applied to multiplication circuits 11 and 12. Multiplication circuit 11
Is supplied with a quasi-synchronous carrier signal from the synthesizer 13. The quasi-synchronous carrier signal has a frequency quasi-synchronous to the carrier of the received modulated signal. The multiplier 11 multiplies the received modulated signal by the quasi-synchronous carrier signal, that is,
Performing quasi-synchronous quadrature demodulator sends quasi-coherent demodulated signal ^P, and.

The above-mentioned quasi-synchronous carrier signal is supplied to a π / 2 phase shift circuit 14, where the π / 2 phase is shifted to π
The signal is supplied to the variable phase shift circuit 15 as a / 2 phase shift carrier signal. The phase-shifted carrier signal is phase-controlled in a variable phase shift circuit 15 as described later, and is supplied to a multiplier 12 as a control carrier signal. The multiplier 12 multiplies the received modulated signal by the control carrier signal, that is, performs quasi-synchronous quadrature demodulation ^, and sends out the quasi-synchronous demodulated signal Q 1.

[0008] These quasi-coherent demodulated signals ^P, and ^Q, is given to the A / D converter circuit 18 and 19 via respective low-pass filter circuit 16 and 17. And the quasi-synchronous demodulated signal P
^, And ^Q, are each converted into a digital signal by the A / D converter circuit 18 and 19, applied to carrier recovery demodulation circuit 20.

[0009]

[0010]

The carrier reproduction / demodulation circuit 20 is a complex multiplication circuit 2
1 and a carrier recovery circuit 22. The complex multiplication circuit 21 synchronously demodulates the digital signals supplied from the A / D conversion circuits 18 and 19 according to the reproduced carrier signal from the carrier recovery circuit 22, and performs quadrature demodulation. Output signals P and Q. Then, these quadrature demodulated signals P and Q are supplied to a carrier recovery circuit 22 for carrier recovery and output as demodulated signals. Further, the above-described quadrature demodulated signal P
And Q are provided to a quadrant determination circuit 23, and the quadrature demodulated signal Q is provided to an error detection circuit 24.

When the quadrant determination circuit 23 determines that the received signal vectors (signal points) represented by the quadrature demodulated signals P and Q belong to the first or second quadrant on the phase plane, the load clock is subjected to error detection. To the circuit 24. Specifically, when the signal point belongs to the first quadrant, the quadrant determination circuit 23 sends the first load clock, and when the signal point belongs to the second quadrant, the quadrant determination circuit 23 outputs the first load clock. The determination circuit 23 sends out a second load clock. In other words, the quadrant determination circuit 23 determines the received signal vector in the first quadrant or the second quadrant and generates a load clock corresponding to the signal point on the reference axis in both quadrants.

The error detection circuit 24 includes first and second shift registers (not shown) and a subtraction circuit (not shown). The first and second registers respectively output the quadrature demodulated signal Q. The data is stored according to the first and second load clocks. When the reference axis is the Q axis, the signal value stored in the first and second shift register (amplitude value) but are the same, Q reference axis deviates from the Q ^axis, at the axis,
The signal values stored in the first and second shift registers will be different from each other.

In the subtraction circuit, a difference value between the output values of the first and second shift registers is obtained. At this time, if the reference axis is the Q axis as described above, the difference value becomes zero. On the other hand, the reference axis ^Q, if the axis difference value is not zero. That is, there is a quadrature phase error. That is, the magnitude of the quadrature phase error is represented by the magnitude of the difference value. The difference value is sent from the error detection circuit 24 to the variable phase shift circuit 1.
5 given. The variable phase shift circuit 15 controls the phase of the π / 2 phase shift carrier signal based on the difference value and outputs a control carrier signal.

Here, the operation of the variable phase shift circuit 15 will be further described.

If the phase difference between the control carrier signal and the quasi-synchronous carrier signal is smaller than π / 2, the amplitude value of the quadrature demodulated signal Q when the signal point belongs to the first quadrant belongs to Q1 and the second quadrant. Assuming that the amplitude value of the quadrature demodulated signal Q is Q2, Q1> Q2. As a result, the error detection circuit 24 outputs a positive difference value. On the other hand, if the phase difference between the control carrier signal and the quasi-synchronous carrier signal is larger than π / 2, Q1 <Q2
As a result, the error detection circuit 24 outputs a negative difference value. When the phase difference between the control carrier signal and the quasi-synchronous carrier signal is π / 2, the quadrature error becomes zero and Q1 =
It becomes Q2. As a result, the difference value from the error detection circuit 24 becomes zero. That is, the variable phase shift circuit 15 controls the phase of the π / 2 phase shifted carrier signal so that the difference value output from the error detection circuit 24 becomes zero. That is, if the difference value is positive, the variable phase shift circuit 15 adjusts the phase shift amount so as to increase the phase difference, and if the difference value is negative, the variable phase shift circuit 15
Adjusts the amount of phase shift so as to reduce the phase difference. If the difference value is zero, the variable phase shift circuit 15 maintains the current phase shift amount. In this way, the orthogonal error in the orthogonal multiplier is automatically corrected to zero.

[0017]

In the digital demodulation circuit shown in FIG. 6, the .pi. / 2
It is necessary to correct the phase shift error in the phase shift circuit in an analog manner by a variable phase shift circuit, thereby maintaining the orthogonality of the orthogonal multiplication circuit. Therefore, it is necessary to widen the bandwidth of the variable phase shift circuit, and in addition, it is necessary to accurately adjust the variable phase shift circuit for error correction. Further, since the variable phase shift circuit operates in an analog manner, an analog circuit for converting the output from the error detection circuit into analog must be added to the error detection circuit. From the above points, the conventional digital demodulation circuit has a problem that the cost is high and the downsizing is difficult.

An object of the present invention is to provide a small-sized digital demodulation circuit which can demodulate accurately over a wide band and is low in cost.

[0019]

According to the present invention, an oscillating means for generating a quasi-synchronous carrier signal quasi-synchronous with a carrier frequency, which is used in performing quadrature demodulation, and changing the phase of the quasi-synchronous carrier signal to π Phase shifting means for generating a phase-shifted carrier signal by performing a phase shift of 1/2, and receiving the received signal, the quasi-synchronous carrier signal, and the phase-shifted carrier signal, and performing quasi-synchronous quadrature demodulation on the received signal. Orthogonal multiplying means for generating a signal, carrier demodulation means for synchronously demodulating the quasi-synchronous quadrature demodulated signal based on the reproduced carrier signal and outputting a quadrature demodulated signal, A quadrant determining unit for determining which quadrant the quadrature demodulated signal belongs to and generating a judgment signal; and an error detecting unit for obtaining a quadrature error of the quadrature demodulated signal based on the judgment signal. The demodulation means digital demodulation circuit, characterized in that is provided with means for correcting to match the quadrature error of the phase shifting means depending on the quadrature error of perpendicularity of the regenerated carrier is obtained.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments.

Referring to FIG. 1, in the digital demodulation circuit shown in FIG. 1, the same components as those in the digital demodulation circuit shown in FIG. 6 are denoted by the same reference numerals.

The illustrated digital demodulation circuit has an orthogonal multiplication circuit 25. This orthogonal multiplication circuit 25 does not include a variable phase shift circuit, and the other components are the same as those of the orthogonal multiplication circuit 10 shown in FIG. That is, in the orthogonal multiplication circuit 25, the output (π / 2 phase-shifted carrier signal) from the π / 2 phase shift circuit 14 is directly supplied to the multiplication circuit 12.

Now, the phase shift amount of the π / 2 phase shift circuit 14 is set to π /
When 2-theta, quasi-coherent demodulated signal P after low pass ^filtering, and ^Q, are represented by respective equations 1 and 2.

[0024]

(Equation 1)

[0025]

Q ^, (t) = − p (t) sin (Δωt−θ) + q (t) cos (Δωt−θ) where Δω represents the difference between the angular velocity of the carrier of the received wave and the quasi-synchronous carrier signal. .

[0026] As described above, quasi-coherent demodulated signal P after low pass ^filtering, and ^Q, is converted A / D, is converted into a digital signal string. These digital signal trains are provided to a complex multiplier 21 where, based on the recovered carrier signal,
The operations shown in Equations 3 and 4 are performed and the phase synchronization processing is performed.
It is output as quadrature demodulated signals P and Q. (Note that the carrier recovery circuit shown in FIG. 1 has a different function from the carrier recovery circuit 22 shown in FIG.
6).

[0027]

(Equation 3)

[0028]

(Equation 4) Here, δ represents a phase shift amount corresponding to an address shift amount described later.

Therefore, the quadrature demodulated signals P and Q can be expressed by Expressions 5 and 6 using Expressions 1 to 4.

[0030]

(Equation 5)

[0031]

(Equation 6) The quadrature demodulated signals P and Q shown in Equations 5 and 6 are subjected to phase synchronization processing based on the reproduced carrier signal so that δ becomes equal to θ. As a result, actually, as shown in Equations 7 and 8, Are output in a state where intersymbol interference is removed.

[0032]

(Equation 7)

[0033]

(Equation 8) These quadrature demodulated signals P and Q are given to a quadrant judging circuit 23, and the quadrature demodulated signals P and Q are further
7 given.

Here, referring to FIG.
3 and the error detection circuit 27 will be described. In this example, a case where an error of the quadrature demodulated signal P is detected will be described.

The quadrant judging circuit 23 has polarity judging circuits 23a and 23b, and the quadrature demodulation signal P is supplied to the polarity judging circuit 23a as an input signal. On the other hand, the quadrature demodulation signal Q is supplied to the polarity determination circuit 23b as an input signal. Each and 23b outputs a logic one when its input signal is positive, and outputs a logic zero when its input signal is negative.

If P (t) = 1 and Q (t) =-1 (that is, if there is a signal point in the fourth quadrant), the polarity determination circuit 23a outputs a logical 1 and the polarity determination circuit 23b outputs logic 0. As shown, the polarity determination circuit 23a
Is connected to the AND gates 23c and 23d, and the polarity determination circuit 23b is connected to the AND gate 23c via the inverter 23e and the inverter 23e, so that the output of the AND gate 23d becomes logic 1.

On the other hand, when P (t) = 1 and Q (t) = 1 (that is, when there is a signal point in the first quadrant), both the polarity determination circuits 23a and 23b output logic 1. As a result, the output of the AND gate 23c becomes logic 1.

The error detection circuit 27 includes registers 27a and 2
7b and a subtraction circuit 27c.
If the output of 3c is logic 1, the register 27a stores the amplitude value (digital k bits) of the quadrature demodulated signal P (t). On the other hand, if the output of the AND gate 23d is logic 1, the amplitude value (digital k bits) of the quadrature demodulated signal P (t) is stored in the register 27b. Subtraction circuit 2
7c receives the outputs of the registers 27a and 27b, subtracts these outputs, and outputs an error (ΔP).

The above error (ΔP) is expressed by Equation 9 (where, in Equation 9, p (t) and q (t) have an amplitude of 1).

[0040]

(Equation 9) As is apparent from Equation 9, the error (ΔP) takes a positive or negative value according to the sign of θ−δ except for some short sections,
Generally, the phase of the carrier of the quasi-synchronous demodulated signal is nπ / 2 (n =
1, 3, 5,...), The amplitude takes the maximum value. That is, when Δωt = nπ / 2, Equation 9 is represented by Equation 10.

[0041]

(Equation 10) As can be understood from Expression 10, when Δωt = nπ / 2, the output of the error detection circuit 27 represents a quadrature error, and the quadrature error is estimated to be small in other phases.

Although not shown in the figure, similarly, the case of detecting an error in the quadrature demodulated signal Q can be configured similarly to the example shown in FIG. In this case, the register 27a
And 27b are supplied with the quadrature demodulated signal Q. At this time, the error detection circuit 27 outputs an error (ΔQ) shown in Expression 11.

[0043]

[Equation 11] Next, the quadrant determination circuit 23 and the error detection circuit 27 used in the present invention will be described with reference to FIG.

In FIG. 3, the same components as those shown in FIG. 2 are denoted by the same reference numerals. In FIG. 3, the quadrant determination circuit 23 further includes an AND gate 23f.
Similarly, the error detection circuit 27 further includes registers 27d and 27e, a subtraction circuit 27f, and an addition circuit 27g. In the illustrated error detection circuit 27, the registers 27a and 27
The b error and the subtraction circuit 27c form a P error detection unit 271. The registers 27d and 27e and the subtraction circuit 27f form a Q error detection unit 272.

As described above, P (t) = 1 and Q (t) =
If −1, the output of the AND gate 23d becomes logic 1, and if P (t) = 1 and Q (t) = 1, the output of the AND gate 23c becomes logic 1. Further, P (t) = −
If 1, Q (t) = 1 (that is, if there is a signal point in the second quadrant), the output of the AND gate 23f becomes logic 1.

When the output of the AND gate 23c becomes logic 1, the amplitude values of the quadrature demodulated signals P (t) and Q (t) are stored in the registers 27a and 27d, respectively. When the output of the AND gate 23d becomes logic 1, the amplitude value of the quadrature demodulated signal P (t) is stored in the register 27b. And A
When the output of the ND gate 23f becomes logic 1, the register 2
The amplitude value of the 7e quadrature demodulated signal Q (t) is stored. The subtraction circuit 27c receives the outputs of the registers 27a and 27b,
These outputs are subtracted to output an error (ΔP). Similarly, the subtraction circuit 27f stores the registers 27d and 27e.
, And subtract these outputs to obtain the error (ΔQ)
Is output. These errors ΔP and ΔQ are added to an adder 27
g, where it is added. And the addition circuit 2
From (7g), (ΔP + ΔQ) is output as a difference value, which is supplied to the carrier recovery circuit 26. That is, the difference value represented by Expression 12 is output from the error detection circuit 27 shown in FIG.

[0047]

(Equation 12) As described above, by adding the errors of both P (t) and Q (t), the output (difference value) from the error detection circuit 27 does not change with time, and represents the quadrature error in all phases. become.

Referring to FIG. 4, carrier recovery circuit 26 will be described.

The carrier recovery circuit 26 has a phase error detection circuit 26a. The phase error detection circuit 26a receives the quadrature demodulated signals P and Q, and outputs an address (first address) corresponding to the phase of the reproduction carrier. An address (second address) corresponding to a phase delayed by π / 2 from the phase of the reproduced carrier is generated alternately as an address string. These address strings are provided to the multiplexer 26b and the address shift circuit 26c.

Referring to FIG. 5, the address shift circuit 26c includes a phase address conversion circuit 261. The phase address conversion circuit 261 receives the difference value from the error detection circuit 27 and responds to the difference value. Is converted to a difference (address difference value) of the addresses. The accumulator 262 stores the address shift amount corresponding to the above-mentioned δ. The adder 263 adds the address difference value and the address shift amount, and the addition result is stored in the accumulator 262 again as the address shift amount. Addition circuit 2
At 64, the address shift amount from the accumulator 262 and the address string provided from the phase error detection circuit 26a are added, and the sum is given to the multiplexer 26b as an added address string.

As described above, the updating of δ is performed as follows by using the equations (10) and (12).

Δ (after update) = δ (before update) + output / 2 of error detection circuit 27 The multiplexer 26b selectively outputs the address string and the added address string as the selected address string. That is,
The address string and the added address string are selectively output from the multiplexer 26b at a predetermined timing.

The above-mentioned selection address string is given to the sine / cosine ROM 26d. Sine / cosine ROM2
In 6d, sine waveform data and cosine waveform data exceeding one cycle are individually stored corresponding to addresses. That is, the sine / cosine ROM 26d stores sine waveform data and cosine waveform data for one cycle in association with respective addresses, and also stores waveform data for address shift.

From the sine / cosine ROM 26d, sine waveform data and cosine waveform data are selectively read according to the selected address string. As described above, the address string includes the first and second addresses, and correspondingly, the added address string also includes the first and second shift addresses. As a result, the sine / cosine ROM 26d reads the first to fourth reproduced carrier data, which are latched by the latch circuits 26e to 26h, respectively, and supplied to the complex multiplier 21 as reproduced carrier signals. Then, the complex multiplying circuit 21 performs a phase process based on the reproduced carrier signal,
The quadrature demodulated signals P and Q are output.

[0055]

As described above, according to the present invention, even if an orthogonal error occurs in the output of the orthogonal multiplication circuit, the orthogonal error is automatically corrected by the carrier recovery circuit and the intersymbol interference is removed. Thus, there is an effect that demodulation can be performed with high accuracy over the range.

Further, in the present invention, the quadrature multiplication circuit is not provided with a variable phase circuit, and since the correction is performed digitally, it is not necessary to provide a separate analog circuit, and a π / 2 phase shift circuit is provided. Since it is not necessary to strictly adjust the size, the size can be reduced at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a digital demodulation circuit according to the present invention.

FIG. 2 is a block diagram illustrating an example of a quadrant determination circuit and an error detection circuit illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating another example of the quadrant determination circuit and the error detection circuit illustrated in FIG. 1;

FIG. 4 is a block diagram illustrating an example of a carrier recovery circuit illustrated in FIG. 1;

FIG. 5 is a block diagram illustrating an example of an address shift circuit illustrated in FIG. 4;

FIG. 6 is a block diagram showing a conventional digital demodulation circuit.

[Explanation of symbols]

 10, 25 orthogonal multiplication circuit 11, 12 multiplication circuit 13 synthesizer 14 π / 2 phase shift circuit 15 variable phase shift circuit 16, 17 low-pass filtering circuit 18, 19 A / D conversion circuit 20 carrier wave demodulation circuit 21 complex multiplication circuit 22 , 26 Carrier recovery circuit 23 Quadrant determination circuit 24, 27 Error detection circuit

Claims (5)

(57) [Claims] An oscillator for generating a quasi-synchronous carrier signal quasi-synchronous with a carrier frequency, used for performing quadrature demodulation, and a phase-shifted carrier signal by shifting the phase of the quasi-synchronous carrier signal by π / 2. A quadrature multiplying means for receiving a received signal, the quasi-synchronous carrier signal, and receiving the phase-shifted carrier signal and performing quasi-synchronous quadrature demodulation on the received signal to generate a quasi-synchronous quadrature demodulated signal; A carrier recovery demodulation means for synchronously demodulating the quasi-synchronous quadrature demodulated signal based on the reproduced carrier signal and outputting a quadrature demodulated signal; And a quadrature judging means for judging whether or not the quadrature error of the quadrature demodulated signal is obtained on the basis of the judgment signal. Digital demodulation circuit, wherein a correction to means is provided to match the quadrature error of the phase shifting means in response to said quadrature error. 2. The digital demodulation circuit according to claim 1, further comprising a conversion unit configured to convert the quasi-synchronous quadrature demodulated signal into a digital signal sequence, wherein the quasi-synchronous quadrature demodulated signal is used as the digital signal sequence. A digital demodulation circuit provided to a carrier wave demodulation means. 3. The digital demodulation circuit according to claim 2, wherein said quadrature multiplying means is supplied with said received signal and said quasi-synchronous carrier signal and generates a first signal component of said quasi-synchronous quadrature demodulated signal. A digital demodulation circuit comprising: first multiplying means; and second multiplying means supplied with the received signal and the phase-shifted carrier signal to generate a second signal component of the quasi-synchronous quadrature demodulated signal. . 4. The digital demodulation circuit according to claim 2, wherein said quadrant judging means includes at least a first quadrant and a second quadrant or a first quadrant and a fourth quadrant on a signal phase plane according to the quadrature demodulated signal. A quadrant relating to any one of the quadrants is determined, and a load clock signal is generated as the determination signal corresponding to a signal point projected on an axis in the determined combination quadrant. Digital demodulation circuit. 5. The digital demodulation circuit according to claim 4, wherein said digital signal sequence includes first and second signal components, and wherein said error detecting means includes said first and second signal components. Receiving the signal component corresponding to the axis in the combination quadrant which is at least one of the components and determined by the quadrant determination means and projecting the amplitude value of each signal point projected on the axis to the load clock signal. A digital demodulation circuit for storing a difference between the stored amplitude values and generating the phase error according to the difference value.