JP5213769B2 - Receiving machine - Google Patents

Description

  The present invention relates to a receiver that corrects a frequency deviation of a received signal and performs phase correction.

  In order for a radio receiver such as mobile communication or satellite communication to detect data transmitted by demodulating a received signal, frequency synchronization is required. In particular, when the transmission data sequence is mapped to the phase and frequency component of the transmitted signal, high-accuracy frequency synchronization is required.

  The radio receiver converts the received signal to a baseband frequency through an intermediate frequency by a frequency down converter, or directly converts it to a baseband frequency. The wireless receiver performs AD (Analog to Digital) conversion on the signal converted to the baseband frequency, and detects the converted digital signal by digital signal processing. At this time, if down-conversion is performed at the frequency generated by the local oscillator of the wireless receiver due to fluctuations in the reception frequency due to the propagation environment and frequency deviation between the transmission and reception local oscillators, the digital signal input to the digital signal processing is converted into a digital signal. Contains the frequency deviation. Therefore, in order to correctly detect the received signal, it is necessary to compensate for this frequency deviation.

  As a method for the radio receiver to compensate for the frequency deviation, there is a method using an AFC (Automatic Frequency Control) circuit. In particular, when the transmission data sequence is mapped to the phase and frequency component of the transmission signal, an AFC circuit is necessary because high-accuracy frequency synchronization is required. In recent wireless communications, transmission data is often mapped to phase components in order to increase the transmission rate, such as PSK (Phase Shift Keying) and QAM (Quadrature Amplitude Modulation). Further, when the radio receiver performs synchronous detection, a CR (Carrier Recovery) circuit for reproducing the detection axis is necessary. Therefore, a radio receiver that requires high-accuracy frequency synchronization includes both an AFC circuit and a CR circuit.

  In the AFC circuit, the digital signal after AD conversion is converted into a complex signal, and the phase fluctuation of the converted Fuso signal is detected. Since the detected phase fluctuation amount corresponds to the frequency deviation to be compensated, the detected phase fluctuation amount is changed to the frequency to obtain the frequency deviation, and the obtained frequency deviation is reflected in the intermediate frequency to generate the frequency deviation compensation. I do. On the other hand, in order to detect, it is necessary to determine the detection axis. For example, in the case of QPSK (information data 2 bits mapped to one symbol), the MS axis is determined by setting the I axis as the detection axis, and the LSB is determined by setting the Q axis as the detection axis. Therefore, in the CR circuit, the phase of the received signal after frequency deviation compensation is rotated so as to be in such a state.

  In addition, as a wireless receiver that reduces frequency synchronization errors, for example, in Patent Document 1 below, pseudo-synchronization is suppressed by using only the auxiliary signals of a plurality of consecutive symbols at the beginning of a frame. Technology is disclosed.

JP 2000-31030 A

  However, according to the above conventional technique, in the radio receiver, the AFC circuit and the CR circuit have different functions, but each has a function of changing the phase of the received signal. For this reason, functions having similar functions are duplicated in the same receiver, and there is a problem that the circuit configuration is not efficient.

  Further, although the wireless receiver described in Patent Document 1 discloses a technique for suppressing the occurrence of pseudo-synchronization, there is a problem that it cannot be applied to a configuration that performs processing of an AFC circuit and processing of a CR circuit. .

  The present invention has been made in view of the above, and an object of the present invention is to obtain a receiver capable of reducing the circuit scale when performing AFC processing and CR processing.

In order to solve the above-described problems and achieve the object, the present invention includes a frequency correction process for detecting and correcting the frequency deviation of the received signal, a phase correction process for setting the phase of the received signal to a desired phase, A correction phase calculating means for calculating a correction phase amount for setting the phase of the received signal to the desired phase based on the received signal, and calculating phase information based on the received signal and, previous sample by subtracting the amount of one sample before the correction phase amount from the phase information, and frequency deviation detecting means for detecting the frequency deviation information from the difference between the phase information value and the current sample obtained by this subtraction A sine wave generating means for generating a sine wave for performing quadrature detection based on the frequency deviation information and the correction phase amount; and a quadrature detection using a quadrature detection of the received signal based on the sine wave to form a complex signal. Characterized in that it comprises a means.

  According to the present invention, the phase control means for executing both the CR loop and the AFC loop is provided, and the phase control means compensates for both based on the phase fluctuation corresponding to the frequency deviation fluctuation and the correction phase. Since a sine wave for quadrature detection is generated, the circuit scale can be reduced.

FIG. 1 is a diagram illustrating a functional configuration example of a receiver according to the present invention. FIG. 2A is a diagram illustrating an example of signal points in a state where the frequency deviation can be compensated for by the AFC loop. FIG. 2B is a diagram illustrating the correction phase amount. FIG. 3 is a diagram illustrating an internal configuration example of the NCO unit and the frequency deviation detection unit. FIG. 4 is a diagram illustrating a configuration example of the loop filter unit.

  Embodiments of a receiver according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

Embodiment.
FIG. 1 is a diagram illustrating a functional configuration example of a receiver according to the present invention. The receiver according to the present embodiment includes an AD converter (AD) 1 that AD converts a received signal into a digital signal, a phase control unit 2 that performs frequency deviation and phase compensation, and detects the received signal after compensation processing. It is comprised by the detection part 3 to do. As shown in FIG. 1, the phase control unit 2 according to the present embodiment includes an NCO (Numerical Controlled Oscillator) unit 11, a frequency deviation detection unit 12, a correction phase calculation unit 13, a quadrature detector 14, and an LPF (Low Pass Filter). 15. In the conventional receiver, the AFC function unit and the CR function unit are separately provided, the AFC function unit compensates the frequency deviation, and the CR function unit compensates the phase. The control unit 2 has both an AFC function (AFC loop) and a CR function (CR loop).

  First, general AFC loop and CR loop processing will be described. FIG. 2A is a diagram illustrating an example of signal points in a state where the frequency deviation can be compensated by the AFC loop (locked state). FIG. 2B is a diagram illustrating the correction phase amount. In a state where the frequency deviation cannot be compensated, for example, at the start of reception, the signal point rotates on the IQ plane due to the frequency deviation. On the other hand, in the locked state, the rotation of the signal point stops as shown in FIG. The phase of the stop position is arbitrary. On the other hand, in the CR loop, phase correction is performed to adjust the detection axis to a desired position. For example, in the case of FIG. 2-2, the signal point is moved on the I axis by rotating the signal point of FIG.

  Next, the operation of the present embodiment will be described. First, the AD converter 1 performs AD conversion on the received signal, converts it into a digital signal, and outputs it to the phase control unit 2. In the state where frequency synchronization is not established, first, processing as an AFC function for establishing frequency synchronization. (AFC loop) is started. As an AFC loop, the quadrature detector 14 of the phase control unit 2 performs quadrature detection (IQ separation) on the digital signal using the sine wave signal output from the NCO unit 11. When the AD converter 1 performs IF (intermediate frequency) sampling (when the input digital signal is IF), the NCO unit 11 outputs a sine wave having a frequency corresponding to IF. If the input digital signal is a baseband signal, the frequency corresponding to IF is set to zero. The NCO unit 11 adjusts a sine wave signal for compensating the frequency deviation and phase based on the outputs from the frequency deviation detection unit 12 and the correction phase calculation unit 13 as will be described later. However, at the start of processing, a sine wave signal having a set predetermined frequency is generated.

  The LPF 15 performs processing such as out-of-band noise removal and waveform shaping on the signal after IQ separation, and outputs the processed signal to the frequency deviation detection unit 12. The frequency deviation detection unit 12 detects frequency deviation information that is information for correcting the frequency deviation based on the signal input from the LPF 15, and outputs the detected information to the NCO unit 11. The NCO unit 11 is based on the frequency deviation information. Thus, a sine wave signal for compensating the frequency deviation is generated and output to the quadrature detector 14. The quadrature detector 14 performs quadrature detection of the digital signal input to the phase control unit 2 using the sine wave signal that compensates the frequency output from the NCO unit 11 and outputs the digital signal to the LPF 15. Thereafter, the processing (AFC loop) in order of the quadrature detector 14, the LPF 15, the frequency deviation detection 12, the NCO unit 11, and the quadrature detector 14 is performed until frequency synchronization is established.

  When the frequency synchronization is established, the CR loop including the correction phase calculation unit 13 is also operated, and the two loops are simultaneously operated together with the AFC loop. As processing of the CR loop, the LPF 15 outputs the processed signal to the correction phase calculation unit 13 together with the frequency deviation detection unit 12. Then, the correction phase calculation unit 13 calculates a deviation of the signal point from the I axis for the input signal to obtain phase correction information, and outputs the phase correction information to the NCO unit 11 and the frequency deviation detection unit 12. The NCO unit 11 synthesizes the frequency deviation output from the frequency difference detection unit 12 and the phase correction upper method output from the correction phase calculation unit 13 to generate a sine wave for compensating the phase of the received signal. To do.

  The frequency deviation detection unit 12 subtracts the correction phase based on the phase correction information output from the correction phase calculation unit 13. This process is a process of subtracting the correction phase amount so that the amount of the correction phase amount is not detected as a phase variation (frequency deviation).

  FIG. 3 is a diagram illustrating an internal configuration example of the NCO unit 11 and the frequency deviation detection unit 12 according to the present embodiment. The NCO unit 11 includes an adder 20, a multiplier 21, a buffer (Buf) 22 that is a memory for storing input data for one sample, an adder 23, and a sine wave generation unit 24. Composed. Further, the sine wave generating unit 24 includes a multiplier 32, a buffer (Buf) 33, a cos generating unit (cos (dp)) 34, and a −sin generating unit (−sin (dp)) 35. The frequency deviation detector 12 is a memory for storing a loop filter (LF) 25, a multiplier 26, a phase difference calculator 27, a phase calculator 28, and input data for one sample. Buffers (Buf) 29 and 31 and a multiplier 30 are included. Further, the phase difference calculation unit 27 includes an adder 36.

  As will be described later, the sine wave generation unit 24 of the NCO unit 11 sequentially adds frequency deviations input as phase fluctuations per one sample time by an adder 32 and a buffer 33, and a cos generation unit 34 based on the added value. The -sin generator 35 generates a cosine wave and a -sin wave. The sine wave (cos wave, -sin wave) generation method of the cos generation unit 34 and the -sin generation unit 35 is, for example, a method using a sin, cos table, a method using a CORDIC (COordinate Rotation DIgital Computer) algorithm, or the like. However, any method may be used.

  The phase calculation unit 28 of the frequency deviation detection unit 12 performs a process including an Arctan operation in order to obtain the phase of the input signal (IQ complex signal). As a method for performing the Arctan operation, for example, there are a method using a table and a method using a CORDIC algorithm, but any method may be used. The phase difference calculation unit 27 of the frequency deviation calculation unit 12 calculates the phase difference between two consecutive samples by the adder 36. The loop filter unit 25 of the frequency deviation calculation unit 12 has a function for stably operating a feedback system such as an AFC loop.

  FIG. 4 is a diagram illustrating a configuration example of the loop filter unit 25. In order to track without steady error even when the frequency deviation fluctuates linearly, the loop filter unit 25 is configured as shown in FIG. 4, for example. 4 includes, for example, multipliers 41 and 43, adders 42 and 44, and a buffer (Buf) 45 that is a memory for storing input data. The signal input to the loop filter unit 25 is output to the multipliers 41 and 43, respectively, and the multipliers 41 and 43 multiply the signals by fixed parameters α and β, respectively. Note that α and β, which are fixed parameters, are values set to achieve desired tracking characteristics, respectively. The output of the multiplier 43 is output to the adder 44. The adder 44 adds the signal input from the multiplier 43 and the data stored in the buffer 45, and stores the addition result in the buffer 45. The result is output to the adder 42. The adder 42 adds the output of the multiplier 41 and the output of the adder 44 and outputs the result. In this example, the AFC loop is a secondary loop.

  Next, a processing procedure of the present embodiment will be described. First, AD1 AD-converts the received signal into a digital signal, and the quadrature detector 14 of the phase control unit 2 performs quadrature detection of the digital signal and separates it into an I signal and a Q signal (IQ complex signal). The later signal is output to the LPF 15. The LPF 15 performs processing such as out-of-band noise removal and waveform shaping on the IQ complex signal, and outputs the processed IQ complex signal to the frequency deviation detection unit 12, the correction phase calculation unit 13, and the detection unit 3, respectively. .

In a state where frequency synchronization is not established, the AFC loop first operates as described above. Specifically, the phase calculation unit 28 of the frequency deviation calculation unit 12 calculates the phase of the IQ complex signal, and outputs the calculated phase to the buffer 29 and the phase difference calculation unit 27. The phase difference calculation unit 27 calculates a difference between the phase input from the phase calculation unit 28 and the phase one sample before stored in the buffer 29, and outputs the difference (phase difference) to the multiplier 26. . The multiplier 26 multiplies the phase difference by 1 / (2πT _PLL ) in order to convert the phase difference into a variation in frequency deviation between one sample, and outputs the multiplication result to the loop filter unit 25. T _PLL represents the operation cycle of the AFC loop. The loop filter unit 25 performs a process of stably operating the feedback system on the multiplication result output from the multiplier 26 as described above, and uses the processed value as frequency deviation fluctuation (frequency deviation information) between one sample. Output to the NCO unit 11.

  The NCO unit 11 integrates the input frequency deviation fluctuation between one sample by the adder 23 and the buffer 22 to obtain a frequency deviation. Specifically, the adder 23 adds the frequency deviation fluctuation between one sample output from the frequency deviation detector 1 and the addition result of the previous sample stored in the buffer 22, and the addition result is obtained. The data is output to the buffer 22 and the multiplier 21. The buffer 22 stores the addition result output from the adder 23.

The multiplier 21 multiplies 2πT _S in order to convert the frequency deviation output from the adder 23, which is an integration result, into phase fluctuation, and outputs the multiplication result to the adder 20. T _S represents the sample period. It is to be noted that the multiplier 21 and the multiplier 26 do not need to be mounted separately at the time of mounting, and a value obtained by multiplying 1 / (2πT _PLL ) and 2πT _S by using one multiplier is used for the multiplier 21 and the multiplier 26. You may make it multiply in any position. The adder 20 outputs a phase fluctuation corresponding to the frequency deviation output from the multiplier 21 to the sine wave generation unit 24 when there is no output from the correction phase calculation unit 13. Then, the sine wave generation unit 24 generates a sine wave for quadrature detection so as to compensate for the phase fluctuation based on the phase fluctuation. With the above operation, frequency deviation compensation is performed (frequency synchronization), and when phase deviation compensation is within a predetermined error, phase rotation is stopped (the amount of phase change is within a predetermined error). That is, the AFC loop is locked.

  When the AFC loop is locked, the correction phase calculation unit 13 starts operating, and the CR loop operates. Specifically, first, the correction phase calculation unit 13 obtains the phase of the IQ complex signal output from the LPF 15 and obtains the correction phase amount based on the obtained phase so that the detection axis is at a desired position. The corrected phase amount is output to the NCO unit 11 and the frequency deviation detection unit 12. The adder 20 of the NCO unit 11 adds the correction phase amount output from the correction phase calculation unit 13 and the output from the multiplier 21 and outputs the result to the sine wave generation unit 24.

  The frequency deviation detection unit 12 stores the correction phase amount output from the correction phase calculation unit 13 in the buffer 31, and the adder 30 calculates the correction phase amount stored in the buffer 31 from the phase stored in the buffer 29. Subtraction is performed, and the subtraction result is output to the phase difference calculation unit 27 as the phase one sample before. By this subtraction, the frequency deviation detector 12 can detect only the phase fluctuation of the received signal excluding the phase fluctuation corresponding to the correction phase calculated by the correction phase calculator 13. The subsequent processing is the same as the operation of the AFC loop before the AFC loop is locked.

  After the operation of the CR loop is started, the detection unit 3 starts the detection when it is confirmed that the detection axis can be reproduced with a desired accuracy. The detection unit 3 starts detection after obtaining bit synchronization or frame synchronization according to a wireless system to be applied.

  The correction phase calculation unit 13 determines, for example, a fixed correction phase value Δ, determines whether the Q component of the IQ complex signal is positive or negative, and outputs −Δ as the correction phase when the Q component is positive, When the Q component is negative, + Δ is output. In order to shorten the acquisition time of phase synchronization, for example, when the Q component is positive, the correction phase calculation unit 13 sequentially increments −Δ to −Δ, −2Δ,. When the phase of the Q component changes to a negative value, the increment result is initialized (set to + Δ), and the Q component continues to be a negative value. In such a case, a configuration may be adopted in which a value obtained by sequentially incrementing + Δ is output as a correction phase. The configuration of the correction phase calculation 13 is not limited to this, and any configuration may be used.

  In the present embodiment, the example in which the NCO unit 11, the frequency deviation detection unit 12, and the correction phase calculation unit 13 perform the process on the digital signal after the AD conversion of the reception signal has been described. Each element may be a component corresponding to an analog signal, and the same operation as described above may be performed on the analog signal.

  As described above, the receiver according to the present embodiment includes the phase control unit 2 that performs processing of both the CR loop and the AFC loop. In the phase control unit 2, the frequency deviation variation calculated by the frequency deviation detection unit 12 is provided. The NCO unit 11 generates a sine wave for quadrature detection that compensates for both based on the phase fluctuation corresponding to the correction phase and the correction phase calculated by the correction phase calculation unit 13. Therefore, the circuit scale can be reduced as compared with the conventional receiver that performs both the CR loop processing and the AFC loop processing.

  As described above, the receiver according to the present invention is useful for a receiver that corrects a frequency deviation of a received signal and performs phase correction, and is particularly useful for a receiver in a communication system that maps transmission data to phase components. Is suitable.

1 AD
2 Phase control unit 3 Detection unit 11 NCO unit 12 Frequency deviation detection unit 13 Correction phase calculation unit 14 Quadrature detector 15 LPF
20, 23, 32, 36 Adder 21, 26, 30 Multiplier 22, 29, 33 Buffer (Buf)
24 Sine wave generator 25 Loop filter (LF)
27 phase difference calculation unit 28 phase calculation unit 34 cos (dp)
35 -sin (dp)

Claims (4)

A receiver that performs a frequency correction process for detecting and correcting a frequency deviation of a received signal, and a phase correction process for setting a phase of the received signal to a desired phase,
Correction phase calculation means for calculating a correction phase amount for setting the phase of the reception signal to the desired phase based on the reception signal;
Calculating phase information based on the received signal, one sample before subtracting the amount of one sample before the correction phase amount from the phase information, the frequency deviation from the difference between the phase information value and the current sample obtained by this subtraction A frequency deviation detecting means for detecting information;
Sine wave generating means for generating a sine wave for performing quadrature detection based on the frequency deviation information and the correction phase amount;
A quadrature detection means for quadrature detection of the received signal based on the sine wave to form a complex signal;
A receiver comprising:   The sine wave generating means converts the frequency deviation information into a corresponding phase amount, adds the converted phase amount and the correction phase amount, and generates the sine wave based on the addition result. The receiver according to claim 1.   The receiver according to claim 1, wherein the frequency deviation detecting unit detects the frequency deviation information based on a reception signal after subtracting the correction phase amount.   The receiver according to claim 1, wherein the frequency deviation detection unit and the correction phase calculation unit use the complex signal as a reception signal.

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