JP2022072447A - Digital receiver - Google Patents

Abstract

To provide a digital receiver that can easily establish synchronization even in a pseudo-synchronized state.SOLUTION: A digital receiver 1 includes a demodulation unit 11 that detects a received signal orthogonally and demodulates the signal into an I signal Si and a Q signal Sq, a first decoding unit 12 that decodes data on the basis of the I signal Si and the Q signal Sq demodulated by the demodulation unit 11, a second decoding unit 13 that corrects a reproduction carrier frequency corresponding to pseudo-synchronization to the I signal Si and the Q signal Sq demodulated by the demodulation unit 11 and decodes the data, and a synchronization detection unit 14 that detects a unique word representing a synchronization word from either first data D1 input from the first decoding unit 12 or second data D2 input from the second decoding unit 13.SELECTED DRAWING: Figure 3

Description

The present invention relates to a digital receiver used in a wireless communication system.

The receiver in the wireless communication system is equipped with an automatic frequency control (AFC) function that corrects a deviation (frequency error) between the frequency of the transmitted wave transmitted by the transmitter and the received frequency. In the case of a digital modulation / demodulation receiver, AFC can be realized by digital signal processing. As a method of realizing AFC by digital signal processing, a received symbol for a symbol position detected from a received signal (hereinafter referred to as "received symbol position") and a symbol position originally to be detected (hereinafter referred to as "regular symbol position"). A method of obtaining and correcting a frequency error from a positional deviation is known.

As a digital modulation / demodulation method, the normal symbol points in the four-phase phase shift keying method exist in each of the four quadrants (phase angles of the normal symbol points are 45 degrees, 135 degrees, 225 degrees, and 315 degrees). In AFC using 4-phase phase shift keying, if the phase error between the normal symbol position and the received symbol position is larger than 45 degrees, it is judged that the received symbol exists in a different quadrant from the original quadrant, and the frequency error. Is corrected, and as a result, it may be in a pseudo-synchronized state where it is locked at the wrong frequency. Patent Document 1 discloses a technique for detecting this pseudo-synchronization.

Japanese Unexamined Patent Publication No. 2008-61173

However, in the conventional technique, there is a problem that it is difficult to establish synchronization because the demodulated data is distorted in the state of pseudo-synchronization.

An object of the present invention is to provide a digital receiving device capable of easily establishing synchronization even in a pseudo-synchronized state.

In order to achieve the above object, the digital receiving device according to one aspect of the present invention has a demodulation unit that performs orthogonal detection of the received signal and demodulates it into an I signal and a Q signal, and the I signal demodulated by the demodulation unit and the said. A first decoding unit that decodes data based on the Q signal, and a second that corrects the reproduction carrier frequency corresponding to pseudo synchronization with respect to the I signal and the Q signal demodulated by the demodulation unit to decode the data. 2. It is characterized by including a decoding unit and a synchronization detection unit that detects a unique word representing a synchronization word from any one of the data input from the first decoding unit and the data input from the second decoding unit. And.

According to one aspect of the present invention, synchronization can be easily established even in a pseudo-synchronized state.

It is a figure explaining the digital receiving apparatus by one Embodiment of this invention, and is the figure which shows the constellation of QPSK when the phase error between the received symbol position and the normal symbol position is 45 degrees or less. It is a figure explaining the digital receiving apparatus by one Embodiment of this invention, and is the figure which shows the constellation of QPSK when the phase error between the received symbol position and the normal symbol position is larger than 45 degrees. It is a block diagram which shows the schematic structure of the digital receiving apparatus by one Embodiment of this invention. It is a figure explaining the effect of the digital receiving apparatus by one Embodiment of this invention, and is the figure which shows typically the frequency band of the data of the decoding process, and the frequency band of the low-pass filter provided in the decoding part.

One embodiment of the present invention exemplifies an apparatus or method for embodying the technical idea of the present invention, and the technical idea of the present invention includes materials, shapes, structures, arrangements, etc. of components. Is not specified as the following. The technical idea of the present invention may be modified in various ways within the technical scope specified by the claims described in the claims.

Before explaining the schematic configuration of the digital receiver 1 according to the present embodiment, the figure shows the correction of the frequency error performed by the digital receiver 1 by taking Quadrature Phase-Shift Keying (QPSK) as an example. It will be described with reference to 1 and FIG. FIG. 1 is a diagram showing a QPSK constellation when the phase error between the received symbol position and the normal symbol position is 45 degrees or less. Here, the constellation is expressed by plotting the symbol data on a two-dimensional complex plane with the in-phase component I (In-phase) as the horizontal axis and the orthogonal component Q (Quadrature) as the vertical axis for each symbol. Is. FIG. 2 is a diagram showing a QPSK constellation when the phase error between the received symbol position and the normal symbol position is larger than 45 degrees.

As shown in FIG. 1, the phase error between the received symbol position B and the normal symbol position A is Δθ in the first symbol (see FIG. 1 (a)) and 2 × Δθ in the second symbol (FIG. 1). (B)) It is assumed that the third symbol is 3 × Δθ (see FIG. 1 (c)). In this case, the phase error increases by Δθ for each symbol time. Therefore, assuming that one symbol time is Ts, the frequency error Δf can be obtained by the following equation (1).
Δf = Δθ / (2π × Ts) ・ ・ ・ (1)

The digital receiving device 1 according to the present embodiment digitally controls the oscillation frequency of the reference oscillator (not shown) which is the basis of the local signal (details will be described later) based on the frequency error Δf obtained by the equation (1). It is possible to correct the frequency error between the frequency of the carrier signal and the frequency of the local signal of the signal transmitted from the transmission device (not shown). Hereinafter, the frequency of the carrier signal may be referred to as "carrier frequency".

However, in the case of this method, for example, as shown in FIG. 2, when the phase error Δθ exceeds 45 degrees, it is erroneously assumed that the received symbol position B exists in a quadrant different from the original correct normal symbol position A. Is judged. As shown in FIG. 2A, when the received symbol position B exists in the quadrant of the normal symbol position C because the phase error Δθ exceeds 45 degrees, the normal symbol position of the received symbol position B is originally Is erroneously determined to be the normal symbol position C even though it is the normal symbol position A. As a result, as shown in FIG. 2A, the phase error of the received symbol position B with respect to the normal symbol position is determined to be Δφ instead of Δθ. Further, as shown in FIG. 2B, when the phase error of the received symbol position B with respect to the original normal symbol position A is 2 × Δθ (> 45 degrees), the phase error of the received symbol position B is 2 × Δφ. It is determined that (≦ 45 degrees). Further, as shown in FIG. 2C, when the phase error of the received symbol position B with respect to the original normal symbol position A is 3 × Δθ (> 45 degrees), the phase error of the received symbol position B is 3 × Δφ. It is determined that (≦ 45 degrees).

If the digital receiver makes an erroneous frequency correction based on an erroneous phase error that is different from the actual phase error as illustrated in FIGS. 2 (a) to 2 (c), then one symbol time. The symbol is detected at the wrong position, which is shifted by 90 degrees or -90 degrees each time. The decoding unit provided in the digital receiver maintains a state in which the oscillation frequency of the reference oscillator is corrected based on the symbol detected at this incorrect position (hereinafter, may be referred to as “pseudo-synchronous state”). It will be. The reproduction carrier frequency (frequency of the local signal) in the pseudo-synchronous state is called "pseudo-synchronous frequency". The frequency of the reproduction carrier generated by correcting the oscillation frequency of the reference oscillator based on the normal symbol position with respect to the "pseudo-synchronous frequency" is called "normal frequency".

In the pseudo-synchronous state, the received symbol position is detected at a position shifted by 90 degrees or −90 degrees for each symbol time with respect to the normal symbol position. Therefore, the decoding unit provided in the digital receiver locks to a pseudo-synchronous frequency whose frequency is deviated by 1/4 of the symbol frequency with respect to the carrier frequency. For example, when the symbol frequency is 4.8 kHz, the pseudo-synchronous frequency is a frequency deviated by ± 1.2 kHz (= ± 4.8 kHz / 4) from the carrier frequency. Further, the received symbol position deviates from the originally detected symbol position by 90 degrees (0 degrees, 90 degrees, 180 degrees, 270 degrees (−90 degrees)). Therefore, the decoding unit provided in the digital receiving device cannot correctly decode the signal transmitted from the digital transmitting device on the transmitting side in the pseudo-synchronous state. The decoding process in the present embodiment is a conversion process from the mapping position on the constellation of the demodulated symbol to the bit series of "0" and "1".

As described above, the digital receiving device 1 according to the present embodiment may be in a pseudo-synchronous state when the received signal transmitted from the transmitting side and received is demodulated and decoded. Therefore, the digital receiving device 1 includes a first decoding unit 12 and a second decoding unit 13 (see FIG. 3, details of which will be described later). A state in which one of the first decoding unit 12 and the second decoding unit 13 detects a received symbol position based on a normal phase error for the same received signal (hereinafter, may be referred to as a "normal synchronization state"). If it is, the other is set to be in a pseudo-synchronous state and to be in a different state from each other. Further, the first decoding unit 12 is set to decode data to be output to a subsequent device connected to the digital receiving device 1. The digital receiving device 1 detects which of the first decoding unit 12 and the second decoding unit 13 is in the normal synchronization state, and when the first decoding unit 12 is in the normal synchronization state, the first decoding unit 12 is used as it is. The decoded data from the decoding unit 12 is output to a subsequent device, and when the second decoding unit 13 is in the normal synchronization state, the first decoding unit 12 is adjusted so as to be in the normal synchronization state. As a result, the digital receiving device 1 can output the data decoded in the normal synchronization state to the subsequent device.

<Configuration of digital receiver>
The schematic configuration of the digital receiver according to this embodiment will be described with reference to FIG. FIG. 3 is a block diagram for explaining a schematic configuration of the digital receiver 1 according to the present embodiment.

As shown in FIG. 3, the digital receiving device 1 includes a demodulation unit 11 that orthogonally detects a received signal and demodulates it into an I signal Si and a Q signal Sq. The received signal is orthogonally detected by, for example, a local signal having a phase difference of 90 degrees. Further, the digital receiving device 1 includes a first decoding unit 12 that decodes data based on the I signal Si and the Q signal Sq demodulated by the demodulation unit 11. Further, the digital receiving device 1 includes a second decoding unit 13 that corrects the reproduction carrier frequency corresponding to pseudo synchronization with respect to the I signal Si and the Q signal Sq demodulated by the demodulation unit 11 and decodes the data. There is. Further, the digital receiving device 1 includes a synchronization detection unit 14 that detects a unique word representing a synchronization word from either the data input from the first decoding unit 12 or the data input from the second decoding unit 13. ing. Further, when the digital receiving device 1 does not detect an error in the data input from the first decoding unit 12, the digital receiving device 1 outputs the data as a decoding signal in the subsequent stage, and makes an error in the data input from the first decoding unit 12. An error correction / decoding processing unit 15 that discards the data as invalid data when it is detected is provided.

The digital receiving device 1 divides the I data Di based on the I signal Si and the Q data Dq based on the Q signal Sq output from the demodulation unit 11 into two paths of the first decoding unit 12 and the second decoding unit 13. It has a configuration to decrypt. That is, the digital receiving device 1 has a first receiving pass P1 which is a first decoding unit 12 and a second receiving pass P2 which is a second decoding unit 13. In the digital receiving device 1, the first receiving path P1 is the main path (main path). The decrypted data of the first reception path P1 is output to the error correction decoding processing unit 15 in the subsequent stage.

(Structure of demodulation unit)
As shown in FIG. 3, the demodulation unit 11 has an antenna 111 that receives a radio signal transmitted from a transmission side (for example, a digital transmission device (not shown)). Further, the demodulation unit 11 has a local oscillator 112 that oscillates a local signal having the same frequency as the carrier signal frequency (carrier frequency) of the radio signal. The local oscillator 112 includes a reference oscillator (not shown) that generates a reference signal for generating a local signal. The frequency of the local signal can be changed by controlling the oscillation frequency of this reference oscillator. Further, the demodulation unit 11 has a 90-degree phase shifter 113 that shifts the phase of the local signal oscillated by the local oscillator 112 by 90 degrees (π / 2).

The demodulation unit 11 has a mixer 114 to which a received signal, which is a radio signal received by the antenna 111, and a local signal oscillated by the local oscillator 112 are input. The mixer 114 multiplies the received signal received by the antenna 111 by the local signal, and extracts the I signal Si. Further, the demodulation unit 11 inputs a received signal which is a radio signal received by the antenna 111 and a local signal whose phase is shifted by 90 degrees with respect to the basic local signal by the 90 degree phase shifter 113. have. The mixer 115 is a component that extracts the Q signal Sq by multiplying the received signal received by the antenna 111 by a signal whose phase is shifted by 90 degrees with respect to the local signal.

The received signal is converted into the baseband I signal Si and Q signal Sq by the mixers 114 and 115. The local oscillator 112 is configured to oscillate a local signal having the same frequency as the carrier signal of the radio signal transmitted from the transmitting side. However, matching the frequency of the carrier signal with the frequency of the local signal is extremely difficult and usually different. Therefore, the frequencies of the I signal Si and the Q signal Sq are shifted by the difference (error) between the frequency of the carrier signal and the frequency of the local signal, respectively.

The demodulation unit 11 has an A / D converter 116 that generates I data Di by analog-digital (hereinafter abbreviated as “A / D”) conversion of the I signal Si output from the mixer 114. .. Further, the demodulation unit 11 has an A / D converter 117 that A / D-converts the Q signal Sq output from the mixer 115 to generate Q data Dq. The A / D converter 116 outputs the digital I data Di to the first decoding unit 12 and the second decoding unit 13. The A / D converter 117 outputs the digital Q data Dq to the first decoding unit 12 and the second decoding unit 13.

(Structure of the first decoding unit)
As shown in FIG. 3, the first decoding unit 12 has a phase rotation unit 121 in which I data Di and Q data Dq are input from the demodulation unit 11. The phase rotation unit 121 rotates the phases of the I data Di and the Q data Dq by the phase rotation amount input from the rotation amount calculation unit 129 (details will be described later).

The first decoding unit 12 has a low-pass filter (LPF) 122 to which the I data Di, whose phase is rotated and output by the phase rotation unit 121, is input. The first decoding unit 12 has a low-pass filter (LPF) 123 to which the Q data Dq output by rotating the phase by the phase rotation unit 121 is input. The low-pass filters 122 and 123 are designed to obtain Nyquist characteristics throughout the system together with a band limiting filter inserted before up-converting the digitally modulated signal to the transmission frequency band on the transmitting side. Therefore, the low-pass filters 122 and 123 are composed of, for example, a root Nyquist filter.

The first decoding unit 12 has a symbol clock reproduction unit 124 in which the I data Di output by the low-pass filter 122 and the Q data Dq output by the low-pass filter 123 are input. The symbol clock reproduction unit 124 reproduces a symbol clock signal indicating the switching timing (that is, the timing of the zero cross point) of the codes of the I data Di and the Q data Dq, which are the baseband signals.

The first decoding unit 12 has a symbol point extraction unit 125 that extracts the received symbol point Xk1 based on the I data Di input from the low-pass filter 122 and the symbol clock signal input from the symbol clock reproduction unit 124. There is. Further, the first decoding unit 12 has a symbol point extraction unit 126 that extracts the received symbol point Yk1 based on the Q data Dq input from the low pass filter 123 and the symbol clock signal input from the symbol clock reproduction unit 124. are doing. As a result, the first decoding unit 12 can acquire the reception symbol position B shown in FIG. 1, for example. In this example, the reception symbol point at the reception symbol position B can be represented as "Xk1, Yk1".

It has a decoding determination unit 127 for decoding and determining a received symbol based on the reception symbol point Xk1 input from the first decoding unit 12 and the symbol point extraction unit 125 and the reception symbol point Yk1 input from the symbol point extraction unit 126. are doing. The decoding determination unit 127 decodes the bit sequence from the normal symbol position set in the quadrant where the reception symbol points (Xk1, Yk1) exist. The first decoding unit 12 outputs the bit sequence decoded by the decoding determination unit 127 as the first data D1 to the synchronization detection unit 14 and the error correction decoding processing unit 15.

The first decoding unit 12 has a frequency correction amount calculation unit 128 that calculates a frequency correction amount based on a frequency error between the frequency of the local signal and the carrier frequency of the received signal. The frequency correction amount calculation unit 128 obtains the phase that should be originally detected from the quadrant of the detected symbol point, and obtains the frequency error from the amount of change in the phase shift corresponding to the received symbol point with respect to the obtained phase. ..

In the present embodiment, the frequency correction amount calculation unit 128 is a local signal based on the reception symbol position obtained from the reception symbol points (Xk1, Yk1) taken out by the symbol point extraction units 125 and 126 and the normal symbol position. Detects the frequency error between the frequency of and the carrier frequency of the received signal. The frequency error is the phase corresponding to the normal symbol position set in the quadrant in which the received symbol point (Xk1, Yk1) exists and the phase corresponding to the received symbol position obtained from the received symbol point (Xk1, Yk1). It is detected based on the amount of change in the difference (phase shift) per unit time.

Although the details will be described later, when the synchronization information Im input from the synchronization detection unit 14 is the information synchronously detected by the first decoding unit 12, the frequency correction amount calculation unit 128 uses the detected frequency error as the frequency correction amount. It is output to the rotation amount calculation unit 129 and the pseudo-synchronization rotation amount calculation unit 139. On the other hand, when the synchronization information Im input from the synchronization detection unit 14 is the information synchronously detected by the second decoding unit 13, the frequency correction amount calculation unit 128 has a phase rotation amount of the pseudo-synchronization frequency (90 in this embodiment). The rotation amount of the degree) is output to the rotation amount calculation unit 129 and the pseudo-synchronization rotation amount calculation unit 139 as the frequency correction amount by adding or subtracting the value obtained by adding or subtracting the detected frequency error. The synchronization information Im output from the synchronization detection unit 14 is information on the decoding unit of the first decoding unit 12 and the second decoding unit 13 that have been synchronously detected by the synchronization detection unit 14. Therefore, the frequency correction amount calculation unit 128 calculates the frequency correction amount by adding the detection result of the synchronization detection unit 14 to the detected frequency error. The synchronization detection unit 14 does not output the synchronization information Im until the synchronization is detected. Further, when the synchronization information Im from the synchronization detection unit 14 is not input, the frequency correction amount calculation unit 128 calculates the frequency correction amount on the assumption that the synchronization detection is performed by the first decoding unit 12. As described above, in the present embodiment, the frequency correction amount calculation unit 128 calculates the frequency correction amount, and the rotation amount calculation unit 129 and the pseudo-synchronization rotation amount calculation unit 139 use the correction amount to perform phase rotation. This is a baseband process equivalent to controlling the frequency of the reference oscillator described above, and which part of the digital receiving device 1 performs such a baseband process is not limited to the present embodiment. Further, any process equivalent to the process of controlling the oscillation frequency of the local oscillator is included in the present invention.

Here, assuming that the frequency error calculated by the frequency correction amount calculation unit 128 during the i-th data decoding (i is a natural number of 2 or more) is _Δfi and the phase rotation amount of the pseudo-synchronous frequency is α, the i-th time. The frequency correction amount fC _i calculated by the frequency correction amount calculation unit 128 at the time of data decoding can be expressed by the following equation (2).
fC _i = Δf _i + α ・ ・ ・ (2)

When the synchronization information Im indicating that the first decoding unit 12 has detected synchronization is input from the synchronization detection unit 14, the frequency correction amount calculation unit 128 calculates the frequency correction amount fc _i with α as zero. Further, when the frequency correction amount calculation unit 128 receives the synchronization information Im indicating that the second decoding unit 13 has synchronously detected the synchronization information Im from the synchronization detection unit 14, and the calculated frequency error _Δfi is a positive value, the frequency correction amount calculation unit 128 has a positive value. , Α is set as a negative value and is added to the frequency error Δf _i (that is, α is subtracted from the frequency error Δf _i ). Further, in the frequency correction amount calculation unit 128, when the synchronization information Im indicating that the second decoding unit 13 has synchronously detected is input from the synchronization detection unit 14, and the calculated frequency error _Δfi is a negative value, the frequency correction amount calculation unit 128 has a negative value. , Α are positive values and are added to the frequency error _Δfi . At the time of the first data decoding, the frequency correction amount fC _i is set to zero.

The first decoding unit 12 calculates the phase rotation amount used for extracting the next reception symbol point (Xk1, Yk1) based on the frequency correction amount and the elapsed time input from the frequency correction amount calculation unit 128. It has a rotation amount calculation unit 129. The rotation amount calculation unit 129 outputs the calculated phase rotation amount to the phase rotation unit 121.

The phase rotation unit 121 adjusts the phase of the I data Di and the Q data Dq input from the A / D converters 116 and 117 provided in the demodulation unit 11 by the phase rotation amount input from the rotation amount calculation unit 129. .. Further, the first decoding unit 12 decodes the I data Di and the Q data Dq transmitted from the demodulation unit 11 while accumulating the phase rotation amount calculated by the rotation amount calculation unit 129 in the I data Di and the Q data Dq. Repeat to adjust the frequency error. Assuming that the phase rotation amount set in the phase rotation unit 121 at the time of the first data decoding is b11 and the _one symbol time (that is, the time interval for extracting the received symbol points) is Ts, the i-th time (that is, the second and subsequent times). The phase rotation amount b1 _i calculated at the time of data decoding can be expressed by the following equation (3). The reciprocal of 1 symbol time Ts is the sampling frequency for sampling the signal transmitted from the transmitting side (that is, the received signal).
b1 _i = b1 ₁ + 2π × ΣfC _i-1 × Ts ・ ・ ・ (3)

As described above, the first decoding unit 12 has the phase rotation amount set at the time of the first data decoding at the time of extracting the received symbol point at the i-th time (that is, at the time of data decoding) and the i- from the second time. The phase rotation amount calculated by the rotation amount calculation unit 129 can be reflected in the data decoding up to the first time. As a result, the digital receiving device 1 can improve the accuracy of decoding the data transmitted from the transmitting side.

(Structure of the second decoding unit)
As shown in FIG. 3, the second decoding unit 13 has substantially the same configuration as the phase rotation unit 121 provided in the first decoding unit 12 to the decoding determination unit 127. That is, except that the phase rotation unit 131 provided in the second decoding unit 13 adjusts the phases of the I data Di and the Q data Dq using the pseudo-synchronization rotation amount (details will be described later) instead of the phase rotation amount. Therefore, it has the same configuration as the phase rotation unit 121 provided in the first decoding unit 12, and exhibits the same function.

The low-pass filter 132 provided in the second decoding unit 13 has the same configuration as the low-pass filter 122 provided in the first decoding unit 12, and exhibits the same function. The low-pass filter 133 provided in the second decoding unit 13 has the same configuration as the low-pass filter 123 provided in the first decoding unit 12, and exhibits the same function. The symbol clock reproduction unit 134 provided in the second decoding unit 13 has the same configuration as the symbol clock reproduction unit 124 provided in the first decoding unit 12, and exhibits the same function.

The symbol point extraction unit 135 provided in the second decoding unit 13 is the same as the symbol point extraction unit 125 provided in the first decoding unit 12, except that the received symbol points are not output to the frequency correction amount calculation unit 128. It has the same structure and exhibits the same function. The symbol point extraction unit 136 provided in the second decoding unit 13 has the symbol point extraction unit 126 provided in the first decoding unit 12 except that the reception symbol point Yk2 is not output to the frequency correction amount calculation unit 128. It has a similar configuration and exhibits similar functions. The decoding determination unit 137 provided in the second decoding unit 13 does not output the decoded bit sequence as the second data D2 to the error correction decoding processing unit 15, but the decoding determination unit 12 is provided in the first decoding unit 12. It has the same configuration as the unit 127 and exhibits the same function.

As shown in FIG. 3, the second decoding unit 13 has a pseudo-synchronization rotation amount calculation unit 139 that calculates the phase rotation amount of the pseudo-synchronization frequency, which is the carrier frequency in the pseudo-synchronization state, based on the frequency correction amount. ing. Here, the "phase rotation amount of the pseudo-synchronous frequency, which is the carrier frequency in the pseudo-synchronous state" may be referred to as "pseudo-synchronous phase rotation amount". The frequency correction amount calculated by the frequency correction amount calculation unit 128 provided in the first decoding unit 12 is input to the pseudo-synchronization rotation amount calculation unit 139. The pseudo-synchronization rotation amount calculation unit 139 calculates different pseudo-synchronization phase rotation amounts according to the positive / negative of the frequency correction amount input from the frequency correction amount calculation unit 128. When the frequency correction amount input from the frequency correction amount calculation unit 128 is, for example, a positive value, the pseudo-synchronization rotation amount calculation unit 139 sets a value corresponding to "-1 / (4 × Ts) Hz". The pseudo-synchronous phase rotation amount is calculated by adding it to the frequency correction amount. Further, when the frequency correction amount input from the frequency correction amount calculation unit 128 is, for example, a negative value, the rotation amount calculation unit 139 for pseudo synchronization sets a value corresponding to "+ 1 / (4 × Ts) Hz". The pseudo-synchronous phase rotation amount is calculated by adding it to the frequency correction amount.

The phase rotation unit 131 uses only the phase rotation amount input from the pseudo-synchronization rotation amount calculation unit 139 for the I data Di and Q data Dq input from the A / D converters 116 and 117 provided in the demodulation unit 11. Adjust the phase. Further, the second decoding unit 13 accumulates the pseudo-synchronous phase rotation amount calculated by the pseudo-synchronization rotation amount calculation unit 139 in the I data Di and the Q data Dq, and the I data Di and the I data Di input from the demodulation unit 11. Decoding of Q data Dq is repeated to adjust the frequency error for pseudo synchronization. Assuming that the pseudo-synchronous phase rotation amount set in the phase rotation unit 131 at the time of the first data decoding is b2 ₁ and the value corresponding to "1 / (4 × Ts) Hz" is β, the i-th time (that is, 2) The pseudo-synchronous phase rotation amount _b2i calculated at the time of data decoding (from the second time onward) can be expressed by the following equations (4) and (5).
b2 _i = b2 ₁ + (2π × ΣfC _i-1 × Ts) −α ・ ・ ・ (4)
b2 _i = b2 ₁ + (2π × ΣfC _i-1 × Ts) + α ・ ・ ・ (5)

Equation (4) is an equation for calculating a pseudo-synchronous phase rotation amount b2 _i when the frequency correction amount is, for example, a positive value. Equation (5) is an equation for calculating a pseudo-synchronous phase rotation amount b2 _i when the frequency correction amount is, for example, a negative value.

Therefore, the phase of the pseudo-synchronous phase rotation amount b2 _i calculated by the pseudo-synchronization rotation amount calculation unit 139 is 90 degrees or −90 degrees with respect to the phase rotation amount b1 _i calculated by the rotation amount calculation unit 129. Therefore, the I data Di that is phase-adjusted and output by the phase rotation unit 131 is data whose phase is shifted by 90 degrees with respect to the I data Di that is phase-adjusted and output by the phase rotation unit 121. Similarly, the Q data Dq that is phase-adjusted and output by the phase rotation unit 131 is data whose phase is shifted by 90 degrees with respect to the Q data Dq that is phase-adjusted and output by the phase rotation unit 121.

Similarly, the symbol clock signal reproduced by the symbol clock reproduction unit 134 is a signal whose phase is 90 degrees out of phase with the symbol clock signal reproduced by the symbol clock reproduction unit 124.

Similarly, the received symbol point Xk2 taken out by the symbol point taking out unit 135 has a value whose phase is 90 degrees out of phase with the received symbol point Xk1 taken out by the symbol point taking out unit 125. Similarly, the received symbol point Yk2 taken out by the symbol point taking out unit 136 has a value whose phase is 90 degrees out of phase with respect to the received symbol point Yk1 taken out by the symbol point taking out unit 126. Therefore, in the QPSK constellation shown in FIGS. 1 and 2, the received symbol position based on the received symbol point (Xk1, Yk1) and the received symbol position based on the received symbol point (Xk2, Yk2) are π / 2 ( It has a phase difference of 90 degrees).

The decoding determination unit 137 decodes the bit sequence from the normal symbol position set in the quadrant in which the reception symbol points (Xk1, Yk1) exist. The decoding determination unit 137 outputs the decoded bit sequence as the second data D2 to the synchronization detection unit 14. As described above, the received symbol points (Xk1, Yk1) are 90 degrees out of phase with respect to the received symbol points (Xk2, Yk2). Therefore, the second data D2 output from the decoding determination unit 137 is data whose phase is shifted by 90 degrees with respect to the first data D1 output from the decoding determination unit 127.

Further, the pseudo-synchronous phase rotation amount b2 ₁ is set to a value whose phase is shifted by 90 degrees with respect to the phase rotation amount b1 ₁ . Therefore, the digital receiving device 1 uses data whose phases are 90 degrees out of phase with each other in the first receiving pass P1 which is the first decoding unit 12 and the second receiving pass P2 which is the second decoding unit 13 for the first time. Data decryption can be performed.

(Configuration of sync detector)
The digital receiver 1 is adapted to adjust the frequency error between the frequency of the local signal oscillated by the local oscillator 112 and the carrier frequency of the received signal by using the unique word included in the signal transmitted from the transmitting side. .. Further, the digital receiving device 1 adjusts the frequency error by using the unique word transmitted a plurality of times in succession.

The synchronization detection unit 14 has the first data D1 decoded by the first decoding unit 12 based on the I signal Si and the Q signal Sq demodulated by the demodulation unit 11 for the specific signal which is the reception signal including the unique word, and the first data D1. The unique word included in any of the second data decoded by the second decoding unit 13 based on the I signal Si and the Q signal Sq demodulated by the demodulation unit 11 is detected, and the first decoding unit It is configured to detect that either 12 or the second decoding unit 13 is synchronized.

In the digital transmission / reception system including the digital reception device 1, the digital reception device 1 stores the same unique word as the unique word transmitted from the transmission side in the synchronization detection unit 14. Therefore, the synchronous detection unit 14 compares the decoded data decoded by the first decoding unit 12 and the second decoding unit 13 with the stored unique word, and correlates with the unique word, that is, the degree of matching. It can be detected that it has been synchronized with. The unique word has, for example, a structure in which a predetermined character string is represented by a plurality of bits.

The synchronization detection unit 14 compares the bit sequence representing the first data D1 decoded by the first decoding unit 12 with the bit sequence representing the stored unique word, and determines the presence / absence of synchronization detection based on the degree of matching. do. Further, the synchronization detection unit 14 determines whether or not synchronization detection is performed based on the degree of coincidence between the bit sequence representing the second data D2 decoded by the second decoding unit 13 and the bit sequence representing the stored unique word. judge. For example, in the case of a 20-bit unique word, if 16 bits (80%) or more of them match, it is determined that synchronization has been detected, and if it is less than that, synchronization detection has not been performed. judge.

The synchronization detection unit 14 outputs the synchronization information Im of the decoding unit of the first decoding unit 12 and the second decoding unit 13 that can be synchronously detected to the frequency correction amount calculation unit 128. When the synchronization information Im input from the synchronization detection unit 14 is the information synchronously detected from the first data D1 decoded by the first decoding unit 12, the frequency correction amount calculation unit 128 has the I signal Si and the Q signal Sq. The frequency error based on is calculated as the frequency correction amount. On the other hand, in the frequency correction amount calculation unit 128, when the synchronization information Im 14 input from the synchronization detection unit is the information synchronously detected from the second data D2 decoded by the second decoding unit 13, the I signals Si and Q The frequency correction amount is calculated by correcting the frequency error based on the signal Sq with the phase rotation amount of the pseudo-synchronous frequency. The reception symbol points (Xk1, Yk1) are obtained by subjecting the I signal Si and the Q signal Sq to predetermined processing. That is, the reception symbol points (Xk1, Yk1) are signals based on the I signal Si and the Q signal Sq. Therefore, the frequency error calculated by the frequency correction amount calculation unit 128 using the reception symbol points (Xk1, Yk1) represents the frequency error based on the I signal Si and the Q signal Sq.

When the first data D1 has a higher degree of coincidence with the unique word among the first data D1 and the second data D2 decoded by the first decoding unit 12 and the second decoding unit 13, the digital receiving device 1 determines. It is in the normal synchronization state, not in the pseudo synchronization state. Therefore, when the synchronization information Im indicating that the first decoding unit 12 has synchronized detection is output from the synchronization detection unit 14 to the frequency correction amount calculation unit 128, the synchronization detection unit 14 then synchronizes with the second decoding unit 13. The first reception path P1 is locked at the normal frequency until the synchronization information Im indicating the detection is output to the frequency correction amount calculation unit 128.

On the other hand, when the second data D2 has a higher degree of coincidence with the unique word among the first data D1 and the second data D2 decoded by the first decoding unit 12 and the second decoding unit 13, the digital receiving device 1 Is in a pseudo-synchronous state. Therefore, when the synchronization information Im indicating that synchronization has been detected by the second decoding unit 13 is output from the synchronization detection unit 14 to the frequency correction amount calculation unit 128, the synchronization detection unit 14 then synchronizes with the first decoding unit 12. The first reception path P1 is locked at the pseudo-synchronous frequency until the synchronization information Im indicating the detection is output to the frequency correction amount calculation unit 128.

As described above, when the first reception path P1 is locked at the normal frequency, the digital receiving device 1 uses the phase rotation amount based on the frequency error that is not corrected by the phase rotation amount of the pseudo-synchronous frequency. The data is decoded after rotating the phases of the data Di and the Q data Dq. On the other hand, when the first reception path P1 is locked at the pseudo-synchronous frequency, the digital receiving device 1 uses the phase rotation amount corrected by the phase rotation amount of the pseudo-synchronous frequency for the I data Di and Q. The data is decoded after rotating the phase of the data Dq. Therefore, the digital receiving device 1 can perform the next time (for example, i) regardless of whether the frequency locked by the first receiving path P1 in the previous data decoding (for example, i-1st time) is a normal frequency or a pseudo-synchronized frequency. In the data decoding of the third time), the first reception path P1 can be locked to the normal frequency.

In the digital receiving device 1, when the first receiving path P1 is locked at the pseudo-synchronous frequency in the previous (for example, i-1st) data decoding, the first receiving pass P1 is used in the next (for example, i-th) data decoding. Can be locked at a regular frequency. However, in the digital receiving device 1, there may be a case where the first receiving path P1 does not lock at the normal frequency in the next data decoding (for example, the i-th time) due to some trouble. In this case, each time the synchronization detection unit 14 detects a unique word (synchronization detection) until the first reception path P1 is locked at the normal synchronization frequency (that is, the first decoding unit 12 is in the normal synchronization state). The synchronization information Im is configured to be output to the frequency correction amount calculation unit 128. As a result, the digital receiving device 1 can finally shift the first decoding unit 12 from the pseudo synchronization state to the normal synchronization state.

Until the synchronization detection in the digital receiving device 1 is completed, the first data D1 output from the first decoding unit 12 may contain an error. However, when an error is detected in the first data D1 by the error correction decoding processing unit 15 provided in the subsequent stage of the first decoding unit 12, the digital receiving device 1 discards the first data D1 as invalid data. can do. Therefore, the digital receiving device 1 can prevent the first data D1 including an error from being output to a predetermined device (not shown) provided in the subsequent stage in a state where the synchronization detection is not completed.

<Operation of digital receiver>
Next, an operation example of the digital receiving device according to the present embodiment will be described again with reference to FIG. Hereinafter, an operation example of the digital receiving device 1 will be described by taking synchronous detection of a local signal and a carrier signal as an example.

For example, it is assumed that the first reception path P1 is locked at a normal frequency in the i-1st data decoding of the received signal including the unique word. In this case, the synchronization detection unit 14 detects synchronization because the first data D1 input from the decoding determination unit 127 has a higher degree of coincidence with the unique word than the second data D2 input from the decoding determination unit 137. do. Therefore, the synchronization detection unit 14 outputs the synchronization information Im indicating that the first decoding unit 12 has synchronously detected to the frequency correction amount calculation unit 128.

The frequency correction amount calculation unit 128 is based on the reception symbol position obtained from the reception symbol point Xk1 input from the symbol point extraction unit 125 and the reception symbol point Yk1 input from the symbol point extraction unit 126, and the normal symbol position. , The frequency error Δf _i-1 between the frequency of the local signal and the carrier frequency of the received signal is detected. The frequency correction amount calculation unit 128 calculates the frequency correction amount fC _i-1 based on the above equation (2). The frequency correction amount calculation unit 128 receives the synchronization information Im indicating that the first decoding unit 12 has synchronously detected, and the phase rotation amount α of the pseudo-synchronous frequency in the equation (2) becomes zero, so that the detection is performed. The frequency error Δf _i-1 is output to the rotation amount calculation unit 129 and the pseudo-synchronization rotation amount calculation unit 139 as the frequency correction amount fC _i-1 .

The rotation amount calculation unit 129 calculates the phase rotation amount b1 _i-1 based on the above equation (3) and outputs the phase rotation amount b1 i-1 to the phase rotation unit 121. The phase rotation unit 121 adjusts the phases of the I data Di and the Q data Dq input from the demodulation unit 11 based on the phase rotation amount b1 _i-1 input from the rotation amount calculation unit 129. The first decoding unit 12 executes the i-th data decoding using the phase-adjusted I data Di and Q data Dq in the phase rotation unit 121.

On the other hand, the pseudo-synchronous rotation amount calculation unit 139 calculates the pseudo-synchronous phase rotation amount b2 _i-1 based on the above equations (4) and (5) and outputs the pseudo-synchronous phase rotation amount b2 i-1 to the phase rotation unit 131. The phase rotation unit 131 sets the respective phases of the I data Di and the Q data Dq input from the demodulation unit 11 based on the pseudo-synchronous phase rotation amount b2 _i-1 input from the pseudo synchronization rotation amount calculation unit 139. adjust. The second decoding unit 13 executes the i-th data decoding using the phase-adjusted I data Di and Q data Dq by the phase rotation unit 131.

In the i-th data decoding, it is assumed that the synchronization detection unit 14 synchronously detects the first data D1 because the degree of coincidence with the unique word is higher than that of the second data D2. In this case, the digital receiving device 1 operates in the same manner as the i-1st data decoding process. Since the first reception path P1 is locked at the normal frequency at the time of the i-th data decoding, the frequency correction amount calculation unit 128 corrects the phase rotation amount α of the pseudo-synchronous frequency to the frequency error _Δfi . Is not done. Therefore, even at the time of i + 1th data decoding, the first reception path P1 is in the locked state at the normal frequency, and the first decoding unit 12 is in the normal synchronization state.

On the other hand, in the i-th data decoding, it is assumed that the second data D2 has a higher degree of coincidence with the unique word than the first data D1, and the synchronization detection unit 14 performs synchronous detection. In this case, the synchronization detection unit 14 outputs the synchronization information Im indicating that the second decoding unit 13 has synchronously detected to the frequency correction amount calculation unit 128.

The frequency correction amount calculation unit 128 is based on the reception symbol position obtained from the reception symbol point Xk1 input from the symbol point extraction unit 125 and the reception symbol point Yk1 input from the symbol point extraction unit 126, and the normal symbol position. , The frequency error _Δfi between the frequency of the local signal and the carrier frequency of the received signal is detected. The frequency correction amount calculation unit 128 calculates the frequency correction amount fC _i based on the above equation (2). The frequency correction amount calculation unit 128 receives the synchronization information Im indicating that the second decoding unit 13 has synchronously detected, and α in the equation (2) is the phase rotation of the pseudo-synchronous frequency corresponding to the phase of 90 degrees. The amount is α. Therefore, the frequency correction amount calculation unit 128 calculates the frequency correction amount fC _i by adding or subtracting the phase rotation amount α to the detected frequency error _Δfi , and the rotation amount calculation unit 129 and the pseudo-synchronization rotation amount calculation unit. Output to 139.

The rotation amount calculation unit 129 calculates the phase rotation amount b1 _i based on the above equation (3) and outputs the phase rotation amount b1 i to the phase rotation unit 121. The phase rotation unit 121 adjusts the phases of the I data Di and the Q data Dq input from the demodulation unit 11 based on the phase rotation amount b1 _i input from the rotation amount calculation unit 129. The first decoding unit 12 executes i + 1th data decoding using the phase-adjusted I data Di and Q data Dq in the phase rotation unit 121. At the time of the i-th data decoding, the first reception path P1 is in a state of being locked to the pseudo-synchronization frequency, but the frequency correction amount calculation unit 128 sets the frequency error _Δfi to the phase rotation amount α of the pseudo-synchronization frequency. Correction has been made. Therefore, at the time of i + 1th data decoding, the first decoding unit 12 is locked to the normal frequency, and the first decoding unit 12 is in the normal synchronization state.

On the other hand, the pseudo-synchronous rotation amount calculation unit 139 calculates the pseudo-synchronous phase rotation amount b2 _i based on the above equations (4) and (5) and outputs the pseudo-synchronous phase rotation amount b2 i to the phase rotation unit 131. The phase rotation unit 131 adjusts the phases of the I data Di and the Q data Dq input from the demodulation unit 11 based on the pseudo-synchronous phase rotation amount _b2i input from the pseudo-synchronization rotation amount calculation unit 139. .. The second decoding unit 13 executes i + 1th data decoding using the phase-adjusted I data Di and Q data Dq by the phase rotation unit 131.

As described above, in the digital receiving device 1, the first decoding unit 12 (that is, the first receiving path P1) in the i-1th data decoding is locked to either the normal frequency or the pseudo-synchronous frequency. The i-th data decoding can be executed with the decoding unit 12 (that is, the first reception path P1) locked to the normal frequency.

<Effect of digital receiver>
Next, the effect of the digital receiving device according to the present embodiment will be described with reference to FIG. 3 with reference to FIG. FIG. 4 corresponds to the frequency band FBa of the data in the decoding process (corresponding to the data output from the phase rotation units 121 and 131) and the decoding unit (corresponding to the first decoding unit 12 and the second decoding unit 13) in the digital receiving device. It is a figure which shows typically the frequency band FBb of the low-pass filter (corresponding to low-pass filters 122, 123, 132, 133) provided in). FIG. 4A is a diagram schematically showing a state in which the frequency band FBa of the data and the frequency band FBb of the low-pass filter overlap. FIG. 4B is a diagram schematically showing a state in which the frequency band FBa of the data is shifted to the positive side by Δf with respect to the frequency band FBb of the low-pass filter. FIG. 4C is a diagram schematically showing a state in which the frequency band FBa of the data is shifted to the negative side by Δf with respect to the frequency band FBb of the low-pass filter.

Before explaining the effect of the digital receiver 1 according to the present embodiment, the problems of the prior art will be described in detail.
The digital receiver described in Patent Document 1 (hereinafter referred to as "conventional digital receiver" r) has the data decoded by the decoding determination unit and the regular unique word when the decoding unit is locked to the normal frequency. It is possible to perform normal synchronous detection by correlating with. On the other hand, in the conventional digital receiving device, when the decoding unit is locked at the pseudo-synchronous frequency, the decoded data cannot be correlated with the normal unique word, but the normal unique word is deformed in the pseudo-synchronous state. The correlation between the unique word and the decoded data is detected. Therefore, the conventional digital receiving device can convert the frequency error to the correct frequency correction value by correcting the frequency error by ± 1 / (4Ts) Hz, and can lock the decoding unit to the normal frequency.

The conventional digital receiver is configured to pass through a low-pass filter after correcting the frequency error. Similar to the low-pass filters 122, 123, 132, 133 in the present embodiment, this low-pass filter is composed of, for example, a root Nyquist filter in order to obtain Nyquist characteristics in the entire system. In addition, this low-pass filter is generally designed to have steep filter characteristics with a bandwidth approximately the same as the signal band of the data being decoded, in order to also achieve out-of-frequency channel and noise removal. .. Therefore, in the digital receiving device, it is necessary to accurately correct the frequency error in the previous stage of this low-pass filter.

If the frequency-corrected signal still contains a frequency error Δf, the frequency band of the signal is shifted on the frequency axis by the frequency error Δf, as shown in FIGS. 4 (b) and 4 (c). .. As a result, the center frequency of the frequency band of the signal and the center frequency of the frequency band of the low-pass filter do not match. Of the frequency bands of the signal, the signal components in the band that does not overlap the frequency band of the low-pass filter are blocked by the low-pass filter. As a result, the signal after passing through the low-pass filter is distorted.

As shown in FIG. 4A, in the conventional digital receiver, when the decoding unit is locked at the normal frequency, the center frequency of the frequency band of the low-pass filter and the signal after correcting the frequency error are used. It matches the center frequency of the frequency band. Therefore, the signal after passing through the low-pass filter is hardly distorted. On the other hand, in the conventional digital receiving device, when the decoding unit is locked to the pseudo-synchronous frequency, the center frequency of the frequency band of the signal after correcting the frequency error is relative to the center frequency of the frequency band of the normal frequency. It is in a state where a frequency error of ± 1 / (4Ts) Hz is included. Therefore, as shown in FIGS. 4 (b) and 4 (c), a signal in which the center frequency of the frequency band is deviated by Δf = ± 1 / (4 Ts) Hz with respect to the center frequency of the frequency band of the low-pass filter is low-pass. Pass through the filter. Therefore, the signal after passing through the low-pass filter is distorted.

In a conventional digital receiver, when the decoding unit is locked at a normal frequency, synchronization is detected for a signal that is hardly distorted even if it passes through a low-pass filter. On the other hand, in the conventional digital receiving device, when the decoding unit is locked at the pseudo-synchronization frequency, the pseudo-synchronization is detected for the signal distorted by passing through the low-pass filter. Therefore, in the conventional digital receiving device, the detection accuracy of pseudo-synchronization in the state where the decoding unit is locked at the pseudo-synchronization frequency is worse than the detection accuracy of synchronization in the state where the decoding unit is locked at the normal frequency. As described above, the conventional digital receiving device has a problem that the accuracy of synchronization detection may decrease depending on the frequency locked by the decoding unit.

On the other hand, in the digital receiving device 1 according to the present embodiment, when the first receiving path P1 is locked to the normal frequency, the synchronization detection unit 14 is more than the second data D2 input from the second decoding unit 13. The first data D1 input from the first decoding unit 12 has a higher degree of coincidence with the unique word and synchronous detection is performed. Therefore, the synchronization detection unit 14 determines that the first reception path P1 is a path that has been synchronously detected. In this case, as shown in FIG. 4A, the center of each frequency band of the I data Di and the Q data Dq after the frequency correction in the first reception path P1 (that is, after the phase rotation in the phase rotation unit 121). The frequency and the center frequency of each frequency band of the low-pass filters 122 and 123 are the same. Therefore, the I data Di after passing through the low-pass filter 122 arranged in the first reception path P1 and the Q data Dq passing through the low-pass filter 123 are hardly distorted. As a result, the digital receiver 1 can perform synchronous detection with high accuracy.

In this case, the second decoding unit 13 (that is, the second reception path P2) is locked at the pseudo-synchronous frequency. Therefore, the synchronization detection unit 14 does not detect the unique word from the second data D2 output from the second reception path P2.

When the first reception pass P1 is locked at the pseudo-synchronization frequency, the second reception pass P2 has a frequency correction corresponding to the pseudo-synchronization frequency in the pseudo-synchronization rotation amount calculation unit 139, so that the second reception pass P2 has a normal frequency. It will be locked. Therefore, the synchronization detection unit 14 indicates that the second data D2 input from the second decoding unit 13 has a higher degree of coincidence with the unique word than the first data D1 input from the first decoding unit 12. To detect. As a result, the synchronization detection unit 14 determines that the second reception path P2 is a path that has been synchronously detected. In this case, as shown in FIG. 4A, the center of each frequency band of the I data Di and the Q data Dq after the frequency correction in the second reception path P2 (that is, after the phase rotation in the phase rotation unit 131). The frequency corresponds to the center frequency of each frequency band of the low-pass filters 132 and 133. Therefore, the I data Di after passing through the low-pass filter 132 and the Q data Dq after passing through the low-pass filter 133 are hardly distorted. As a result, the digital receiving device 1 can perform synchronous detection with high accuracy.

As described above, in the digital receiving device 1 according to the present embodiment, even if the first receiving path P1 which is the main path is locked at the pseudo-synchronous frequency, the first receiving path P1 is at the normal frequency in the next data decoding. Data can be decrypted in the locked state. Further, when the first reception path P1 is locked to the pseudo-synchronous frequency, the digital reception device 1 is locally generated by the second data D2 output by the second reception path P2 in the state of being locked at the normal frequency. Synchronous detection of the signal and the carrier signal can be performed. As a result, the digital receiving device 1 executes the synchronization detection of the local signal and the carrier signal with high accuracy regardless of whether the first receiving path P1 which is the main path is locked to the normal frequency or the pseudo-synchronized frequency. Can be done.

As described above, in the digital receiving device 1 according to the present embodiment, the demodulation unit 11 that detects the received signal orthogonally and demodulates it into the I signal Si and the Q signal Sq, and the I signal Si and Q demodulated by the demodulation unit 11. The first decoding unit 12 that decodes the data based on the signal Sq, and the I signal Si and Q signal Sq demodulated by the demodulation unit 11 are corrected for the reproduction carrier frequency corresponding to pseudo synchronization, and the data is decoded. The second decoding unit 13 and the synchronization detection unit 14 that detects a unique word from either the first data D1 input from the first decoding unit 12 or the second data D2 input from the second decoding unit 13. It is equipped with.

The digital receiving device 1 having such a configuration can easily establish synchronization even in a pseudo-synchronized state.

The present invention is not limited to the above embodiment, and various modifications are possible.
The digital receiver 1 according to the above embodiment performs orthogonal detection with an RF signal and separates an I signal and a Q signal. However, after converting the RF signal into an intermediate frequency (IF) signal, an A / D converter is used for undersampling. It may be configured to perform orthogonal detection by performing.

Further, the synchronization detection unit 14 provided in the digital reception device 1 has the first reception path P1 after the first reception path P1 is locked to the normal frequency (that is, the first decoding unit 12 is in the normal synchronization state). May be configured so that the synchronization information Im is not output to the frequency correction amount calculation unit 128 until is locked at the pseudo-synchronization frequency (that is, the first decoding unit 12 is in the pseudo-synchronization state). As a result, the digital receiving device 1 can reduce the processing load of data decoding.

Further, in the digital receiving device 1, after the first receiving path P1 is locked to the normal synchronization frequency (that is, the first decoding unit 12 is in the normal synchronization state), the first receiving path P1 is released from the normal synchronization state. The operation of the second decoding unit 13 may be stopped until this is done. In this case, for example, in the digital receiving device 1, after the operation of the second decoding unit 13 is stopped, the correlation with the unique word of the first data D1 in which the received signal including the unique word is decoded becomes lower than the predetermined threshold value. (That is, the degree of coincidence with the unique word becomes lower than the predetermined threshold value), the operation of the second decoding unit 13 is restarted. As a result, the digital receiving device 1 can reduce the processing load of data decoding and prevent a decrease in the detection accuracy of synchronous detection.

Further, in the above embodiment, although described by QPSK modulation, the present invention is also effective for 4-phase PSK modulation signals such as DQPSK and π / 4 shift DQPSK.

1 Digital receiver 11 Demodulation unit 12 Demodulation unit 12 First decoding unit 13 Second decoding unit 14 Synchronous detection unit 15 Correction decoding processing unit 111 Antenna 112 Local oscillator 113 90 degree phase shifter 114, 115 Mixer 116, 117 A / D converter 121 , 131 Phase rotation unit 122, 123, 132, 133 Low-pass filter 124, 134 Symbol clock reproduction unit 125, 126, 135, 136 Symbol point extraction unit 127, 137 Decoding judgment unit 128 Frequency correction amount calculation unit 129 Rotation amount calculation unit 139 Pseudo-synchronization rotation amount calculation unit

Claims (6)

A demodulator that detects the received signal orthogonally and demodulates it into an I signal and a Q signal,
A first decoding unit that decodes data based on the I signal and the Q signal demodulated by the demodulation unit, and
A second decoding unit that decodes the data by correcting the reproduction carrier frequency corresponding to pseudo-synchronization with respect to the I signal and the Q signal demodulated by the demodulation unit.
A digital receiving device including a synchronization detection unit that detects a unique word representing a synchronization word from either one of the data input from the first decoding unit and the data input from the second decoding unit. .. The digital according to claim 1, wherein the first decoding unit has a frequency correction amount calculation unit that calculates a frequency correction amount based on a frequency error between the frequency of the local signal and the carrier frequency of the received signal. Receiver. The second decoding unit is characterized by having a pseudo-synchronization rotation amount calculation unit that calculates the phase rotation amount of the pseudo-synchronization frequency, which is the carrier frequency in the pseudo-synchronization state, based on the frequency correction amount. The digital receiver described in. The synchronization detection unit includes first data decoded by the first decoding unit based on the I signal and Q signal demodulated by the demodulation unit of the specific signal which is the reception signal including the unique word, and the said. The unique word included in any of the second data decoded by the second decoding unit based on the I signal and the Q signal whose specific signal is demodulated by the demodulation unit is detected, and the first decoding unit or the first decoding unit or the specific signal is detected. The digital receiving device according to claim 3, wherein it detects that any of the second decoding units is synchronized. The digital receiving device according to claim 4, wherein the synchronization detection unit outputs the synchronization information of the decoding unit of the first decoding unit and the second decoding unit that can be synchronously detected to the frequency correction amount calculation unit. .. The frequency correction amount calculation unit is
When the synchronization information input from the synchronization detection unit is information synchronously detected from the first data decoded by the first decoding unit, the frequency error based on the I signal and the Q signal is set to the frequency. Calculated as a correction amount,
When the synchronization information input from the synchronization detection unit is information synchronously detected from the second data decoded by the second decoding unit, the frequency error based on the I signal and the Q signal is simulated. The digital receiver according to claim 5, wherein the frequency correction amount is calculated by correcting with a synchronous frequency.

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