JP2996967B2 - Receiving machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver, and more particularly, to a two-phase and eight-phase, a two-phase and four-phase, a four-phase and eight-phase, or a two-phase and four-phase in a hierarchical transmission system or the like. A PSK modulated signal obtained by time-multiplexing a digital signal modulated by a plurality of types of PSK modulation schemes having different numbers of phases such as a phase and an 8-phase is demodulated using a carrier reproduced by a carrier reproducing means, and I, Q The present invention relates to a receiver that outputs symbol stream data.

[0002]

2. Description of the Related Art A plurality of modulation schemes that require different C / N, such as 8PSK modulated wave, QPSK modulated wave, BP
A digital satellite T based on a hierarchical transmission system in which SK modulated waves are time-multiplexed and repeatedly transmitted for each frame.
Practical use of V broadcasting is in progress.

FIG. 9A is an explanatory diagram showing an example of a frame configuration in the hierarchical transmission system. One frame is BPS
A frame synchronization signal pattern composed of 32 symbols modulated by K (the latter 20 symbols are actually used as a frame synchronization signal in 32 symbols), and a TM for identifying a transmission multiplex configuration composed of 128 symbols modulated by BPSK.
CC (Transmission and Multiplexing Configuration)
Control) pattern, a superframe identification signal pattern consisting of 32 symbols (the latter 20 symbols are actually used as a superframe identification signal in 32 symbols), 8PSK (trellis codec 8PSK) modulated main signal of 203 symbols, pseudo Random noise (P
N) A 4-symbol burst symbol signal (BS) with a BPSK-modulated signal, a 203-symbol main signal with a 8PSK (trellis codec 8PSK) modulation, and a 4-symbol burst symbol with a pseudo-random noise (PN) signal BPSK-modulated A signal (BS), a QPSK-modulated 203-symbol main signal, a pseudo-random noise (PN) signal, a BPSK-modulated 4-symbol burst symbol signal (BS), a QPSK-modulated 203-symbol main signal, The BPSK-modulated burst symbol signal (BS) is composed of four symbols.

[0004] In a receiver for receiving a digital modulated wave (PSK modulated wave) by the hierarchical transmission system, an intermediate frequency signal of a received signal received by a receiving circuit is demodulated by a demodulating circuit, and I signals having orthogonal relations to each other. Two series of I and Q baseband signals (hereinafter, I and Q baseband signals are also referred to as I and Q symbol stream data) representing instantaneous values for each symbol on the axis and the Q axis are obtained. The frame synchronization signal is captured from the demodulated I and Q baseband signals, the current received signal phase rotation angle is obtained from the signal point arrangement of the captured frame synchronization signal, and demodulated based on the obtained received signal phase rotation angle. By rotating the I and Q base band signals in opposite phases, an absolute phase conversion circuit that performs absolute phase matching to the transmission signal phase angle is performed.

[0005] As shown in FIG. 10, an absolute phase shift circuit of a receiver for receiving a PSK modulated wave according to the conventional hierarchical transmission method is provided on the output side of a demodulation circuit 1 to capture a frame synchronization signal. It comprises a frame synchronization detecting / reproducing circuit 2 as a synchronizing signal capturing means, a remapper 7 as an anti-phase rotating means composed of a ROM, and a received signal phase rotation angle detecting circuit 8 as a received signal phase rotating angle detecting means. Reference numeral 9 denotes a transmission configuration identification circuit for identifying the transmission multiplex configuration shown in FIG. 9A, and outputs a 2-bit modulation scheme identification signal DM.

The demodulation circuit 1 performs quadrature detection on the intermediate frequency signal to obtain I and Q baseband signals. 10 of the demodulation circuits 1
Is synchronized in frequency and phase with the received carrier and has a phase of 9
Two reference carriers f _C1 (= co
s ωt) and carrier recovery circuit for recovering f _C2 (= sin ωt), 60 and 61 are multipliers for multiplying the intermediate frequency signal IF by f _C1 and f _C2 , and 62 and 63 are the outputs of multipliers 60 and 61 A / D converters for performing A / D conversion at a sampling rate twice as high as the symbol rate, and 64 and 65 are A / D converters 62 and 6
A digital filter for limiting the band of the output of the digital filter 3 by digital signal processing.
4 and 65 are thinned out to 1/2 sampling rate, and two series of I and Q baseband signals (I and Q symbol stream data) representing instantaneous values for each symbol on the I and Q axes are output. The decimation circuits 66 and 67 have I and Q baseband signals I (8) and Q (8) of 8 bits (two's complement system) (the numbers in parentheses indicate the number of quantization bits. (They are also simply referred to as I and Q with the number of coded bits omitted).

Here, mapping for each modulation scheme on the transmitting side will be described with reference to FIG. FIG.
(1) shows a signal point arrangement on an IQ phase plane (also referred to as an IQ vector plane or an IQ signal space diagram) when 8PSK is used as a modulation scheme. In the 8PSK modulation method, a 3-bit digital signal (abc) can be transmitted by one symbol, and the combination of bits forming one symbol is (000), (001), (010), (01).
1), (100), (101), (110), (11)
There are 8 types of 1). These three-bit digital signals are converted into signal point arrangements "0" to "7" on the transmission-side IQ phase plane in FIG. 11A, and this conversion is called 8PSK mapping.

In the example shown in FIG. 11A, the bit string (00
0) to the signal point arrangement “0”, the bit string (001) to the signal point arrangement “1”, the bit string (011) to the signal point arrangement “2”, the bit string (010) to the signal point arrangement “3”,
The bit string (100) is assigned to the signal point arrangement “4”, the bit string (101) is assigned to the signal point arrangement “5”, and the bit string (111) is assigned.
Is converted into a signal point arrangement “6”, and the bit string (110) is converted into a signal point arrangement “7”.

FIG. 11 (2) shows a signal point arrangement on an IQ phase plane when QPSK is used as a modulation method.
In the modulation method, a 2-bit digital signal (de) can be transmitted by one symbol, and there are four combinations of bits constituting the symbol: (00), (01), (10), and (11). In the example of FIG. 11B, for example, the bit string (00) is assigned to the signal point arrangement “1”, the bit string (01) is assigned to the signal point arrangement “3”, the bit string (11) is assigned to the signal point arrangement “5”, and the bit string ( 10) is converted to a signal point arrangement “7”.

FIG. 11 (3) shows a signal point arrangement when BPSK is used as a modulation method. In the BPSK modulation method, a 1-bit digital signal (f) is transmitted by one symbol.
In the digital signal (f), for example, bit (0) is converted into a signal point arrangement "0" and bit (1) is converted into a signal point arrangement "4". Note that the relationship between the signal point constellation and the constellation number for each modulation scheme is the same as that between the signal point constellation and the constellation number based on 8 BPSK. QPS in hierarchical transmission system
The I axis and Q axis of K and BPSK coincide with the I axis and Q axis of 8PSK.

If the phase of the received carrier wave and the phases of the reference carrier waves f _C1 and f _C2 reproduced by the carrier wave reproduction circuit 10 match, the signal point arrangement “0” to “0” on the IQ phase plane on the transmission side is obtained.
When the digital signal corresponding to “7” is received, the phase of the received signal point on the IQ phase plane by the I and Q baseband signals I (8) and Q (8) on the receiving side matches the transmitting side. I do. Therefore, the received digital signal can be correctly identified from the signal point arrangement of the reception signal points, using the correspondence between the signal point arrangement and the digital signal on the transmission side (see FIG. 11) as it is.

However, actually, the reference carrier f _C1 , f _C2
Can be in various phase states with respect to the received carrier, so that the received signal point on the receiving side has a phase position rotated by a certain angle θ with respect to the transmitting side. Then, if the phase of the received carrier changes, θ also changes. If the phase of the received signal point rotates at random with respect to the transmitting side, the received digital signal cannot be identified. For example, when θ = π / 8, the transmission side 8P
The digital signal (000) having the signal point arrangement "0" in the SK modulation method is received at the signal point arrangement "0" because the reception signal point is located at the center between the signal point arrangements "0" and "1" on the receiving side. If it is assumed that the digital signal (000) has been received correctly, it is mistaken that the digital signal (001) has been received if it is assumed that the digital signal (001) has been received in the signal point arrangement "1". Therefore, the carrier recovery circuit 10 controls the reference carrier f so that the reception signal point keeps a certain rotation angle with respect to the transmission side.
The phases of _C1 and _fC2 are corrected so that digital signals can be correctly identified.

More specifically, the VCO of the carrier recovery circuit 10
A reference carrier f _C1 is created by oscillating a (voltage-controlled oscillator) 11 at the transmission carrier frequency, and a reference carrier f _C2 is created by delaying the phase of the oscillation signal of the VCO 11 by 90 ° by the 90 ° phase shifter 12. Then, by varying the control voltage of the VCO 11, the phases of the reference carrier waves f _C1 and f _C2 can be varied. The carrier recovery circuit 10 has 8P
Various data sets of I and Q baseband signals I (8) and Q (8) and carrier phase error data of 8 bits (two's complement system) for each of SK, QPSK and BPSK modulation schemes (Hereinafter, also simply referred to as phase error data) Δ
The phase error tables 13, 14-1 and 14-2, each of which is made up of a ROM, in which the correspondence relationship of φ (8) is
15-1 to 15-4 are provided (see FIG. 12). Each phase error table 13, 14-1 and 14-2, 15-1 to
15-4 include I and Q baseband signals I (8) and Q
(8) is input in parallel. The phase error table selectively enabled by the selector described later includes the I and Q baseband signals I (8) and Q input from the demodulation circuit 1.
The phase error data Δφ (8) corresponding to (8) is output.

The phase error table 13 is for 8PSK. The phase on the IQ phase plane of the received signal points indicated by the I and Q baseband signals I (8) and Q (8) input from the demodulation circuit 1 is shown. Angle φ (see FIG. 13) and phase error data Δφ
The relationship with (8) is configured as shown in FIG. The selector 16 receives the I and Q baseband signals I from the demodulation circuit 1.
(8) According to the clock CLK _SYB (see FIG. 9 (2)) at the symbol rate synchronized with the output of Q (8), while the demodulation circuit 1 is demodulating the digital modulated wave by the 8PSK modulation method (described later). (Specified by the modulation scheme identification signal DM from the transmission configuration identification circuit 9), only the phase error table 13 is enabled (active), and the demodulation circuit 1
Are the I and Q baseband signals I (8) and Q for one symbol
Every time (8) is output, the phase error data Δφ (8) corresponding to the set data of I (8) and Q (8) is read. The phase error data Δφ (8) is converted into a phase error voltage by the D / A converter 17, and then a low-frequency component is extracted by the LPF 18 and applied to the VCO 11 as a control voltage. If the phase error data Δφ (8) is 0, the output of the LPF 18 does not change and the phases of the reference carriers f _C1 and _{fc 2} do not change, but if the phase error data Δφ (8) is +, the LPF 1
8 increases, the phases of the reference carriers f _C1 and f _c2 are delayed, and conversely, if the phase error data Δφ (8) is −, L
The output of PF18 is reduced, the phase of the reference carrier f _C1, f _c2 is advanced.

In the phase error table 13, the difference between φ and the phase of the nearest signal point arrangement “0” to “7” is the phase error data Δφ (8). Therefore, 8PS on the transmitting side
Phase 0, π / 4, 2π / 4, 3π / 4,
Digital signals having signal point arrangements of 4π / 4, 5π / 4, 6π / 4, and 7π / 4 are respectively expressed by 受 信 in the IQ phase plane on the receiving side.
= M × π / 4 (where m is an arbitrary integer from 0 to 7; see FIG. 14). Θ is the received signal phase rotation angle. As a result, the received signal points of the 8PSK modulation method have phases 0, π / 4, 2π / 4, 3π /
4, 4π / 4, 5π / 4, 6π / 4, 7π / 4, so that the signal point arrangement “0” to “7” on the IQ phase plane on the receiving side is the same as that on the transmitting side. It can be assigned to the phase (however, the correspondence between the signal point arrangement and the digital signal changes according to Θ). If Θ is detected and the phase is rotated by −Θ, the correspondence between the signal point arrangement and the digital signal can be made the same as that on the transmitting side (absolute phase conversion), and the received digital signal can be easily identified.

The phase error tables 14-1 and 14-2 have Q
For PSK, I and Q baseband signals I (8), Q
The phase angle φ on the IQ phase plane of the received signal point shown in (8)
FIG. 16 and FIG. 17 show the relationship between
It is configured as follows. During normal reception, the selector 16 _{operates in} accordance with the symbol rate clock CLK _SYB ,
Is demodulating the digital modulated wave by the QPSK modulation method, while the received signal phase rotation angle Θ is 0, 2π / 4, 4π
/ 4, 6π / 4, only the phase error table 14-1 is enabled, and the demodulation circuit 1 outputs I, Q for one symbol.
Each time the baseband signals I (8) and Q (8) are output,
The phase error data Δφ (8) corresponding to the set data of I (8) and Q (8) is read from the phase error table 14-1.

In the phase error table 14-1, the difference between φ and the phase of the nearest signal point arrangement “1”, “3”, “5”, “7” is the phase error data Δφ. Therefore, the phase π / 4, 3π / 4 in the QPSK modulation scheme on the transmission side,
5π / 4, 7π / 4 signal point arrangement “1”, “3”,
The digital signals “5” and “7” are respectively transmitted to the I side on the receiving side.
The position is rotated to the position rotated by Θ on the −Q phase plane.
If Θ = 0, 2π / 4, 4π / 4, 6π / 4, QPS
The reception signal point of the K modulation method has a phase of π / 4, 3π / 4, 5π
/ 4, 7π / 4. If Θ is detected and the phase is rotated by −Θ, the correspondence between the signal point arrangement and the digital signal can be made the same as that on the transmitting side (absolute phase conversion), and the received digital signal can be easily identified.

The selector 16 determines whether the demodulation circuit 1 has a QPS
While demodulating a digital modulated wave by the K modulation method, if Θ = π / 4, 3π / 4, 5π / 4, 7π / 4, only the phase error table 14-2 is enabled,
The demodulation circuit 1 outputs the I and Q baseband signals I for one symbol.
Each time (8) and Q (8) are output, the I (8) and Q (8)
Phase error data Δφ (8) corresponding to the set data of (8)
From the phase error table 14-2. In the phase error table 14-2, φ and the nearest signal point arrangement “0”,
The difference between the phases “2”, “4”, and “6” is the phase error data Δφ. Therefore, the digital signals of the signal point arrangements “1”, “3”, “5”, and “7” with phases π / 4, 3π / 4, 5π / 4, and 7π / 4 in the QPSK modulation scheme on the transmission side are obtained. , Respectively, are corrected to positions rotated by the angle で on the IQ phase plane on the receiving side. Θ = π / 4, 3π / 4, 5π /
In the case of 4,7π / 4, the received signal point of the QPSK modulation method comes at the phase 0, 2π / 4, 4π / 4, 6π / 4. Θ
If the phase is detected and the phase is rotated by -Θ, the phase can be made the same as the transmitting side (absolute phase conversion), the correspondence between the signal point arrangement and the digital signal can be made the same as the transmitting side, and the digital signal received easily can be Can be identified.

The phase error tables 15-1 to 15-4 are B
For PSK, I and Q baseband signals I (8), Q
The phase angle φ on the IQ phase plane of the received signal point shown in (8)
The relationship between the phase error data Δφ (8) and
It is configured as follows. The selector 16 synchronizes with the symbol rate clock CLK _SYB , and the demodulation circuit 1
If the received signal phase rotation angle に よ る by correcting the phase of the 8PSK modulation portion is 0, 4π / 4 while demodulating the digital modulated wave by the K modulation method, the phase error table 14−
1 is enabled, and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, it corresponds to the set data of the I (8) and Q (8). The phase error data Δφ (8) to be read is read from the phase error table 15-1.

In the phase error table 15-1, the difference between φ and the phase of the nearest signal point arrangement “0” or “4” is the phase error data Δφ. Therefore, BPSK on the transmitting side
Signal point arrangement “0” of phase 0, 4π / 4 in modulation scheme,
Each of the digital signals "4" is corrected to the position rotated by the angle Θ on the IQ phase plane on the receiving side. Θ = 0, 4
In the case of π / 4, the received signal point of the BPSK modulation method comes at the phase 0, 4π / 4.

Further, while demodulating the digital modulated wave by the BPSK modulation method, the selector 16 generates Θ = π /
In the case of 4, 5π / 4, only the phase error table 15-2 is enabled, and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-2. In the phase error table 15-2, the difference between φ and the phase of the nearest signal point arrangement “1” or “5” is the phase error data Δ
φ. Accordingly, the digital signals of the signal point constellations “0” and “4” of the phases 0 and 4π / 4 in the BPSK modulation scheme on the transmission side are respectively transmitted on the IQ phase plane of the reception side by the Θ.
Corrected to the rotated position. Θ = π / 4, 5π / 4
In the case of, the received signal point of the BPSK modulation method has a phase of π / 4,
Come to 5π / 4.

Further, while demodulating a digital modulated wave by the BPSK modulation method, the selector 16 outputs Θ = 2π /
In the case of 4, 6π / 4, only the phase error table 15-3 is enabled, and each time the demodulation circuit 1 outputs the I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-3. In the phase error table 15-3, the difference between φ and the phase of the nearest signal point arrangement “2” or “6” is the phase error data Δ
φ. Accordingly, the digital signals of the signal point constellations “0” and “4” of the phases 0 and 4π / 4 in the BPSK modulation scheme on the transmission side are respectively transmitted on the IQ phase plane of the reception side by the Θ.
Corrected to the rotated position. Θ = 2π / 4, 6π /
4, the received signal point of the BPSK modulation method has a phase of 2π /
Comes at 4,6π / 4.

Further, the selector 16 demodulates the digital modulated wave by the BPSK modulation method while Θ = 3π /
In the case of 4, 7π / 4, only the phase error table 15-4 is enabled, and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-4. In the phase error table 15-4, the difference between φ and the phase of the nearest signal point arrangement “3” or “7” is the phase error data Δ
φ. Accordingly, the digital signals of the signal point constellations “0” and “4” of the phases 0 and 4π / 4 in the BPSK modulation scheme on the transmission side are respectively transmitted on the IQ phase plane of the reception side by the Θ.
Corrected to the rotated position. Θ = 3π / 4, 7π /
In the case of 4, the received signal point of the BPSK modulation method has a phase of 3π /
Comes at 4,7π / 4. Also in the case of BPSK modulation, if Θ is detected and the phase is rotated by −Θ in opposite phase, the phase can be made the same as that on the transmitting side (absolute phase conversion), and the correspondence between the signal point arrangement and the digital signal can be made the same as on the transmitting side. The received digital signal can be easily identified.

On the other hand, the frame synchronization detecting / reproducing circuit 2 comprises a BPSK demapper 3, a synchronization detecting circuit 4
0 to 47, a frame synchronization circuit 5, an OR gate circuit 53,
It comprises a frame synchronization signal generator 6. The reception signal phase rotation angle detection circuit 8 includes delay circuits 81, 82, 0
° / 180 ° phase rotation circuit 83, averaging circuits 84, 8
5. It comprises a reception phase determination circuit 86.

The I and Q baseband signals I (8) and Q (8) output from the demodulation circuit 1 are used to capture a BPSK-modulated frame synchronization signal, for example. 3 and BP
The SK demapped bit stream B0 is output. The BPSK demapper unit 3 is constituted by, for example, a ROM.

Next, the frame synchronization signal will be described.
In the hierarchical transmission method, the frame synchronization signal is transmitted after being subjected to BPSK modulation requiring the lowest C / N. The bit stream of the frame synchronization signal composed of 20 bits is (S0S1... S18S19) = (11101)
100110100101000), and are sequentially transmitted from S0. Hereinafter, the bit stream of the frame synchronization signal is also referred to as “SYNCPAT”. This bit stream is converted into a signal point arrangement “0” or “4” by the BPSK mapping shown in FIG. 11 (3) on the transmission side, and the converted symbol stream is transmitted.

In order to capture a frame synchronization signal of 20 bits, that is, 20 symbols transmitted by BPSK modulation, contrary to the mapping converted on the transmission side,
It is necessary to convert received symbols into bits by the BPSK demapping shown in FIG. Therefore, as shown in FIG. 23A, when the demodulated signal is received in the hatched area on the IQ phase plane on the receiving side (0), and when the demodulated signal is received in the portion without the hatched ( 1) is determined. That is, the output is set to (0) or (1) depending on which of the two determination areas divided by the BPSK determination boundary line shown by the thick line in FIG.

I, Q Baseband signals I (8), Q
(8) is BPSK demapping to perform BPSK demapping.
The bit stream B0 input to the K demapper 3 and subjected to BPSK demapping in the BPSK demapper 3
Is output. In this specification, a demapper refers to a circuit that performs demapping. The bit stream B0 is input to the synchronization detection circuit 40, and the synchronization detection circuit 40 captures a bit stream of a frame synchronization signal from the bit stream B0.

Next, the synchronization detecting circuit 40 will be described with reference to FIG. The synchronization detection circuit 40 is connected in series
It has zero D-flip-flops (hereinafter referred to as DF / F) D19 to D0, and these DF / FD19 to D0 constitute a 20-stage shift register. The bit stream B0 is input to the DF / FD19, and sequentially,
Shifted up to DF / FD0 and simultaneously DF
The outputs of / FD19 to / FD0 are input to the AND gate 51 after a logical inversion is performed on predetermined bits. In the AND gate 51, the output states of DF / FD19 to D0 (D0D
1 ... D18D19) is (111011001101001)
01000), the output S of the AND gate 51
YNA0 becomes high potential. That is, when SYNCPAT is captured, SYNA0 becomes high potential.

The output SYNA0 of the synchronization detection circuit 40 is OR
The signal is input to the frame synchronization circuit 5 via the gate circuit 53. In the frame synchronization circuit 5, when it is confirmed that the output SYA of the OR gate circuit 53 repeatedly becomes a high potential every fixed frame period, it is determined that the frame synchronization is established, and a frame synchronization pulse is output every frame period. You.

Normally, in a hierarchical transmission system in which a plurality of required modulation systems having different C / Ns are time-multiplexed and repeatedly transmitted for each frame, header data indicating their multiplexing structure is multiplexed. (TM in FIG. 9 (1)
CC pattern). After the frame synchronization detection / reproduction circuit 2 determines that the frame synchronization is established, the transmission configuration identification circuit 9 outputs the BP input from the frame synchronization detection / reproduction circuit 2.
A TMCC indicating a multiplex configuration is extracted from the bit stream after the SK demapper, decoded, and a modulation scheme identification signal DM indicating what modulation scheme the current I and Q baseband signals I and Q are output to the selector 16 and the like. (Fig. 9
(See (2)). Also, the reception signal phase rotation angle detection circuit 8
Detects the received signal phase rotation angle Θ based on the reproduced frame synchronization signal output from the frame synchronization signal generator 6 after the frame synchronization detection / reproduction circuit 2 determines that the frame is synchronized. The bit reception signal phase rotation angle signal AR (3) is output to the remapper 7, the selector 16 of the carrier recovery circuit 10, and the like.

The selector 16 of the carrier recovery circuit 10 receives the modulation scheme identification signal DM from the transmission configuration identification circuit 9 and the reception signal phase rotation angle signal AR (3) from the reception signal phase rotation angle detection circuit 8. After that, the phase error data Δφ (8) is read from the phase error table corresponding to the modulation method and the received signal phase rotation angle Θ, and is output to the D / A converter 17, but until then, the phase error for 8PSK is obtained. The phase error data Δφ (8) is read from the table 13.

Therefore, the demodulation circuit 1 always operates at 8PSK until the transmission configuration identification circuit 9 identifies the multiplex configuration and the reception signal phase rotation angle detection circuit 8 detects the reception signal phase rotation angle Θ.
Since it operates as a demodulation circuit, depending on the phase state of the reference carrier waves f _C1 and f _C2 reproduced by the carrier wave recovery circuit 10 in the demodulation circuit 1, the reception signal point becomes Θ = m ×
The phase is rotated by π / 4 (m is an integer from 0 to 7).

That is, as shown in FIG. 11 (3), BPSK mapping is performed on the transmitting side to the signal point arrangement "0" for bit (0) and to the signal point arrangement "4" for bit (1). The received signal point of the symbol stream of the frame synchronization signal is a signal point arrangement “0” where Θ = 0 as in the transmitting side depending on the phase state of the reference carriers f _C1 and f _C2 ,
The signal point arrangements "1" and "5" appearing at "4", Θ = π / 4 phase rotation, and the signal point arrangements "2" and "6" appearing at Θ = 2π / 4 phase rotation. And Θ
= 3π / 4 phase-rotated signal point constellations “3” and “7”, Θ = 4π / 4 phase-rotated signal point constellations “4” and “0”, and Θ = 5π / A case where the signal point arrangement appears in the signal point arrangement “5” and “1” rotated by four phases, and と = 6
The case where the signal point constellation “6” or “2” appears by rotating the phase by π / 4, or the signal point constellation “7” by rotating Θ = 7π / 4 phase.
There are eight different phase states of the demodulated frame synchronization signal, as in the case of appearing at “3”. For this reason, it is necessary to be able to capture a frame synchronization signal that has been demodulated at any phase.

Therefore, the BPSK demapper unit 3 is
As shown in FIG. 5, Θ = 0 (m = 0), Θ = π / 4 (m =
1), Θ = 2π / 4 (m = 2),..., Θ = 6π / 4
(M = 6) and BPSK demappers 30 to 37 corresponding to a phase rotation of Θ = 7π / 4 (m = 7).

FIG. 23 (2) shows that the symbol stream of the demodulated frame synchronization signal is rotated by Θ = π / 4 phase, bit (0) is in signal point arrangement “1” and bit (1) is
Shows the BPSK demapping for the case where appears in the signal point arrangement “5”. The BPSK determination boundary indicated by the bold line in FIG. 23 (2) is counterclockwise with respect to the BPSK determination boundary indicated by the bold line in the BPSK demapping of FIG. It rotates π / 4. By using a BPSK demapper (see reference numeral 31 in FIG. 25) for performing BPSK demapping as shown in FIG. 23 (2), it is possible to stably capture a frame synchronization signal rotated by Θ = π / 4 phase. BP with BPSK demapper 31
The SK demapped bit stream is the BP in FIG.
This is the output B1 of the SK demapper unit 3.

Similarly, the BPSK demappers 32 to 37
Respectively correspond to 2π / counterclockwise with respect to the BPSK determination boundary line indicated by the bold line of the BPSK demapping in FIG.
BPS rotated by 4, 3π / 4, ..., 7π / 4
BPSK demapping at the K decision boundary line, Θ = 2π /
A frame synchronization signal whose phase is rotated by 4, 3π / 4,..., 7π / 4 is stably captured. BPSK demapper 32
The bit stream subjected to BPSK demapping at to 37 is the outputs B2 to B7 of the BPSK demapper unit 3 in FIG. The BPSK demapper 30 performs BPSK demapping at the BPSK determination boundary indicated by the bold line of the BPSK demapping in FIG. 23A, and stably captures a frame synchronization signal of Θ = 0. BPSK with BPSK demapper 30
The demapped bit stream is BPSK of FIG.
This is the output B0 of the demapper unit 3.

The circuit configuration of the synchronization detection circuits 41 to 47 is the same as that of the synchronization detection circuit 40. By providing such synchronization detection circuits 40 to 47, the demodulation circuit 1
Irrespective of the phase rotation of the baseband signal due to the phase state of the reference carrier waves f _C1 and f _C2 reproduced by the carrier reproduction circuit 10 in any one of the synchronization detection circuits 40 to
At 47, the frame synchronization signal is captured, and a high-potential SYNAn
(N is an integer from 0 to 7) is transmitted.

S output from the synchronization detection circuits 40 to 47
YNAn is input to the OR gate circuit 53, and the OR gate circuit 53 outputs the logical sum SYNA of SYNAn. When it is confirmed that the high potential of the SYNA is alternately and repeatedly input at regular frame intervals, the frame synchronization circuit 5 determines that frame synchronization is established, and outputs a frame synchronization pulse FSYNC at each frame period. .
According to the frame synchronization pulse FSYNC output from the frame synchronization circuit 5, the frame synchronization signal generator 6
The pattern SY of the frame synchronization signal captured by the SK demapper 3, the synchronization detection circuits 40 to 47, and the frame synchronization circuit 5.
It generates the same bit stream as NCPAT (this is called a playback frame synchronization signal).

A frame synchronization signal is captured from the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1 by the frame synchronization detection / reproduction circuit 2 shown in FIG. The process until the reproduction frame synchronization signal is output from the frame synchronization signal generator 6 has been described. Next, the transmission configuration identification operation by the transmission configuration identification circuit 9 will be described. The transmission configuration identification circuit 9 includes bit streams B0 to B7 output from the BPSK demapper 3 of the frame synchronization detection / reproduction circuit 2, SYNA0 to SYNA7 output from the synchronization detection circuits 40 to 47, and a frame synchronization circuit 5.
Is input. Then, when the frame synchronization pulse FSYNC is input, a bit stream Bn of a system having a high potential repeatedly among SYNA0 to SYNA7 is fetched, and a predetermined timing signal generated from the frame synchronization pulse FSYNC is used as shown in FIG. ) Is extracted and decoded, and a modulation scheme identification signal D indicating which modulation scheme the current I and Q baseband signals I and Q are based on.
M is output (see FIG. 9 (2)).

Next, the present received signal phase rotation angle is obtained from the signal point arrangement of the captured frame synchronization signal, and the demodulated I and Q baseband signals I (8 ) And Q (8) will be described in terms of absolute phase conversion by rotating them in opposite phases. Each symbol of the symbol stream of the frame synchronization signal, which is BPSK-mapped and transmitted on the transmission side and demodulated into I and Q baseband signals I (8) and Q (8) by the demodulation circuit 1, is converted by the BPSK demapper unit 3 The symbol is demapped to bit (0) or (1). The phase difference between the symbol demapped to bit (0) and the symbol demapped to (1) is 180 °. Therefore, the symbol stream demapped to bit (0) can be obtained by rotating the symbol demapped to bit (1) of the frame synchronization signal portion of the received symbol stream by 180 °.

Further, by determining the average value over a plurality of symbols of the symbol stream demapped to all the bits (0), the reception signal point arrangement with respect to the BPSK bit (0) is obtained. Therefore, the received signal point for bit (0) of the determined BPSK,
The transmitting side obtains a phase difference from the signal point arrangement “0” mapped to bit (0), and calculates this as the received signal phase rotation angle Θ.
And η = −
By performing the phase rotation of Θ, the I and Q baseband signals I (8) and Q (8) can be made to have an absolute phase.

As described above, in response to the frame synchronization pulse output from the frame synchronization circuit 5, the frame synchronization signal generator 6 sets the pattern S of the captured frame synchronization signal.
The same bit stream as that of YNCPAT is generated and supplied to a 0 ° / 180 ° phase rotation circuit 83 in the reception signal phase rotation angle detection circuit 8 as a reproduced frame synchronization signal. 0
The {/ 180} phase rotation circuit 83 converts the I and Q baseband signals in the case of (1) based on the bit (0) or (1) in the bit stream of the supplied reproduced frame synchronization signal. The phase is rotated by 180 °, and in the case of (0), the phase is not rotated.

The timing of the bit stream of the reproduced frame synchronization signal sent from the frame synchronization signal generator 6 and the timing of the symbol stream of the frame synchronization signal in the I and Q symbol streams are 0 ° / 180 ° by the delay circuits 81 and 82. The phase is matched on the input side of the phase rotation circuit 83. Since the delay circuits 81 and 82 open their output gates only while the frame synchronization signal section signal is being output from the frame synchronization signal generator 6, the delay circuit 8
From I and 82, I and Q symbol streams DI (8) and DQ (8) of the frame synchronization signal portion are output. These I and Q symbol streams DI (8) and DQ (8)
The symbol portion corresponding to bit (1) in the bit stream of the reproduced frame synchronization signal is rotated by 180 ° in the 0 ° / 180 ° phase rotation circuit 83, and the symbol portion corresponding to bit (0) is not phase-rotated. , Symbol streams VI (8) and VQ (8) to the averaging circuits 84 and 85. The symbol streams VI (8) and VQ (8) are symbol streams when a BPSK-mapped signal is received on the transmission side on the assumption that all 20 bits forming the frame synchronization signal are bits (0).

FIG. 26A shows the received signal phase rotation angle Θ = 0.
26 shows the signal point arrangement of the I and Q symbol streams I (8) and Q (8) of the frame synchronizing signal when the signal is received in FIG.
3, the I and Q symbol streams V converted
The signal point arrangement of I (8) and VQ (8) is shown. I and Q symbol streams VI (8), VQ (8)
Are sent to averaging circuits 84 and 85, respectively.
After the quantization bit length is converted to about 16 to 18 bits, four frames (20 × 4 = 80 symbols) are averaged, and the averaged value is based on the original 8-bit quantization bit length. Output as AVI (8) and AVQ (8). Here, the I and Q symbol streams VI (8), V
The averaging is performed on Q (8) so that the signal point arrangement can be stably obtained even when a small phase change or amplitude change of the received baseband signal occurs due to deterioration of the received C / N. To do that.

The reception signal point [A of the signal in which the bit (1) is BPSK mapped by the averaging circuits 84 and 85 [A
VI (8), AVQ (8)]. Next, the received signal points [AVI (8), AVQ (8)] are input to a phase determination circuit 87 composed of a ROM, and the AVI shown in FIG.
The received signal phase rotation angle Θ is obtained according to the received signal phase rotation angle determination table on the AVQ phase plane, and the 3-bit (natural binary number) phase rotation angle signal AR corresponding to Θ is obtained.
(3) is output. R = 0 to 7 in FIG. 27 indicate the decimal number display of the phase rotation angle signal AR (3). For example, the point Z = [AVI (8), AVQ shown in FIG.
(8)], the received signal phase rotation angle determined by the received signal phase rotation angle determination table is Θ = 0. Therefore, R = 0, and the received signal phase rotation angle signal AR
(000) is transmitted as (3). If the received signal phase rotation angle π is π / 4, R = 1, and (001) is transmitted as the received signal phase rotation angle signal AR (3).

The remapper 7 comprising a ROM receives the received signal phase rotation angle signal AR (3) and converts the I and Q baseband signals I (8) and Q (8) to the received signal phase rotation angle signal A (3).
By rotating the phase according to R (3), absolute phase conversion is achieved. The operation of the remapper 7 will be described. The remapper 7 receives the I and Q baseband signals I (8), Q
A phase conversion circuit is configured to make the signal point arrangement of (8) the same as that on the transmission side. The reception signal phase rotation angle detection circuit 8 calculates the reception signal phase rotation angle Θ, and supplies the reception signal phase rotation angle signal AR (3) corresponding to the reception signal phase rotation angle に to the remapper 7. here,
The decimal representation R of the received signal phase rotation angle signal AR (3) is 0.
And the relationship with the received signal phase rotation angle Θ is
It is defined as shown in the following equation (1).

R = Θ / (π / 4) (1) where Θ = m · (π / 4), and m is an integer of 0 to 7. For the absolute phase conversion of the I and Q baseband signals, the received signal phase rotation angle? Therefore, the remapper 7 rotates the phase of the input I and Q baseband signals I and Q by the angle η (= −Θ) according to the following equations (2) and (3), and sets the absolute phase I , Q baseband signal I ′
(8), Q '(8) (hereinafter the quantization bit number is omitted and I
'And Q'). I ′ = Icos (η) −Qsin (η) (2) Q ′ = Isin (η) + Qcos (η) (3) Note that the frame synchronization signal is captured by the frame synchronization detection / reproduction circuit 2. After the frame sync pulse is output,
The transmission configuration identification circuit 9 identifies the transmission configuration first, and then the reception signal phase rotation angle detection circuit 8 may detect the reception signal phase rotation angle, and conversely, the reception signal phase rotation angle first. The detection circuit 8 detects the received signal phase rotation angle, and thereafter, the transmission configuration identification circuit 9 may identify the transmission configuration, and further, the received signal phase rotation angle detection circuit 8 detects the received signal phase rotation angle. The detection and the identification of the transmission configuration by the transmission configuration identification circuit 9 can be performed simultaneously and in parallel.

[0049]

However, in the above-mentioned conventional receiver, in order to correct the phases of the reference carriers f _C1 and f _C2 during demodulation of the QPSK modulation method, the phase error tables 14-1 and 14- are required. 2 must be prepared, and the reference carriers f _C1 and f _C1 are demodulated during the demodulation of the BPSK modulation method.
To correct the phase of _C2 , the phase error table 15-
There is a problem that the required memory capacity becomes large-scale because three of 1 to 15-3 must be prepared. An object of the present invention is to provide a receiver that requires a small circuit scale.

[0050]

SUMMARY OF THE INVENTION In a receiver according to the present invention, a PSK modulated signal in which digital signals modulated by a plurality of types of PSK modulation systems having different phases are time-multiplexed is reproduced by a carrier wave reproducing means. Demodulate using the carrier, I,
Demodulation means for outputting Q symbol stream data, I signal output from the demodulation means, reception signal phase rotation angle detection means for detecting a phase rotation angle of the Q symbol stream data with respect to the transmitting side, and I, An anti-phase rotation means for rotating the phase of the Q symbol stream data by an amount corresponding to the phase rotation angle detected by the reception signal phase rotation angle detection means, and outputting the result. Separately, a phase error table storing carrier phase error data for various demodulated I and Q symbol stream data sets is provided, and while the demodulation means is demodulating a certain modulation scheme portion, the phase of the corresponding modulation scheme is demodulated. The phase error data corresponding to the demodulated I and Q symbol stream data is read from the error table, and the phase of the carrier is corrected. In the receiver, while the demodulation means is demodulating a certain modulation scheme part of the received signal, the carrier recovery means uses the phase error table of the corresponding modulation scheme, and outputs the demodulated I, Reading out phase error data corresponding to the Q symbol stream data,
It is characterized in that the phase of the carrier is corrected.

From the phase error table of the carrier recovery means, the phase error data corresponding to the I and Q symbol stream data after the absolute phase conversion by the anti-phase rotation means is read out. regardless of,
The reception signal points of the I and Q symbol stream data input to the phase error table are the same as those on the transmission side. Therefore, only one phase error table is provided for the carrier recovery means for each modulation method, and the number of phase error tables provided for the carrier recovery means can be reduced, and the circuit configuration can be greatly simplified.

[0052]

Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a main part of a broadcast receiver (PSK modulated wave receiver) according to the present invention. The same components as those in FIG. 10 are denoted by the same reference numerals. In FIG. 10, the phase error table 1 is added to the carrier recovery circuit.
3, 14-1, 14-2, 15-1 to 15-4, and input the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit. However, in FIG. 1, the phase error tables 13, 14-
1, 15-1 and the I and Q symbol stream data I output from the remapper 7.
'(8) and Q' (8). The remapper 7 performs phase rotation on the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit until the reception signal phase rotation angle detection circuit detects the phase rotation angle. Instead, the input data is output as it is.

Selector 16C of carrier recovery circuit 10C
After the start of reception, the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8C
Until the symbol clock CLK _SYB rises (CLK
H level section of _SYB . 9 (2)), only the 8PSK phase error table 13 (see FIG. 15) is enabled, and from the phase error table 13, I output from the remapper 7 while the symbol clock CLK _SYB rises. , Q symbol stream data I ′
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read out and output to the D / A converter 17. Also,
In parallel with this, while the symbol clock CLK _SYB is falling (the L level section of CLK _SYB ; FIG. 9 (2)
BPSK phase error table 15-1 (see FIG. 1).
8) and only the phase error table 1
From 5-1, the phase error data Δφ (8) corresponding to the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 while the symbol clock CLK _SYB falls. Among them, the upper three bits (which will be referred to as phase error data Δφ (3)) are read and output to the received signal phase rotation angle detection circuit 8C. From the phase error data Δφ (3), the absolute value of the phase error is (π / 8) +
It can be determined whether it is larger or smaller than s · (π / 8) (s is 0, 1, 2).

After the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8C detects the reception signal phase rotation angle (Θ), the selector 16C outputs the symbol clock CLK _SYB. Is rising, the phase error table 13 or 14-1 or 15 according to the modulation method of the received signal demodulated by the demodulation circuit 1C.
-1 is enabled, and I and Q symbol stream data I 'output from the remapper 7 while the symbol clock CLK _SYB rises.
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read out and output to the D / A converter 17, while the symbol clock CLK _SYB falls while BP
From the SK phase error table 15-1, the I and Q symbol stream data I 'output from the remapper 7 while the symbol clock CLK _SYB falls.
(8), phase error data Δφ corresponding to Q ′ (8)
Out of (8), upper three bits of phase error data Δφ (3)
Read out.

Reference numeral 90 denotes a delay circuit, and the selector 16
The phase error data Δφ (3) read by C is output after a predetermined time delay. The delay circuit 90 captures the frame synchronization signal from the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 by the frame synchronization detection / reproduction circuit 2 and Is started, the phase error data Δφ corresponding to the first part of the frame synchronization signal out of the I and Q symbol stream data I ′ (8) and Q ′ (8).
(3) is output. Reference numeral 91 denotes a delay circuit, which is the MSB of the Q symbol stream data Q '(8).
Is output after a predetermined time delay of the sign bit data q ′ (1). In the delay circuit 91, the frame synchronization detecting / reproducing circuit 2 outputs the I and Q symbol stream data I '.
(8) When the frame synchronization signal is captured from Q '(8) and the output of the first part of the reproduced frame synchronization signal is started, the frame synchronization signal of the Q symbol stream data Q' (8) is just The code bit data q '(1) of the first part is output.

Reference numeral 92 denotes a phase rotation angle discriminating circuit, which outputs I and Q symbol streams I '(8), Q output from the remapper 7 from a portion corresponding to the frame synchronization signal in the outputs of the delay circuits 90 and 91. In (8), the phase rotation angle with respect to the transmitting side is determined for the symbol portion corresponding to bit (1) of the frame synchronization signal, and the symbol portion corresponding to bit (0) of the frame synchronization signal is determined for the transmitting side. The phase rotation angle is determined, and the determination result is sequentially output. In the phase rotation angle discriminating circuit 92, reference numeral 93 denotes a 4-bit adder for adding 4-bit data (however, the carry to the fifth bit is not carried out). , And the output of the delay circuit 90 is input to the lower three bits. A selector 94 is connected to the other input side of the adder 93, and the selector 94 is connected to the frame synchronization detection / reproduction circuit 2.
, A bit stream of a reproduction frame synchronization signal output from
(4) = (0001) is output, and when the bit (1) is input, B (4) = (1001) is output.
Adder 93 outputs the upper 3 bits of the addition result as received signal phase rotation angle signal R (3).

Reference numeral 95 denotes an averaging circuit for averaging the received signal phase rotation angle signal R (3). Here, as an example, the frame synchronization signal is averaged over four frames to obtain the received signal phase rotation angle signal AR (3). ). A specific example of the averaging circuit 95 will be described later. 110 is an averaging circuit 95
Outputs the received signal phase rotation angle signal AR (3),
The previous received signal phase rotation angle signal OR (3) held in the register 111 and the current received signal phase rotation angle signal AR
(3) is a 3-bit adder that adds the result and outputs the result as a new received signal phase rotation angle signal OR (3) to the remapper 7 and the like (however, the carry to the fourth bit is not performed). Reference numeral 111 denotes a register for holding the received signal phase rotation angle signal OR (3) output from the adder 110. The functions of the adder 110 and the register 111 will be described later. The other components are configured exactly the same as in FIG.

Next, the operation of the above embodiment will be described. It is assumed that the register 111 has been cleared to (000) in advance. (1) Start of reception At the start of reception, the remapper 7 does not rotate the phase, and the demodulation circuit 1
I and Q symbol streams I (8), Q input from C
(8) is directly output as I '(8) and Q' (8). The selector 16C of the carrier recovery circuit 10C keeps the symbol until the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame after the start of reception and the reception signal phase rotation angle detection circuit 8C detects the reception signal phase rotation angle. Clock CLK
_{During the} rise of _SYB, only the phase error table 13 for 8PSK is enabled, and the phase error table 1
3, phase error data Δφ (8) corresponding to the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 while the symbol clock CLK _SYB rises, Output to the D / A converter 17. In parallel with this, the symbol clock C
While the LK _SYB is falling, only the phase error table 15-1 for BPSK is enabled. From the phase error table 15-1, the I output from the remapper 7 while the symbol clock CLK _SYB is falling. , Q
Among the phase error data Δφ (8) corresponding to the symbol stream data I ′ (8) and Q ′ (8), the phase error data Δφ (3) of the upper three bits is read out, and the delay circuit 9
Output to 0.

The selector 16C reads out the phase error data Δφ (8) from the phase error table 13 for 8PSK,
When output to the D / A converter 17, the signal is converted into a phase error voltage by the D / A converter 17, and a low-frequency component is extracted by the LPF 18 and applied to the VCO 11 as a control voltage.
If the phase error data Δφ (8) is 0, the output of the LPF 18 does not change and the phases of the reference carriers f _C1 and _{fc 2} do not change, but if the phase error data Δφ (8) is +, the LPF
18 output is increased, the reference carrier wave f _C1, f phase _c2 is delayed, conversely, the phase error data [Delta] [phi (8) is - output if LPF18 is reduced, the reference carrier wave f _C1, f _c2
Advances in phase. Thereby, the phases of the reference carriers f _C1 and f _c2 are corrected so as to maintain a fixed relationship with the phase of the received carrier. As a result, the demodulation circuit 1C outputs the phase 0,
π / 4, 2π / 4, 3π / 4, 4π / 4, 5π / 4, 6
The digital signals of the signal point arrangement “0” to “7” of π / 4 and 7π / 4 are respectively converted into Θ = mx on the IQ phase plane on the receiving side.
The position is corrected to a position rotated by π / 4 (where m is an arbitrary integer from 0 to 7).

On the other hand, in the phase error table 15-1, I and Q symbol stream data I '(8), Q'
Upper 3 bits Δ of phase error data Δφ corresponding to (8)
φ (3) indicates that the absolute value of the phase error is (π / 8) + s ·
(Π / 8) (s is 0, 1, 2) is the number of bits to determine whether it is larger or smaller (see FIG. 18). Combining this Δφ (3) and the sign bit data q ′ (1) which is the MSB of the Q symbol stream data Q ′ (8), and performing a simple arithmetic processing, the received signal point seen on the output side of the remapper 7 becomes It can be determined which of the eight signal point arrangements “0” to “7” corresponds. The transmission-side signal point arrangement of the bit (0) (or bit (1)) portion of the frame synchronization signal is “0”.
(Or “4”), the received signal viewed on the output side of the remapper 7 is obtained from the phase error data Δφ (3) and the sign bit data q ′ (1) of the Q symbol stream data Q ′ (8). The phase rotation angle is uniquely determined.

In the reception signal phase rotation angle detection circuit 8C, first, the delay circuits 90 and 91 output the phase error data Δφ (3) output from the selector 16C and the remapper 7
Q symbol stream data Q 'extracted from the output of
The code bit data q ′ (1) of (8) is delayed, and the frame synchronization detection / reproduction circuit 2 captures a frame synchronization signal from the I and Q symbol stream data I ′ (8) and Q ′ (8), When the output of the playback frame synchronization signal starts,
The delay circuit 90 outputs the phase error data Δφ (3) corresponding to the head of the frame synchronization signal portion of the I and Q symbol stream data I ′ (8) and Q ′ (8). The timing is adjusted so that the code bit data q '(1) corresponding to the head of the frame synchronization signal portion of the symbol stream data Q' (8) is output. Outputs of the delay circuits 91 and 90 are input as upper bits and lower bits on one input side of the adder 93.

After a short time after the start of reception, the frame synchronization detection / reproduction circuit 2 sets the I and Q symbol streams I '(8),
The frame synchronization signal of Q '(8) is captured, and a reproduced frame synchronization signal is output. Then, the selector 94 determines that A (4) = A (4) = bit (0) of the reproduced frame synchronization signal.
(0001) is selected and output, and in the bit (1) portion, B (4) = (1001) is selected and output. The adder 93 performs an addition operation of one input and the other input at each bit position of the 20-bit reproduced frame synchronization signal,
Outputs the upper 3 bits. Then, from the adder 93,
FIG. 2 shows the received signal phase rotation angle た viewed from the output side of the remapper 7.
As shown in (1), 0, π / 4, 2π / 4, 3π / 4,
4π / 4, 5π / 4, 6π / 4, 7π / 4
The received signal phase rotation angle signal R (3) in which R is represented by a 3-bit natural binary number in association with R = 0 to 7 in hexadecimal notation is output (see FIG. 2 (2)).

The averaging circuit 95 takes in the output of the adder 93 while the frame synchronization signal section signal is being input from the frame synchronization detection / reproduction circuit 2 and averages it over four frames. The result is the received signal phase rotation angle. Output as signal AR (3). The averaging of the received signal phase rotation angle signal R (3) is performed stably even when a small phase change or amplitude change of the received baseband signal occurs due to deterioration of the received C / N. This is for obtaining the phase rotation angle.

FIG. 3 shows an example of the averaging circuit 95. Received signal phase rotation angle signal R (3) output from adder 93
Is converted into a 3-bit Gray code by a Gray code converter 96 in accordance with FIG. Gray codes have the property that only one bit position changes between adjacent codes. The output of the Gray code converter 96 has a bit position G
The majority decision circuits 97-1 to 97-3 are provided separately for 0 to G2, and while the frame synchronization signal section signal over four frames is being input, the bits (1) and (0) are output from the gray code converter 96. Are determined to be output more. Outputs F0 to F of majority decision circuits 97-1 to 97-3
2 is input to a binary code converter 98, and conversion reverse to that of the Gray code converter 96 is performed according to FIG. The output of the binary code converter 98 is output as the received signal phase rotation angle signal AR (3).

It is also possible to omit the gray code converter 96 and the binary code converter 98 and directly input the output of the adder 93 to the majority decision circuits 97-1 to 97-3 to make a majority decision. . However, once the Gray encoding is performed, even if the phase indicated by the received signal phase rotation angle signal R (3) changes by π / 4, the code always changes only in one bit position, and the received C / N deteriorates. Causes a small phase change and amplitude change of the received baseband signal, and erroneously shifts the received signal phase rotation angle signal R (3) by π / 4, the effect can be minimized, and the reliability is improved. Increase.

The received signal phase rotation angle signal AR (3) output from the averaging circuit 95 is added to the register 11 by the adder 110.
It is added to the holding value of 1, but initially the holding value is (000)
Therefore, the received signal phase rotation angle signal OR (3) for the transmitting side when AR (3) is viewed as it is at the output point of the demodulation circuit 1C.
To the remapper 7 and to the register 111 for holding. Here, as an example, if the received signal phase rotation angle 示 す indicated by OR (3) is 3π / 4, the remapper 7 performs phase rotation by (−3π / 4) to perform absoluteization. The register 111 holds (011).

(2) Normal Receiving Operation As soon as the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal, the transmission configuration identification circuit 9 identifies the multiplex configuration and the current I and Q output from the demodulation circuit 1C. A modulation scheme identification signal DM indicating which modulation scheme part the symbol streams I (8) and Q (8) are output to the selector 16C and the like.

When the received signal phase rotation angle signal OR (3) is output from the adder 110 and the absolute phase is converted by the remapper 7, the selector 16C outputs the modulation scheme identification signal DM input from the transmission configuration identification circuit 9 to the selector 16C. Using demodulation circuit 1
While C is demodulating the 8PSK modulation scheme,
While the symbol clock CLK _SYB rises, only the phase error table 13 is enabled. From the phase error table 13, the I and Q symbol stream data I '(8) and Q' (8) output from the remapper 7 are output. The corresponding phase error data Δφ (8) is read and output to the D / A converter 17. As a result, I ′ (8) and Q ′ (8) become I (8) and Q ′ regardless of the phase variation of the received carrier.
Considering that the phase is rotated by η = −Θ = −3π / 4 compared to (8), the signal point arrangement “0” on the transmission side,
"1", "2", "3", "4", "5", "6",
The digital signal (a
The signal point arrangements “3”, “4”,.
The phases of the reference carriers f _C1 and f _C2 are corrected so as to appear in “5”, “6”, “7”, “0”, “1”, and “2”.
At this time, the I and Q symbol stream data I (8), Q of the 8PSK modulation scheme output from the demodulation circuit 1C.
(8) is phase-rotated by η = −Θ = −3π / 4 by the remapper 7 and converted into an absolute phase.
I and Q symbol stream data I ′ output from
(8), the reception signal point of Q '(8) matches the transmission side.

During the period when the demodulation circuit 1C is performing demodulation of the QPSK modulation scheme, the selector 16C enables only the phase error table 14-1 while the symbol clock CLK _SYB is rising, and the phase error table 14 −1, I, Q symbol stream data I ′
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read and output to the D / A converter 17. As a result, I '(8) and Q' (8) become I (8) and Q (8).
Considering that the phase is rotated by η = −Θ = −3π / 4 as compared with the signal point arrangement “1”, “3”,
Digital signals (de) QPSK mapped to “5” and “7” appear at signal point arrangements “4”, “6”, “0”, and “2”, respectively, as viewed at the input side of remapper 7. Since the phases of the reference carriers f _C1 and f _C2 are corrected, 8PS
K is maintained at the same phase rotation angle as the reception signal phase rotation angle Θ. I and Q symbol stream data I (8), Q of the QPSK modulation scheme portion output from demodulation circuit 1C
Since (8) is rotated by −Θ = −3π / 4 by the remapper 7, the received signal points of the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 are Match with sender.

During the period in which the demodulation circuit 1C is performing demodulation of the BPSK modulation scheme, only the phase error table 15-1 is enabled while the symbol clock CLK _SYB rises.
I, Q symbol stream data I '(8), Q'
The phase error data Δφ (8) corresponding to (8) is read and output to the D / A converter 17. Thereby, I ′
(8), Q '(8) is -Θ compared to I (8), Q (8).
Considering that the phase is rotated by −3π / 4, the digital signal (f) BPSK-mapped to the signal point constellations “0” and “4” on the transmission side respectively has the signal point constellation “ 3 ”, as shown in“ 7 ”, the reference carrier f _C1 ,
Since the phase of f _C2 is corrected, it is maintained at the same phase rotation angle as the reception signal phase rotation angle ８ at 8PSK. Demodulation circuit 1
The I and Q symbol stream data I (8) and Q (8) of the BPSK modulation scheme output from C are remapper 7
Is rotated by η = −Θ = −3π / 4.
The reception signal points of the I and Q symbol stream data I '(8) and Q' (8) output from the remapper 7 coincide with the transmission side.

Note that the selector 16C also operates during the normal reception operation.
While the symbol clock CLK _SYB is falling
Only the phase error table 15-1 is enabled, and the symbol clock CLK
I and Q symbol stream data I (8) ', Q (8) output from remapper 7 while _SYB is falling
'And reads out the phase error data Δφ (3) corresponding to'. Then, the phase rotation angle determination circuit 92 determines the phase rotation angle based on the outputs of the delay circuits 90 and 91, and outputs the determination result as the received signal phase rotation angle signal R.
The signal is output in the form of (3), and the averaging circuit 95 averages the data for four frames, and outputs the result as the received signal phase rotation angle signal AR (3).

When the phase rotation angle determination circuit 92 and the averaging circuit 95 of the reception signal phase rotation angle detection circuit 8C detect the second phase rotation angle and output the reception signal phase rotation angle signal AR (3), The received signal phase rotation angle signal AR (3) indicates the phase rotation angle with respect to the transmission side as seen from I '(8) and Q' (8) after the absolute phase conversion by the remapper 7. Therefore, the previous received signal phase rotation angle signal O held in the register 111
By adding the received signal phase rotation angle signal OR (3) to the transmission side as viewed from the input side of the remapper 7 by adding the signal R (3), the reception signal phase rotation angle signal OR (3) is output to the remapper 7. And perform the second phase rotation (OR (3)
Let the phase rotation angle of the received signal indicated by Θ be Θ, rotate the phase by −Θ), and store it in the register 110. Hereinafter, the same processing is repeated each time the phase rotation angle determination circuit 92 and the averaging circuit 95 of the reception signal phase rotation angle detection circuit 8C detect a new phase rotation angle.

According to this embodiment, the I and Q symbol stream data I '(8), Q' after the absolute phase conversion by the remapper 7 are stored in the phase error table of the carrier recovery circuit 10C.
Since (8) is input, during normal reception, regardless of the value of the received signal phase rotation angle, the I and Q symbol stream data I 'input to the phase error table are output.
(8), the reception signal point of Q '(8) becomes the same as the transmission side. Therefore, only one phase error table is provided for the carrier recovery circuit 10C for each modulation method, and the number of phase error tables provided for the carrier recovery circuit 10C can be reduced, and the circuit configuration can be greatly simplified.

The phase error data in the phase error table for the BPSK modulation corresponding to the I and Q symbol stream data corresponding to bits (1) (bit (0)) of the demodulated frame synchronization signal, The absolute value of the phase error is (π / 8) + s · (π / 8) (s is 0, 1, 2)
The upper three bits that are known to be larger or smaller, and the sign bit data q ′ of the Q symbol stream data Q ′ (8)
From (1), the phase rotation angles of the I and Q symbol stream data I (8) and Q (8) corresponding to bit (1) (bit (0)) of the frame synchronization signal are determined. Therefore, the phase rotation angle of the received signal can be determined by a simple calculation. Therefore, a large-scale R dedicated for determining the phase rotation angle is used.
It is not necessary to use the OM, and the circuit scale can be reduced.

In the above-described embodiment, the code bit data q ′ of the Q symbol stream data Q ′ (8)
Although (1) is used, code bit data which is the MSB of the I symbol stream data I ′ (8) may be used instead. This change can be made simply by appropriately changing the values of A (4) and B (4) selected by the selector 94. Further, although the phase rotation angles are determined for both the bit (1) and the bit (0) of the frame synchronization signal portion of the I and Q symbol stream data, only one of them may be performed. The averaging method in the averaging circuit 95 can be changed in various ways. For example, averaging may be performed for one frame or two frames, or one or more bits at a specific position of the frame synchronization signal may be changed. Averaging may be performed over a plurality of frames.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 shows a broadcast receiver (P
FIG. 1 is a block diagram of a main part of an SK modulated wave receiver).
The same components as those described above are denoted by the same reference numerals. In the embodiment shown in FIG. 1, a phase error table 1 for BPSK is used.
The phase error data Δφ (3) is read from 5-1. However, in FIG. 5, the phase error table 14-
1 (see FIG. 16), the phase error data Δφ (3) is read. After the start of reception, the selector 16D of the carrier recovery circuit 10D keeps the symbol until the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8D detects the reception signal phase rotation angle. 8PSK while the clock CLK _SYB is rising
Only the phase error table 13 for
From the phase error table 13 for PSK, the I and Q symbol stream data I '(8) output from the remapper 7 while the symbol clock CLK _SYB is rising,
The phase error data Δφ (8) corresponding to Q ′ (8) is read and output to the D / A converter 17. In parallel with this, while the symbol clock CLK _SYB falls, only the phase error table 14-1 for QPSK is enabled, and from the phase error table 14-1, the symbol clock CLK _SYB falls. While the I and Q symbol stream data I 'output from the remapper 7
(8), phase error data Δφ corresponding to Q ′ (8)
Out of (8), upper three bits of phase error data Δφ (3)
Read out. From the phase error data Δφ (3), it can be determined whether the absolute value of the phase error is larger or smaller than π / 8.

After the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8D detects the reception signal phase rotation angle Θ, the selector 16D
While the symbol clock CLK _SYB is rising, the I and Q symbol stream data I '(8), Q' (8 ) _Is read out and output to the D / A converter 17, while the QPSK phase error table 14-1 is output while the symbol clock CLK _SYB falls.
I, Q symbol stream data I '(8), Q'
The phase error data Δφ (3) corresponding to (8) is read.

Reference numeral 90 denotes a delay circuit,
D outputs the phase error data Δφ (3) read out with a predetermined time delay. In the delay circuit 90, the frame synchronization detection / reproduction circuit 2 uses the I and Q symbol stream data I '.
(8) When the frame synchronization signal is captured from Q '(8) and the output of the first part of the reproduced frame synchronization signal is started, the I and Q symbol stream data I'
(8) The phase error data Δφ (3) corresponding to the first part of the frame synchronization signal of Q ′ (8) is output. Reference numeral 91 denotes a delay circuit, which is sign bit data q 'which is the MSB of the Q symbol stream Q' (8).
(1) is output after a predetermined time delay. Delay circuit 91
When the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal from the I and Q symbol stream data I '(8) and Q' (8) and starts outputting the first part of the reproduction frame synchronization signal, Just the code bit data q '(1) of the first part of the frame synchronization signal in the Q symbol stream data Q' (8) is output.

Reference numeral 99 denotes a delay circuit which outputs the sign bit data i ′ (1), which is the MSB of the I symbol stream data I ′ (8), with a predetermined delay. In the delay circuit 99, the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal from the I and Q symbol stream data I '(8) and Q' (8), and starts outputting the first part of the reproduction frame synchronization signal. At this time, the code bit data i '(1) of the first part of the frame synchronization signal in the I symbol stream data I' (8) is output.

Reference numeral 92B denotes a phase rotation angle discriminating circuit, which outputs I and Q symbol streams I '(8), Q' output from the remapper 7 from a portion corresponding to the frame synchronization signal output from the delay circuits 90, 91 and 99. In (8), the phase rotation angle with respect to the transmitting side is determined for the symbol portion corresponding to bit (1) of the frame synchronization signal, and the symbol portion corresponding to bit (0) of the frame synchronization signal is determined for the transmitting side. The phase rotation angle is determined, and the determination result is sequentially output. In the phase rotation angle discriminating circuit 92B, reference numeral 100 denotes a 3-bit adder for adding 3-bit data (however, the carry to the 4th bit is not carried out), and the output of the delay circuit 90 and C (3) = ( 110) and outputs the lower 2 bits.

A binary converter 101 converts a 2-bit output obtained by combining the output of the delay circuit 91 as upper bits and the output of the delay circuit 99 as lower bits into a binary code according to FIG. 6 and outputs the binary code. Reference numeral 102 denotes a 4-bit adder that adds 4-bit data (however, 5
The carry of the binary converter 101 is input to the upper two bits on one input side, and the lower two bits of the addition result of the adder 100 are input to the lower two bits. A selector 103 is connected to the other input side of the adder 102. The selector 103 inputs a bit stream of a reproduced frame synchronization signal output from the frame synchronization detection / reproduction circuit 2, and outputs a bit (0).
Is output, D (4) = (0001) is output, and when the bit (1) is input, E (4) is output.
= (1001) is output. Adder 102 outputs the upper 3 bits of the addition result as received signal phase rotation angle signal R (3).

Reference numeral 95 denotes an averaging circuit for averaging the received signal phase rotation angle signal R (3). Here, as an example, the frame synchronization signal is averaged over four frames to obtain the received signal phase rotation angle signal AR (3). ). 110
Means that the averaging circuit 95 sets the received signal phase rotation angle signal AR (3)
Is output, the previous received signal phase rotation angle signal OR (3) held in the register 111 is added to the current received signal phase rotation angle signal AR (3), and the result is added to the new received signal phase rotation angle. This is a 3-bit adder that outputs the signal OR (3) to the remapper 7 and the like (however, the carry to the fourth bit is not performed). Reference numeral 111 denotes a register for holding the received signal phase rotation angle signal OR (3) output from the adder 110. The other components are configured exactly the same as in FIG.

Next, the operation of the above embodiment will be described. It is assumed that the register 111 has been cleared to (000) in advance. (1) Start of reception At the start of reception, the remapper 7 does not rotate the phase, and the demodulation circuit 1
I and Q symbol streams I (8) and Q input from D
(8) is directly output as I '(8) and Q' (8). After the start of reception, the selector 16D of the carrier recovery circuit 10D keeps the symbol until the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8D detects the reception signal phase rotation angle. Clock CLK
_{During the} rise of _SYB, only the phase error table 13 for 8PSK is enabled, and the phase error table 1
3, the phase error data Δφ (8) corresponding to the set data of the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 while the symbol clock CLK _SYB rises. Read D / A converter 1
7 is output. In parallel with this, while the symbol clock CLK _SYB falls, only the phase error table 14-1 for QPSK is enabled, and the symbol clock CLK _{SYB is output} from the phase error table 14-1.
I output from the remapper 7 while falling,
Among the phase error data Δφ (8) corresponding to the set data of the Q symbol stream data I ′ (8) and Q ′ (8), the phase error data Δφ (3) of the upper 3 bits is read and output to the delay circuit 90 I do.

The selector 16D reads out the phase error data Δφ (8) from the phase error table 13 for 8PSK.
Output to the A / A converter 17, the demodulation circuit 1D
Are the phases 0, π / 4, 2π / 4, 3π / 4 on the transmitting side,
4π / 4, 5π / 4, 6π / 4, 7π / 4 signal point arrangement “0” to “7” digital signals are respectively demodulated by demodulation circuit 1
Θ = m × π on the receiving-side IQ phase plane viewed at the output point of D
The position is corrected to a position rotated by / 4 (where m is an arbitrary integer from 0 to 7).

On the other hand, in the phase error table 14-1, the I and Q symbol stream data I '(8), Q'
The upper three bits Δφ (3) of the phase error data Δφ (8) corresponding to (8) are the number of bits for determining whether the absolute value of the phase error is larger or smaller than π / 8 (see FIG. 16).
This Δφ (3) and I, Q symbol stream data I ′
(8), sign bit data i which is the MSB of Q '(8)
By combining '(1) and q' (1) and performing simple arithmetic processing, the received signal points viewed on the output side of the remapper 7 correspond to any of the eight signal point arrangements “0” to “7”. Can be determined. Since the signal point constellation on the transmitting side of bit (0) (or bit (1)) of the frame synchronization signal is determined to be “0” (or “4”), Δφ (3) and the I and Q symbol streams From the sign bit data i '(1) and q' (1) of the data I '(8) and Q' (8), the received signal phase rotation angle is uniquely obtained.

In the reception signal phase rotation angle detection circuit 8D, first, the delay circuits 90, 91 and 99 select the selector 1
ΔD (3) output from 6D and sign bit data q ′ (1), i ′ (1) extracted from the output of remapper 7
When the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal from the I and Q symbol stream data and starts outputting the reproduction frame synchronization signal, the delay circuit 90 outputs the I and Q symbol stream data I ′.
(8) The phase error data Δφ (3) corresponding to the head of the frame synchronization signal portion of Q ′ (8) is output, and the delay circuit 91 outputs the frame synchronization signal of Q symbol stream data Q ′ (8). The code bit data q '(1) corresponding to the head of the portion is output, and the I symbol stream data I'
The timing is adjusted so that the code bit data i '(1) corresponding to the head of the frame synchronization signal portion of (8) is output. After the outputs of the delay circuits 91 and 99 are subjected to binary conversion, they are input as upper bits of one input of the adder 102. After the output of the delay circuit 90 is added to C (3) = (110) by the adder 100, the lower 2 bits are input as the lower 2 bits of one input of the adder 102.

After a short time from the start of reception, the frame synchronization detecting / reproducing circuit 2 sets the I and Q symbol streams I '(8),
The frame synchronization signal of Q '(8) is captured, and a reproduced frame synchronization signal is output. Then, the selector 103 sets D (4) in the bit (0) portion of the reproduction frame synchronization signal.
= (0001) is selected and output, and at the bit (1) portion, E (4) = (1001) is selected and output. The adder 102 performs an addition operation on one input and the other input at each bit position of the 20-bit reproduced frame synchronization signal, and outputs the upper 3 bits. Then, the adder 102 outputs the received signal phase rotation angle Θ as shown in FIG.
0, π / 4, 2π / 4, 3π / 4, 4π / 4, 5π /
Divided into 4, 6π / 4 and 7π / 4, R = 0 in decimal notation
7, a received signal phase rotation angle signal R (3) expressing R as a 3-bit natural binary number is output (FIG. 2).
(See (2)).

The averaging circuit 95 takes in the output of the adder 102 while the frame synchronization signal section signal is being input from the frame synchronization detection / reproduction circuit 2 and averages it over four frames in the same manner as in FIG. , And outputs the result as a reception signal phase rotation angle signal AR (3). AR (3) is added to the value held in the register 111 by the adder 110.
Initially, the held value is (000), so that AR (3) is output to the remapper 7 as the received signal phase rotation angle signal OR (3) for the transmitting side as seen at the output point of the demodulation circuit 1D, and the register 111 And hold it. As an example, the received signal phase rotation angle ＯＲ indicated by OR (3) is 2π / 4.
If so, the remapper 7 rotates the phase by (-2π / 4) to perform absoluteization. The register 111 stores (01
0) is retained.

(2) Normal Receiving Operation As soon as the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal, the transmission configuration identification circuit 9 identifies the multiplex configuration and the current I, Q output from the demodulation circuit 1D. A modulation scheme identification signal DM indicating which modulation scheme part the symbol streams I (8) and Q (8) is output to the selector 16D and the like.

After the received signal phase rotation angle signal OR (3) is output from the adder 110 and the absolute phase is converted by the remapper 7, the selector 16D uses the modulation scheme identification signal DM input from the transmission configuration identification circuit 9. And, for example, OR
When the received signal phase rotation angle の shown in (3) is 2π / 4,
During the period in which the demodulation circuit 10D is demodulating the 8PSK modulation scheme, only the phase error table 13 is enabled while the symbol clock CLK _SYB rises. The phase error data Δφ (8) corresponding to '(8) and Q' (8) is read and output to the D / A converter 17. As a result, I ′ (8) and Q ′ (8)
(8), considering that it is rotated by η = −2π / 4 compared to Q (8), signal point arrangement “0”, “1”, “2”,
Digital signal (abc) 8PSK mapped to “3”, “4”, “5”, “6”, and “7” is a signal point arrangement that is rotated by Θ when viewed at the input side of the remapper 7. "2", "3", "4", "5", "6", "7",
The phases of the reference carriers f _C1 and f _C2 are corrected so as to appear in “0” and “1”. At this time, the I and Q symbol stream data I (8) and Q (8) of the 8PSK modulation scheme output from the demodulation circuit 1D are converted by the remapper 7 into η = −
Since the phase is rotated by Θ = −2π / 4 to be an absolute phase, the reception signal points of the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 coincide with the transmission side. I do.

During the period when the demodulation circuit 1D is performing the demodulation of the QPSK modulation scheme, only the phase error table 14-1 is enabled while the symbol clock CLK _SYB rises.
I, Q symbol stream data I '(8), Q'
The phase error data Δφ (8) corresponding to (8) is read and output to the D / A converter 17. Thereby, I ′
(8), Q ′ (8) is η = η compared to I (8), Q (8).
Considering that the signal is rotated by −2π / 4, QPSK is added to the signal point constellations “1”, “3”, “5”, and “7” on the transmitting side.
The mapped digital signals (abc) are:
When viewed on the input side of the remapper 7, the phases of the reference carriers f _C1 and f _C2 are corrected so that they appear in the signal point arrangements “3”, “5”, “7”, and “1” that are rotated by Θ in phase. , 8PSK
At the same phase rotation angle as the reception signal phase rotation angle Θ. I and Q symbol stream data I (8), Q (8) of the QPSK modulation scheme portion output from demodulation circuit 1D
Is also rotated by η = −Θ = −2π / 4 by the remapper 7, so that the received signal points of the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 are transmitted. Match side.

During the period in which the demodulation circuit 1D is performing demodulation of the BPSK modulation method, the selector 16D enables only the phase error table 15-1 while the symbol clock CLK _SYB is rising, and the phase error table 15- 1 to I, Q symbol stream data I '
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read and output to the D / A converter 17. As a result, I '(8) and Q' (8) become I (8) and Q (8).
Considering that the digital signal (f) is rotated by η = −2π / 4, the digital signal (f) BPSK-mapped to the signal point constellations “0” and “4” on the transmitting side is Since the phases of the reference carriers f _C1 and f _C2 are corrected so as to appear in the signal point arrangements “2” and “6”, the phase rotation angle is maintained at the same as the received signal phase rotation angle ８ at 8PSK. I and Q of the BPSK modulation scheme output from the demodulation circuit 1D
Since the symbol stream data I (8) and Q (8) are also rotated by η = −Θ = −2π / 4 by the remapper 7, the I and Q symbol stream data I ′ (8) output from the remapper 7 are output. , Q ′ (8) coincide with the transmitting side.

It should be noted that also during the normal reception operation, the selector 16D
While the symbol clock CLK _SYB is falling
Only the phase error table 14-1 is enabled, and the symbol clock CLK
I and Q symbol stream data I '(8), Q' output from remapper 7 while _SYB is falling
The phase error data Δφ (3) corresponding to (8) is read and output to the delay circuit 90. The phase rotation angle determination circuit 92B determines the phase rotation angle based on the outputs of the delay circuits 90, 91, and 99, outputs the determination result in the form of a received signal phase rotation angle signal R (3), and outputs an averaging circuit 95. Is 4
The received signal phase rotation angle signal AR is averaged for the frame.
Output as (3).

The phase rotation angle discriminating circuit 92B and the averaging circuit 95 of the reception signal phase rotation angle detection circuit 8D detect the second phase rotation angle, and the received signal phase rotation angle signal AR (3)
Is output, the received signal phase rotation angle signal AR (3)
Are I '(8) and Q' (8) after absolute phase conversion by the remapper 7
3 shows the phase rotation angle with respect to the transmitting side as seen in FIG. Therefore, by adding to the previous reception signal phase rotation angle signal OR (3) held in the register 111, the reception signal phase rotation angle signal OR (3) for the transmission side viewed from the input side of the remapper 7 is obtained. The received signal phase rotation angle signal OR (3) is output to the remapper 7 to perform the second phase rotation (OR
Assuming that the phase rotation angle of the received signal shown in (3) is Θ, the phase is rotated by −Θ), and the register 110 holds the phase. Hereinafter, the same process is repeated each time the phase rotation angle discriminating circuit 92B and the averaging circuit 95 of the reception signal phase rotation angle detecting circuit 8D detect a new phase rotation angle.

According to this embodiment, the I and Q symbol stream data I ′ (8), Q ′ after the absolute phase conversion by the remapper 7 are stored in the phase error table of the carrier recovery circuit 10D.
Since (8) is input, during normal reception, regardless of the value of the received signal phase rotation angle, the I and Q symbol stream data I 'input to the phase error table are output.
(8), the reception signal point of Q '(8) becomes the same as the transmission side. Therefore, only one phase error table is provided for the carrier recovery circuit 10D for each modulation method, and the number of phase error tables provided for the carrier recovery circuit 10D can be reduced, and the circuit configuration can be greatly simplified.

The I and Q symbol stream data I '(8), Q' corresponding to bits (1) (bit (0)) of the frame synchronization signal output from the remapper 7
Phase error table 1 for QPSK modulation corresponding to (8)
The upper 3 bits that determine whether the absolute value of the phase error is larger or smaller than π / 8 in the phase error data according to 4-1;
I, Q symbol stream data I '(8), Q'
From the code bit data i ′ (1) and q ′ (1) of (8), the I of the portion corresponding to bit (1) (bit (0)) of the frame synchronization signal seen at the output point of the demodulation circuit 1D , Q symbol stream data I (8) and Q (8), the received signal phase rotation angle can be determined by a simple calculation. Therefore, it is not necessary to use a dedicated large-scale ROM for determining the phase rotation angle, and the circuit scale can be reduced.

In the above embodiment, the bit (0) and the bit (0) of the frame synchronization signal in the I and Q symbol stream data I '(8) and Q' (8) are used.
Although the phase rotation angle has been determined for both of the above-mentioned portions, it may be performed for only one of them. Various changes can be made to the averaging method. For example, averaging may be performed for one frame or two frames, or one bit or a plurality of bits at a specific position of a frame synchronization signal may be averaged over a plurality of frames. You may do it.

FIG. 1 can be modified as shown in FIG. In FIG. 7, the received signal phase rotation angle detection circuit 8C of FIG.
Are replaced by a phase rotation angle discriminating circuit 92E in which the adder 110 and the register 111 are omitted. Also, demodulation circuit 1
E, I and Q symbol stream data I '(8), Q' of each phase error table 13, 14-1, 15-1
A selector 19 is provided on the input side of (8), and the I and Q symbol stream data I output from the remapper 7 while the symbol clock CLK _SYB is rising.
'(8) and Q' (8) are stored in the respective phase error tables 13 and 14.
-1, 15-1 and the symbol clock CLK _SYB
During the fall, the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1E are input to the phase error tables 13, 14-1 and 15-1. is there. The delay circuit 91 has a demodulation circuit 1
Q symbol stream data Q (8) output from E
The sign bit data q (1), which is the MSB of, is input.

Then, after starting the reception, the selector 16C
Until the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8E detects the reception signal phase rotation angle, the phase for 8PSK is _maintained while the symbol clock CLK _SYB rises. Error table 1
3 from the remapper 7 through the selector 19 while the symbol clock CLK _SYB is rising from the phase error table 13.
The phase error data Δφ (8) corresponding to the Q symbol stream data I ′ (8), Q ′ (8) is read and output to the D / A converter 17. In parallel with this, while the symbol clock CLK _SYB falls, only the phase error table 15-1 for BPSK is enabled, and the symbol clock CL is _output from the phase error table 15-1.
I and Q symbol stream data I (8), Q input through selector 19 while K _SYB is falling
Of the phase error data Δφ (8) corresponding to (8), phase error data Δφ (3) of the upper 3 bits is read.

On the other hand, the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8
After E detects the received signal phase rotation angle Θ, the selector 1
6C is a phase error table 13 or 14-1 or 1 corresponding to the modulation method of the received signal demodulated by the demodulation circuit 1E while the symbol clock CLK _SYB is rising.
Only one of 5-1 is enabled, and the I and Q symbol stream data I '(8), Q' (8) input from the remapper 7 via the selector 19 while the symbol clock CLK _SYB is rising. ) _Is read out and output to the D / A converter 17, while only the BPSK phase error table 15-1 is enabled while the symbol clock CLK _SYB falls. From the phase error table 15-1, the phase error data Δφ corresponding to the I and Q symbol stream data I (8) and Q (8) input via the selector 19 while the symbol clock CLK _SYB falls.
Out of (8), upper three bits of phase error data Δφ (3)
Read out. The delay circuits 90 and 91, the adder 93, the selector 94, and the averaging circuit 95 of the reception signal phase rotation angle detection circuit 8E are operated in the same manner as in FIG. Received signal phase rotation angle signal A for the transmitting side as seen at the input side of remapper 7
(3) AR (3) can be output, and the adder 110 and the register 111 shown in FIG.

FIG. 5 can be modified as shown in FIG. In FIG. 8, the reception signal phase rotation angle detection circuit 8D of FIG.
B is replaced by a phase rotation angle determination circuit 92F in which the adder 110 and the register 111 are omitted. Further, the I and Q symbol stream data I '(8), Q' of each of the phase error tables 13, 14-1, 15-1 of the demodulation circuit 1F.
A selector 19 is provided on the input side of (8), and the I and Q symbol stream data I output from the remapper 7 while the symbol clock CLK _SYB is rising.
'(8) and Q' (8) are stored in the respective phase error tables 13 and 14.
-1, 15-1 and the symbol clock CLK _SYB
Is falling, the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1F are input to the phase error tables 13, 14-1 and 15-1. is there. The delay circuit 91 has a demodulation circuit 1
Q symbol stream data Q (8) output from F
Of the I symbol stream data I (8) output from the demodulation circuit 1F is input to the delay circuit 99 as the sign bit data i (1). Have been.

Then, after starting the reception, the selector 16D
Until the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8F detects the reception signal phase rotation angle, the phase for 8PSK is _maintained while the symbol clock CLK _SYB rises. Error table 1
3 from the remapper 7 through the selector 19 while the symbol clock CLK _SYB is rising from the phase error table 13.
The phase error data Δφ (8) corresponding to the Q symbol stream data I ′ (8), Q ′ (8) is read and output to the D / A converter 17. In parallel with this, while the symbol clock CLK _SYB falls, only the phase error table 14-1 for QPSK is enabled, and the symbol clock CL
I and Q symbol stream data I (8), Q input through selector 19 while K _SYB is falling
Of the phase error data Δφ (8) corresponding to (8), phase error data Δφ (3) of the upper 3 bits is read.

On the other hand, a transmission configuration identification circuit 9 identifies a multiplex configuration of a frame, and a reception signal phase rotation angle detection circuit 8
After F detects the received signal phase rotation angle Θ, the selector 1
6D is a phase error table 13 or 14-1 or 1 corresponding to the modulation method of the received signal demodulated by the demodulation circuit 1F while the symbol clock CLK _SYB is rising.
Only one of the 5-1 is enabled, and the I and Q symbol stream data I '(8), Q' (8) input from the remapper 7 via the selector 19 while the symbol clock CLK _SYB is rising. ) _Is read out and output to the D / A converter 17, while only the QPSK phase error table 14-1 is enabled while the symbol clock CLK _SYB falls. From the phase error table 14-1, the phases corresponding to the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1F via the selector 19 while the symbol clock CLK _SYB falls. From the error data Δφ (8), the phase error data Δφ (3) of the upper 3 bits is read. Delay circuits 90, 9
1, 99, adders 100 and 102, binary converter 10
1, the selector 103 and the averaging circuit 95 operate in the same manner as in FIG. (3) AR (3) can be output, and the adder 110 and the register 111 in FIG. 5 can be omitted, and AR (3) can be output to the remapper 7 or the like as it is.

In each of the above-described embodiments and modifications, after the reception is started, the transmission configuration is identified by the transmission configuration identification circuit, and the reception signal phase rotation angle detection circuit detects the reception signal phase rotation angle. In the meantime, the selector of the carrier wave recovery circuit outputs the phase error data read from the phase error table for 8PSK to the D / A converter. A value may be output. Further, the averaging circuit in FIGS. 1, 5, 7, and 8 may be omitted. Also, the reception signal phase rotation angle detection circuit in FIGS. 1, 5, 7, and 8 may be replaced with the reception signal phase rotation angle detection circuit in FIG.

In addition, 3 of 8PSK, QPSK and BPSK
Time-division multiplexed digital signals by two modulation schemes
Although the SK modulated wave is targeted, the present invention can be similarly applied to the case of receiving and demodulating a PSK modulated wave obtained by time-multiplexing only QPSK and BPSK.
Just prepare two for PSK) or 8PSK
Receives PSK modulated wave time-multiplexed with QPSK only
Used for demodulation (Phase error table is 8PS
KPS and QPSK should be prepared), 8PSK
Receives a PSK modulated wave obtained by time-multiplexing only BPSK and
This can be applied to the case of demodulation (only two phase error tables for 8PSK and BPSK should be prepared). Further, the present invention can be similarly applied to the case where the demodulation circuit performs the demodulation operation by quasi-synchronous detection instead of performing the demodulation operation by synchronous detection.

[0106]

According to the present invention, the phase error data corresponding to the I and Q symbol stream data after the absolute phase conversion by the anti-phase rotation means is read from the phase error table of the carrier recovery means. I and Q input to the phase error table regardless of the value of the received signal phase rotation angle
The reception signal point of the symbol stream data is the same as the transmission side. Therefore, only one phase error table is provided for the carrier recovery means for each modulation method, and the number of phase error tables provided for the carrier recovery means can be reduced, and the circuit configuration can be greatly simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a received signal phase rotation angle signal output from a phase rotation angle discrimination circuit in FIG. 1 and a received signal phase rotation angle.

FIG. 3 is a block diagram illustrating a configuration example of an averaging circuit in FIG. 1;

FIG. 4 is an explanatory diagram showing a correspondence relationship between a binary code and a Gray code.

FIG. 5 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram showing the input / output correspondence of the binary converter in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a modification of FIG. 1;

FIG. 8 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a modification of FIG. 5;

FIG. 9 is an explanatory diagram illustrating an example of a frame configuration in the hierarchical transmission scheme.

FIG. 10 is a block diagram showing a configuration around a demodulation circuit of a PSK modulated wave receiver according to a conventional hierarchical transmission scheme.

FIG. 11 is an explanatory diagram showing a signal point arrangement in PSK mapping.

FIG. 12 is a block diagram in which a part of the carrier wave recovery circuit in FIG. 10 is omitted.

FIG. 13 is an explanatory diagram of how to measure the phase of a received signal point.

FIG. 14 is an explanatory diagram of how to measure a received signal phase rotation angle.

FIG. 15 is an explanatory diagram of a phase error table for 8PSK.

FIG. 16 is an explanatory diagram of a phase error table for QPSK.

FIG. 17 is an explanatory diagram of a phase error table for QPSK.

FIG. 18 is an explanatory diagram of a phase error table for BPSK.

FIG. 19 is an explanatory diagram of a phase error table for BPSK.

FIG. 20 is an explanatory diagram of a phase error table for BPSK.

FIG. 21 is an explanatory diagram of a phase error table for BPSK.

FIG. 22 is a block diagram of a synchronization detection / reproduction circuit in FIG.

FIG. 23 is an explanatory diagram for explaining BPSK demapping;

24 is a circuit diagram showing a configuration of a synchronization detection circuit in FIG.

FIG. 25 is a circuit diagram showing a configuration of a BPSK demapper in FIG. 22;

26 is a signal point arrangement diagram of a frame synchronization signal before and after passing through a 0 ° / 180 ° phase rotation circuit in FIG. 10;

FIG. 27 is an explanatory diagram of a reception signal phase rotation angle determination table used by the phase determination circuit in FIG. 10;

[Explanation of symbols]

 1C, 1D, 1E, 1F Demodulation circuit 2 Frame synchronization detection / reproduction circuit 7 Remapper 8C, 8D, 8E, 8F Received signal phase rotation angle detection circuit 9 Transmission configuration identification circuit 10C, 10D Carrier reproduction circuit 11 VCO 12 90 ° phase shift Units 13, 14-1, 15-1 Phase error tables 16C, 16D, 19, 94, 103 Selectors 90, 91, 99 Delay circuits 92, 92B, 92E, 92F Phase rotation angle discriminating circuits 93, 100, 102, 110 Addition Unit 95 averaging circuit 101 binary converter 111 register

Claims (1)

(57) [Claims] 1. A PSK in which digital signals modulated by a plurality of types of PSK modulation systems having different numbers of phases are time-multiplexed.
A demodulation unit that demodulates the modulated signal using the carrier reproduced by the carrier regeneration unit and outputs I and Q symbol stream data, and a phase rotation of the I and Q symbol stream data output from the demodulation unit with respect to the transmitting side. The phase rotation of the I and Q symbol stream data output from the reception signal phase rotation angle detecting means for detecting the angle and the demodulation means is reversed in phase by the phase rotation angle detected by the reception signal phase rotation angle detection means. Output phase rotation means, and the carrier recovery means of the demodulation means has a phase error table storing carrier phase error data for various demodulated I and Q symbol stream data sets for each modulation method, While the demodulation means is demodulating a certain modulation scheme part, the I and Q symbol stream data after demodulation from the phase error table of the corresponding modulation scheme. In a receiver which reads out the corresponding phase error data and corrects the phase of the carrier wave, the carrier recovery means is configured to perform the phase modulation of the corresponding modulation scheme while the demodulation means is demodulating a certain modulation scheme portion of the received signal. A receiver for reading phase error data corresponding to the demodulated I and Q symbol stream data output from the anti-phase rotation means from the error table, and correcting the phase of the carrier wave.