JP2002101142A - Digital broadcasting demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital broadcasting demodulator capable of effectively carrier regenerating in a PSK demodulating circuit for demodulating a quasi- synchronous detected PSK modulation signal. SOLUTION: A synchronous detecting timer 44 outputs random data X to a random data generator 46 when a state in which a frequency synchronization is detected and a phase synchronization is not detected is continued for a predetermined period. A numeric value control oscillator 54 shifts the regenerated carrier by an amount in response to the random data X and the regenerated carrier falls in a phase leading-in range. Accordingly, a phase error detector 38 and a loop filter 50 are operated, and an accurate carrier can be effectively regenerated in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus for receiving digital broadcasting, for example, receiving BS digital broadcasting, and more particularly to a digital broadcasting demodulating apparatus for demodulating a PSK (phase shift keying) modulated signal.

[0002] More specifically, the present invention relates to carrier recovery in PSK demodulation.

[0003]

2. Description of the Related Art In recent years, digital broadcasting, which replaces conventional analog broadcasting, has been introduced for the purpose of improving image quality, increasing the number of channels, increasing functionality, and improving quality.

FIG. 7 is a diagram for explaining a transmission signal of a BS digital broadcast. Referring to FIG. 7, in BS digital broadcasting, a main signal is transmitted in a frame unit configuration. The frame is composed of a synchronization signal, a transmission multiplex control signal (hereinafter, TMC).
C signal) and the main signal.

[0005] One frame includes a synchronization word signal and a TMCC signal at the beginning. The number of symbols of the TMCC signal and the synchronization word signal is 192, and the number of symbols of the synchronization word signal is 40. Here, the symbol means a signal received in synchronization with one clock. The TMCC signal and the synchronization word signal are modulated by the BPSK method (two-phase shift keying method) and transmitted.

Following the synchronization word signal and the TMCC signal, data of a main signal of 203 symbols is arranged. The data of the main signal includes a video signal, an audio signal, and a data signal used for communication and the like. The main signal data is
Either BPSK modulation, QPSK modulation (four-phase shift keying modulation), or 8PSK modulation (eight-phase shift keying modulation) is performed. Which modulation method is used to modulate the data portion of the main signal can be known by demodulating the contents of the TMCC signal.

After the data, a 4-symbol burst signal is arranged. The burst signal is BP like the TMCC signal.
It is modulated by the SK modulation method. Thereafter, the data of the main signal and the burst signal are arranged alternately.

[0008] A set of four consecutive sets of data of a main signal and a burst signal as one set is called one slot. The data portion of the main signal included in each slot is modulated by various modulation methods for each slot.

The head TMCC signal of one frame and the burst signal inserted between the data contain a control signal which is more important for demodulation than the data part of the main signal. It is modulated by the BPSK method.

FIG. 8 is a block diagram showing the configuration of a conventional PSK demodulator 320. Referring to FIG.
Demodulator 320 receives the I 'and Q' signals converted to baseband. In frequency conversion to a baseband signal, synchronous detection is not performed, and conversion to a baseband signal is generally performed using a free-run local oscillation signal. This frequency conversion method is generally called quasi-synchronous detection.

The quasi-synchronous detection method is a detection method that replaces synchronous detection in which a carrier is reproduced from a received signal and the reproduced carrier is applied to a phase detection circuit. The quasi-synchronous detection method is a method in which a process corresponding to a carrier recovery process performed by analog of the synchronous detection method is realized by digital signal processing in a part where baseband processing is performed. Therefore, there is an advantage that adjustment is unnecessary.

Referring to FIG. 8, PSK demodulator 320
Receives the I ′ signal and the Q ′ signal that have been quasi-synchronously detected, and receives the I (In phase) signal and the Q (Quadratu
re phase) complex multiplier 332 for converting to a signal
And an output of the complex multiplier 332 to obtain a phase angle α based on the I signal and the Q signal, and a frequency error detection for detecting a frequency error from a change in the phase angle α detected by the angle converter 334. Unit 336 and frequency error detection unit 3
36, the high frequency component is removed from the output of the frequency control signal 2π.
and a loop filter 348 that generates fr.

[0013] The PSK demodulator 320 further receives a phase error detecting section 338 which receives an output of the angle converting section 334 to detect a phase error, and receives a phase error θ0 detected by the phase error detecting section 338 to convert a high frequency component. A loop filter 350 for removing and generating a phase control signal θ;
an adder 352 that adds fr and the phase control signal θ, and a signal cos necessary for the complex multiplier receiving the output of the adder 352
Numerically Controlled Oscillator (NCO) 354 that outputs (2πfr + θ) and sin (2πfr + θ).

FIG. 9 is a diagram for explaining how the angle converter 334 determines the phase angle α.

Referring to FIG. 9, angle conversion section 334 includes I
Upon receiving the signal and the Q signal, the phase angle α is determined from the positions of the I and Q signals received on a constellation plane with the value of the I signal on the horizontal axis and the value of the Q signal on the vertical axis.

For example, when the I signal and Q signal received at a certain time correspond to the position of A0 in FIG. 9, the phase angle becomes θ0. Similarly, when the I signal and the Q signal received at the next time correspond to the position of A1, the phase angle becomes θ1
Becomes

If the position recognized from the I signal and the Q signal changes from A0 to A1, the frequency error detection unit 336 in FIG. 8 detects a frequency error from a change in the phase angle, that is, θ1-θ0.

This phase angle is determined by the phase error detector 33 shown in FIG.
8 is also given. For the sake of simplicity, binary PSK will be described. For example, the burst signal described with reference to FIG. 7 is a signal that is BPSK-modulated. And π.

Now, when the position corresponding to the I signal and the Q signal is A0, the phase error is detected as θ0 because the position is close to the position of the point where the phase angle is 0.

[0020]

As described above, in BS digital broadcasting, a BPSK-modulated burst signal is inserted as a transmission standard, and a carrier wave (carrier) is reproduced based on this signal. This makes the system resistant to degradation of the reception state due to rainfall and the like.

However, the burst signal is a signal in which four symbols are inserted every 203 symbols, and during the 203 symbol period during which the main signal data is transmitted, the PSK demodulator must detect the phase error component of the reproduced carrier. Can not. If there is a phase error in the reproduced carrier, correct demodulation cannot be performed during the period of the main signal data. Therefore, it is required that frequency detection and phase detection be rapidly performed with four symbols of a burst signal and carrier reproduction be performed with high accuracy.

FIG. 10 is a diagram for explaining frequency pull-in during carrier reproduction.

Referring to FIG. 10, when the reproduction of the carrier is started, until time t0, frequency error detecting section 33 shown in FIG.
6 detects the frequency error and changes the control signal 2πfr. However, after time t0, the numerically controlled oscillator 354
Is the frequency of the frequency synchronization range W
1, the frequency error detector 336 recognizes that the frequency is in a synchronized state, and holds the control signal 2πfr.

At time t1, the frequency error detector 33
The frequency change according to the control of No. 6 converges, and in this state, it may not be within the phase pull-in range W2. In such a state, that is, in a state in which the phase synchronization detection unit indicates an asynchronous state for a certain period of time despite the fact that the frequency is in a synchronous state, conventionally, nothing is performed in a circuit and accidentally due to noise or the like. Either wait until the frequency at which the phase can be pulled in, or operate from a new frequency synchronization.

As an example of the reason why the reproduced frequency does not reach the pull-in range by the phase control, a case where an offset error due to an AD converter (analog-digital converter) exists will be described.

FIG. 11 is a diagram for explaining the phase angle on the constellation plane when there is an offset error.

In FIG. 11, when the analog I 'and Q' signals are converted into digital signals by the two-channel AD converter, the AD converter for converting the Q 'signal is normal, but receives the I' signal. AD
This shows a case where a positive offset error occurs in the converter. When an offset error occurs, the phase angle of the point A00 becomes θ00, and the phase angle of A11 becomes θ11. If such an offset error exists, accurate frequency detection cannot be performed, and an error may occur in the frequency. In such a case, the frequency of the reproduced carrier does not reach the pull-in range by the phase control.

An object of the present invention is to provide a digital broadcast demodulator capable of performing carrier reproduction more effectively.

[0029]

According to the present invention, there is provided a digital broadcast demodulator for demodulating a quasi-synchronously detected n (n is a natural number of 2 or more) PSK modulated signal, comprising a quasi-synchronously detected I 'signal. Complex multiplying means for receiving the signal and the Q 'signal and converting them into I and Q signals which are synchronous detection signals, and receiving the I signal and the Q signal output from the complex multiplying means to detect a frequency error and a phase error, Synchronization detection means for outputting an oscillation control signal, wherein the synchronization detection means determines whether frequency synchronization and phase synchronization are achieved from the frequency error and the phase error, respectively, and the frequency is in a synchronous state and the phase is in an asynchronous state. When a certain period continues for a predetermined time, the oscillation control signal is forcibly changed according to a predetermined value,
The apparatus further includes a numerically controlled oscillator that outputs reproduced carrier wave data to the complex multiplying means according to the oscillation control signal.

Preferably, the synchronization detecting means includes a frequency error detecting means for detecting a frequency error of the reproduced carrier in accordance with the I signal and the Q signal, and a frequency synchronization detecting means for performing frequency synchronization detection in accordance with the output of the frequency error detecting means. Means, a phase error detecting means for detecting a phase error of the reproduced carrier wave in accordance with the I signal and the Q signal, a phase synchronization detecting means for performing phase synchronization detection in accordance with an output of the phase error detecting means, a frequency synchronization detecting means, In response to the output of the phase synchronization detection means, a period in which the frequency is in a synchronized state and the phase is in an asynchronous state is counted, and a synchronization detection timer for detecting that the period exceeds a predetermined time, and an output of the synchronization detection timer Data generating means for generating a predetermined value according to, frequency error detecting means,
Control signal output means for outputting an oscillation control signal in accordance with the outputs of the phase error detection means and the data generation means.

More preferably, the data generating means has a random data generating circuit for generating random data, and a switch circuit for supplying the random data to the control signal output means according to the output of the synchronization detection timer.

More preferably, the data generating means includes I '
A switch circuit for supplying a plurality of bits from the least significant bit of the internal signal corresponding to at least one of the signal and the Q 'signal to the control signal output means in accordance with the output of the synchronization detection timer.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a schematic block diagram showing the configuration of a digital receiver (STB) 10 for receiving a BS digital broadcast according to the present invention.

Referring to FIG. 1, a digital receiver 10 includes:
A tuner 12 connected to an antenna 4 for receiving BS digital broadcast digital data sent from a satellite 2 and converting the digital data into a desired intermediate wave signal (IF signal)
And a quadrature detection circuit 14 for quadrature detecting the IF signal and outputting baseband analog I and Q signals, and an AD conversion for converting the analog I signal and Q signal output from the quadrature detection circuit 14 to a digital signal And removes unnecessary high frequency components included in the output of the AD converter 16 and
A Nyquist filter 18 for performing a filtering process for preventing intersymbol interference.

The digital receiver 10 further performs PSK demodulation on the digital I 'signal and Q' signal filtered by the Nyquist filter 18 and outputs a PSK demodulator 20 for outputting I and Q signals.
A signal processing unit 22 that receives the output of the demodulation device, reproduces a digital code from the coordinates on the constellation plane, and performs error correction and descrambling, and an MPEG decoding unit 24 that receives the output of the signal processing unit 22 and performs MPEG decoding. And The audio signal A and the video signal V output from the MPEG decoding unit 24 are connected to a monitor including a display device and a sound reproducing device.

FIG. 2 shows the PSK demodulator 20 in FIG.
FIG. 2 is a block diagram showing the configuration of FIG. Referring to FIG.
The SK demodulator 20 receives a baseband-converted I 'and Q' signal and converts them into I and Q signals whose rotation has been stopped on a constellation plane, and a complex multiplier 32 And a synchronous detection unit 33 that detects a phase error and a frequency error from the I signal and the Q signal output from the I / Q signal and outputs a carrier control signal, and receives the output of the synchronization detection unit 33 and outputs a signal cos (2
πfr + θ) and a numerically controlled oscillator 54 that outputs sin (2πfr + θ). The numerically controlled oscillator 54 includes, for example, a ROM (Read Only Memory) holding digital data of a sine wave or a cosine wave, and outputs the data held in synchronization with the system clock to the synchronization detector 3.
3 is read out.

The synchronization detecting section 33 receives an I signal and a Q signal output from the complex multiplier 32, and detects an angle conversion section 34 which detects a change in the phase angle α according to the position on the constellation plane by a combination of these signals. A frequency error detector 36 for detecting a frequency error from a change amount of the phase angle per unit time detected by the angle converter 34, a phase error detector 38 for obtaining a phase error from the phase angle obtained by the angle converter 34, including.

Operations of frequency error detecting section 36 and phase error detecting section 38 are the same as those of frequency error detecting section 336 and phase error detecting section 338 shown in FIG. 8, and description thereof will not be repeated.

The synchronization detection section 33 further includes a frequency synchronization detection section 40 for determining whether or not the amount of change in the phase angle detected by the frequency error detection section 36 is within a specified range. Receiving the output, detects whether or not the position on the constellation plane determined from the I signal and the Q signal is at a phase position within a predetermined range, and determines whether phase synchronization has been achieved. , Frequency synchronization detector 40
The timer count is started after the frequency synchronization is received in response to the output of the phase synchronization detection unit 42. If the phase synchronization cannot be achieved even when the frequency exceeds a predetermined count value, the control signal SD
And a synchronization detection timer 44 for outputting T.

The phase synchronization detecting section 42 has, for example, BPSK
In the case of modulation, if there are many phase angles detected from the I signal and the Q signal near π / 2 or 3π / 2, it is determined that phase synchronization is not established, and the phase is determined near π / 2 or 3π / 2. If there is almost no angle, it is determined that phase synchronization has been achieved. The frequency synchronization detection unit 40 outputs the control signal SD when the phase synchronization has not yet been achieved even after exceeding the predetermined count value.
In response to T, the frequency synchronization detection is reset to a non-detection state in which frequency synchronization is not established.

The synchronization detector 33 further includes a control signal SD
A random data generator 46 for generating random data X in accordance with T, a frequency error detector 36, a phase error detector 38, and a numerically controlled oscillator 54 in response to outputs of the random data generator 46 for carrier reproduction. And a control signal output unit 45 that outputs the control signal of

The control signal output unit 45 includes a frequency control signal output unit 47 that adds random data X to the output of the frequency error detection unit 36, cuts high frequency components, and outputs a frequency control signal 2πfrX. The frequency control signal output unit 47
It includes an adder 48 that adds random data X to the output of the frequency error detection unit 36, and a loop filter 49 that cuts high-frequency components of the output of the adder 48.

The control signal output unit 45 further includes a loop filter 50 that receives the output of the phase error detection unit 38, cuts out high frequency components and outputs a phase control signal θ, a frequency control signal 2πfrX and a phase control signal θ. And an adder 52 for adding the result to the numerically controlled oscillator 54.

FIG. 3 is a block diagram showing a configuration of complex multiplier 32 shown in FIG. Referring to FIG. 3, complex multiplier 32 multiplies I ′ signal by signal cos (2πfrX + θ), Q ′ signal and signal sin (2πfr)
X + θ), and an adder 66 that adds the output of the multiplier 62 and the output of the multiplier 64 and outputs an I signal.

The complex multiplier 32 further includes a multiplier 68 for multiplying the I ′ signal by the signal sin (2πfrX + θ),
It includes a multiplier 70 for multiplying the Q 'signal by the signal cos (2πfrX + θ), and a subtractor 72 for subtracting the output of the multiplier 68 from the output of the multiplier 70 and outputting a Q signal.

Therefore, the I signal and the Q signal are represented by the following equations (1) and (2), respectively.

I = I ′ × cos (2πfrX + θ) + Q ′ × sin (2πfrX + θ) (1) Q = Q ′ × cos (2πfrX + θ) −I ′ × sin (2πfrX + θ) (2) FIG. FIG. 3 is a circuit diagram showing a configuration of a random data generation unit 46 in FIG.

In this example, the random data generator 46
This is an example in which a pseudo random data generator is used. FIG.
Uses a ninth-order random data generator.
Of the next data, three bits from the LSB (least significant bit) are taken out as random data.

The random data generator 46 receives flip-flops 82 to 98 connected in series and operating in synchronization with the system clock, the output of the flip-flop 88 and the output of the flip-flop 98, and supplies them to the input of the flip-flop 82. And an EXOR circuit 100.

The random data generator 46 further controls the E in response to the control signal SDT output from the synchronization detection timer 44.
The output of the XOR circuit 100 and the flip-flop 82,
84 is a 3-bit random data output RDOU
It includes a changeover switch 102 for outputting as T. The changeover switch 102 has a control signal SD on one input.
Three AND circuits may be provided in which T is input and the other input is provided with the output of the EXOR circuit 100 and the flip-flops 82 and 84, respectively.

FIG. 5 is a waveform chart for explaining the frequency pull-in operation in the present invention. Referring to FIGS. 2 and 5, before time t0, frequency error detecting section 36 determines that the frequencies are not synchronized, and performs frequency control so that frequency control signal 2πfr approaches carrier frequency fc. After time t0, the frequency error detector 36
Determines that the frequencies are synchronized. Then, the frequency control signal 2πfr falls to a certain value. As a result, the frequency of the carrier output from the numerically controlled oscillator 54 is f1
Converges to From time t0, the frequency synchronization detection unit detects synchronization, while the phase synchronization detection unit 42 does not detect phase synchronization, so that the synchronization detection timer 44 starts counting.

At time t1, when the synchronization detection timer period specified by the synchronization detection timer 44 has elapsed, the synchronization detection timer 44 resets the frequency synchronization detection unit 40. At the same time, it instructs the random data generator 46 to generate random data X. Accordingly, at time t1, phase control signal 2
πfrX changes. In the case of FIG. 5, it is shown that random data in a direction in which the carrier frequency shifts to a low frequency at the timing of time t1 has occurred.

In this case, the state where frequency synchronization is detected even when random data is generated and phase synchronization is not detected continues. At time t2, as the synchronization detection timer period elapses, the synchronization detection timer 44 outputs the control signal SDT again. At time t2, the random data generator 46 generates the random data X again, and the frequency control signal 2πfrX changes accordingly. In this case, since the random data X is data whose frequency shifts to a high frequency range, the frequency of the reproduced carrier crosses the phase lock-in range. In response, the phase error detection unit 38 operates to change the reproduction carrier frequency to fc, and the phase synchronization detection unit 42 detects phase synchronization.
No longer outputs the control signal SDT.

As described above, according to the present invention, a signal obtained by adding random data X to the frequency control signal 2πfr is newly set as the frequency control signal 2πfrX.
Output from Therefore, as shown in FIG. 5, the frequency of the carrier is forcibly shifted based on the frequency f1 converged in the frequency synchronization state, so that the frequency synchronization and the phase synchronization are performed again from the beginning. Can be planned.

Also, random data X is used as addition data.
Is added, phase synchronization can be performed even when the stable point of frequency synchronization is far away from the actual carrier frequency fc.

[Second Embodiment] FIG. 6 is a diagram showing a configuration of a random data generator 146 used in place of the random data generator 46 in the second embodiment.

Referring to FIG. 6, random data generating section 1
The control signal SDT 46 receives the least significant three bits of the n-bit I 'signal, i.e., I'0, I'1, and I'2.
And a switch circuit 202 for supplying the 3-bit random data output RDOUT to the loop filter 48 in response to The switch 202 has a control signal SDT input to one input and signal bits I'0, I'0,
Three AND circuits to which I'1 and I'2 are applied may be used.

FIG. 6 shows an example in which the lower bits of the I 'signal are used as random data. However, for example, several bits from the LSB of the data of the frequency control signal 2πfr may be used, and the data of the I signal and the Q signal may be used. A configuration using an arbitrary number of bits may be used.

That is, with the configuration as in the second embodiment, the additional circuit only needs to add one changeover switch, and the increase in the number of circuits can be suppressed.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0062]

According to the present invention, the problem that the frequency to be stabilized does not fall within the phase pull-in range but the phase cannot be synchronized can be solved by a simple method even though the frequency is synchronized. .

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating a configuration of a digital receiver (STB) 10 for receiving a BS digital broadcast according to the present invention.

FIG. 2 is a block diagram showing a configuration of a PSK demodulation device 20 in FIG.

FIG. 3 is a block diagram showing a configuration of a complex multiplier 32 shown in FIG.

FIG. 4 is a circuit diagram showing a configuration of a random data generator 46 in FIG. 2;

FIG. 5 is a waveform chart for explaining a frequency pull-in operation in the present invention.

FIG. 6 is a diagram showing a configuration of a random data generator 146 used in the second embodiment.

FIG. 7 is a diagram for explaining a transmission signal of a BS digital broadcast.

FIG. 8 is a block diagram showing a configuration of a conventional PSK demodulator 320.

FIG. 9 is a diagram for explaining how to obtain a phase angle α in the angle conversion unit 334.

FIG. 10 is a diagram for explaining frequency pull-in during carrier reproduction.

FIG. 11 is a diagram for explaining a phase angle on a constellation plane when there is an offset error.

[Explanation of symbols]

Reference Signs List 10 digital receiver, 12 tuner, 14 quadrature detection circuit, 16 AD converter, 18 Nyquist filter, 20 PSK demodulator, 22 signal processing unit, 24
Decoder, 32 complex multiplier, 33 synchronization detector, 3
4 Angle conversion unit, 36 frequency error detection unit, 38 phase error detection unit, 40 frequency synchronization detection unit, 42 phase synchronization detection unit, 44 synchronization detection timer, 46 random data generation unit, 48, 50 loop filter, 52 adder,
54 Numerically controlled oscillator, 62, 64, 68, 70 multiplier, 66, 72 adder, 82, 88, 98 flip-flop, 100 EXOR circuit, 102 switch, 146 random data generator, 202 switch circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Showa Kita 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) in Sanyo Electric Co., Ltd. FA06 FG01 FJ01 5K047 AA06 AA11 CC08 EE02 GG11 GG33 MM12 MM13 MM56 MM60 MM63

Claims (4)

[Claims] 1. A digital broadcast demodulator for demodulating a quasi-coherently detected n (n is a natural number of 2 or more) -valued PSK modulated signal, comprising: receiving a quasi-coherently detected I 'signal and a Q' signal, Complex multiplying means for converting the signals into I and Q signals which are synchronous detection signals; synchronous detection for receiving the I and Q signals output from the complex multiplying means, detecting a frequency error and a phase error, and outputting an oscillation control signal Means for determining whether or not frequency synchronization and phase synchronization have been achieved from the frequency error and the phase error, respectively, and a period in which the frequency is in a synchronous state and the phase is in an asynchronous state is predetermined. Numerically controlled oscillator that forcibly changes the oscillation control signal according to a predetermined value when time continues, and outputs reproduced carrier wave data to the complex multiplying means according to the oscillation control signal. Further comprising, a digital broadcast demodulating unit. 2. The synchronization detection means, wherein: a frequency error detection means for detecting a frequency error of the reproduced carrier in response to the I signal and the Q signal; and a frequency synchronization detection in response to an output of the frequency error detection means. Frequency synchronization detection means, phase error detection means for detecting a phase error of the reproduced carrier according to the I signal and Q signal, and phase synchronization detection means for performing phase synchronization detection according to the output of the phase error detection means Receiving the outputs of the frequency synchronization detection means and the phase synchronization detection means, counting the period in which the frequency is in a synchronous state and the phase is in an asynchronous state, and detecting that the period exceeds a predetermined time. A detection timer, a data generation unit that generates the predetermined value in accordance with an output of the synchronization detection timer, the frequency error detection unit, and the phase error detection unit Depending on the output of the pre said data generating means, and a control signal output means for outputting the oscillation control signal, a digital broadcast demodulating apparatus according to claim 1. 3. The data generating means includes: a random data generating circuit for generating random data; and a switch circuit for supplying the random data to the control signal output means in accordance with an output of the synchronization detection timer. 3. The digital broadcast demodulator according to 2. 4. The data generating means provides a plurality of least significant bits of an internal signal corresponding to at least one of the I 'signal and the Q' signal to the control signal output means in accordance with the output of the synchronization detection timer. The digital broadcast demodulation device according to claim 2, further comprising a switch circuit.