JP3849896B2 - Receiving device, receiving method, and transmission medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a receiving apparatus, a receiving method, and a transmission medium, and in particular, a receiving apparatus and a receiving method capable of determining a carrier frequency based on a correlation value of a predetermined signal repeatedly transmitted, and It relates to a transmission medium.
[0002]
[Prior art]
ISDB (Intergrated Services Digital Broadcasting) is being developed as one method of digital broadcasting. This ISDB is characterized by flexible data multiplexing and can implement various services using various transmission channels.
[0003]
In ISDB, from the viewpoint of achieving consistency with other media such as communication satellites, terrestrial waves, and cables, (204, 188) Reed-Solomon encoded (hereinafter abbreviated as RS code) transport stream (hereinafter referred to as RS code). BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), or Trellis-coded 8PSK (Phase Shift) Keying), and a method of transmitting transmission information of a modulation method and a coding rate by BPSK using a synchronization unit of TS has been proposed.
[0004]
Here, the data structure of the multiplexed transmission signal will be described.
[0005]
First, signals constituting a program such as video, audio, and various data are digitized and encoded by a method suitable for the nature of each signal. The encoded signal is then packetized into packets of a predetermined fixed length and is time division multiplexed on a packet basis to generate a packet stream.
[0006]
Next, as shown in FIG. 3, in order to obtain a strong resistance against transmission degradation, the packet is configured into a frame having a periodic synchronization structure. In this case, 16-byte parity is added to the 188-byte TS packet by RS (204, 188) encoding, and one frame is composed of 48 packets.
[0007]
The first byte of each packet is a synchronization byte, the synchronization bytes of the first two packets of the frame are frame synchronization signals, and the synchronization bytes of the third and subsequent packets are TMCC ( Transmission Multiplexing Configuration Control) signal. This TMCC signal includes transmission control information such as the modulation method and coding rate of the main signal (region signal other than the synchronization byte).
[0008]
The main signal of the first two packets of one frame is a low layer signal LQ, and this signal is interleaved within the range of the two packets and further subjected to convolutional coding. On the other hand, the main signal of the remaining 46 packets out of the 48 packets constituting one frame is a high-layer signal HQ, which is interleaved and then 2/3 trellis encoded. Is done.
[0009]
The RS encoded, interleaved and convolutionally encoded main signal is then read out in units of 8 packets. That is, as shown in FIG. 4A, the first synchronization bytes 1-1, 2-1, 3-1,..., 48-1 of 48 packets are first read in byte units. After that, the main signal is read in units of 8 packets byte by byte in the order of the arrows (1-2, 2-2, ... 8-2, 1-3, 2-3, ...). As a result, the bit stream shown in FIG. 4B is formed and input to a modulator (not shown) as a final multiplexed signal. In the modulator, the frame synchronization signal and the TMCC signal (synchronization byte signal) are modulated by BPSK, the low layer signal LQ is modulated by QPSK, and the high layer signal HQ is modulated by 8PSK.
[0010]
The modulated signal modulated as described above is transmitted to the receiving apparatus via a predetermined transmission path.
[0011]
Next, a receiving apparatus in ISDB will be described. FIG. 5 shows a configuration example of a conventional receiving apparatus.
[0012]
A modulated signal transmitted via a predetermined transmission path is received by a tuner (not shown) and is input to a frame synchronization detection circuit 61 and a PSK demodulation circuit 62. The frame synchronization detection circuit 61 detects a frame synchronization signal from the input signal, and outputs the detection result to the PSK demodulation circuit 62, the phase detection circuit 63, and the Viterbi decoding circuit 64. The phase detection circuit 63 detects phase information from the output of the frame synchronization detection circuit 61 and outputs the detection result to the PSK demodulation circuit 62.
[0013]
The PSK demodulation circuit 62 performs demodulation processing based on the outputs of the TMCC decoder 65, the frame synchronization detection circuit 61, and the phase detection circuit 63. Here, a carrier (reference signal) is reproduced by multiplying the modulation signal by the number of PSK phases of the modulation signal, and the modulation signal is demodulated using the carrier. For example, in the case of a BPSK modulation signal, the carrier can be reproduced by squaring the modulation signal, and in the case of an 8-phase PSK modulation signal, the carrier can be reproduced by raising the modulation signal to the eighth power.
[0014]
The TMCC decoder 65 decodes the TMCC signal from the signal input from the Viterbi decoding circuit 64, extracts transmission control information such as a modulation method and a coding rate, and extracts the extracted result as a PSK demodulation circuit 62 and a Viterbi decoding circuit. 64. Thereafter, the PSK demodulation circuit 62 and the Viterbi decoding circuit 64 demodulate the input main signal in accordance with the transmission control information from the TMCC decoder 65.
[0015]
The Viterbi decoding circuit 64 performs Viterbi decoding on the signal from the PSK demodulation circuit 62 based on the output of the TMCC decoder 65 or the frame synchronization detection circuit 61 and outputs the result to the deinterleave circuit 66. The deinterleave circuit 66 deinterleaves the input signal and outputs it to the Reed-Solomon decoding circuit 67. The Reed-Solomon decoding circuit 67 performs Reed-Solomon decoding on the signal from the deinterleave circuit 66 and outputs it to the MPEG decoder 68. The MPEG decoder 68 decodes the signal from the Reed-Solomon decoding circuit 67 into a video signal or an audio signal.
[0016]
[Problems to be solved by the invention]
In this way, when demodulating a modulation signal, when the carrier of a predetermined frequency serving as a reference for demodulation is reproduced by multiplying the modulation signal by the number of phases of the PSK, Since the included noise component and the like are also added, the influence of the noise component is expanded, the accuracy of the carrier frequency is lowered, and accurate demodulation becomes difficult.
[0017]
The present invention has been made in view of such a situation, and makes it possible to detect and generate an accurate frequency and phase carrier.
[0018]
[Means for Solving the Problems]
Receiver according to claim 1 includes a receiving means for receiving the transmitted modulated signals, the correlation value calculation means for calculating a correlation value of the received modulated signal by the receiving means, the modulation signal received by the receiving means Frequency deviation calculating means for calculating the frequency deviation of the carrier, and frequency determining means for determining the frequency of the carrier for demodulating the modulation signal received by the receiving means based on the frequency deviation calculated by the frequency deviation calculating means. The frequency determining means determines the frequency of the carrier for demodulating the received modulated signal based on the frequency deviation of the modulated signal having a correlation value greater than a predetermined threshold value .
[0019]
According to a third aspect of the present invention, there is provided a reception method of receiving a transmitted modulated signal, a correlation value calculating step of calculating a correlation value of the modulated signal received in the process of the receiving step, and receiving in the process of the receiving step. A frequency deviation calculating step for calculating a frequency deviation of the modulated signal, and a carrier frequency for demodulating the modulation signal received in the receiving step processing based on the frequency deviation calculated in the frequency deviation calculating step processing Determining a carrier frequency for demodulating the received modulated signal based on a frequency deviation of the modulated signal having a correlation value greater than a predetermined threshold value. It is characterized by that.
[0020]
The transmission medium according to claim 4 is a reception step of receiving the transmitted modulation signal, a correlation value calculation step of calculating a correlation value of the modulation signal received in the processing of the reception step, and reception in the processing of the reception step. A frequency deviation calculating step for calculating a frequency deviation of the modulated signal, and a carrier frequency for demodulating the modulation signal received in the receiving step processing based on the frequency deviation calculated in the frequency deviation calculating step processing Determining a carrier frequency for demodulating the received modulated signal based on a frequency deviation of the modulated signal having a correlation value greater than a predetermined threshold value. A program for causing a computer to execute reception processing is transmitted.
[0021]
The receiving device according to claim 1, the receiving method according to claim 2, and the transmission medium according to claim 4 receive a transmitted modulated signal, calculate a correlation value of the received modulated signal, The frequency deviation of the received modulated signal is calculated, and the frequency of the carrier for demodulating the received modulated signal is determined based on the frequency deviation of the modulated signal whose correlation value is greater than a predetermined threshold.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below, but in order to clarify the correspondence between each means of the invention described in the claims and the following embodiments, in parentheses after each means, The features of the present invention will be described with the corresponding embodiment (however, an example) added. However, of course, this description does not mean that each means is limited to the description.
[0023]
The receiving apparatus according to claim 1 includes a receiving unit (for example, the RF block 2 in FIG. 1) that receives the transmitted signal and a correlation value calculating unit (for example, that calculates a correlation value of the signal received by the receiving unit). 2 and a frequency determining means (for example, frequency converting section 50 in FIG. 2) for determining the carrier frequency of the received signal based on the correlation value calculated by the correlation value calculating means. It is characterized by providing.
[0024]
FIG. 1 shows a configuration example of a receiving apparatus to which the present invention is applied.
[0025]
A modulated signal transmitted by a carrier having a predetermined frequency via a predetermined transmission path is received by the RF block 2 via the antenna 1 and converted into an intermediate frequency (IF) signal. The IF signal output from the RF block 2 is A / D converted by the A / D converter 3. The output of the A / D converter 3 is input to a unique word detection circuit 4, a TMCC correlation value detection circuit 5, and a PSK demodulation circuit 6. The unique word detection circuit 4 detects a unique pattern as a frame synchronization signal from the input signal and outputs the detection result to the TMCC correlation value detection circuit 5.
[0026]
The TMCC correlation value detection circuit 5 detects the TMCC signal by calculating the correlation value of the input modulation signal in synchronization with the output of the unique word detection circuit 4, and further calculates the frequency deviation Δf between the TMCC signals. And output to the PSK demodulating circuit 6. The TMCC correlation value detection circuit 5 detects frame sync (synchronization) and outputs the detection signal to the Viterbi decoding circuit 8.
[0027]
FIG. 2 shows a configuration example of the TMCC correlation value detection circuit 5. The TMCC correlation value detection circuit 5 includes a threshold comparison unit 20, a frame sync output unit 30, a correlation value calculation unit 40, and a frequency conversion unit 50. In the threshold comparison unit 20, the threshold generation circuit 21 generates a signal indicating the set value and outputs it to the comparison circuit 22. The comparison circuit 22 compares the signal from the threshold generation circuit 21 with the signal from the addition circuit 45 of the correlation value calculation unit 40, and outputs the comparison result to the AND circuit 31 of the frame sync output unit 30. In the frame sync output unit 30, the AND circuit 31 performs an AND process on the signal from the comparison circuit 22 and the unique word detection signal from the unique word detection circuit 4, and converts the result into a frequency conversion between the Viterbi decoding circuit 8 and the frequency conversion unit 50. Output to the circuit 51.
[0028]
In the correlation value calculation unit 40, the delay circuit 41 delays the input received signal by a predetermined time and outputs it to the shift register 42. The received signal is input to the shift register 43 as it is. The shift register 42 has a resist set for one byte larger than the number of bytes (N) of the code length of the TMCC signal, and (N + 1) (42-1 to 42- (N + 1)) corresponding thereto. A book output terminal is provided. On the other hand, the shift resist 43 has a resist set for N bytes and is provided with N (43-1 to 43-N) output terminals corresponding thereto. The shift register 42 and the shift register 43 sequentially shift the input signal in synchronization with the clock, and supply the signal held at each timing to the multiplication circuit 44.
[0029]
The multiplication circuit 44 multiplies the corresponding bytes of the signals supplied from the shift register 42 and the shift register 43, but the signal supplied from the shift register 42 is received as the first multiplication condition. In order to extract the in-phase component of the modulation signal, the signal from the output terminals 42-1 to 42-N of the shift register 42 is multiplied by the signal from the output terminals 43-1 to 43-N of the shift register 43, and the addition is performed. Output to the circuit 45. Next, as a second multiplication condition, in order to extract the orthogonal component of the received modulation signal, the signal from the output terminals 42-2 to 42-(N + 1) of the shift register 42 and the shift register 43 The signals from the output terminals 43-1 to 43-N are multiplied and output to the adder circuit 45.
[0030]
The addition circuit 45 adds the signals from the multiplication circuit 44 and outputs the addition result to the comparison circuit 22 of the threshold value comparison unit 20 and the frequency conversion circuit 51 of the frequency conversion unit 50. The multiplication circuit 44 uses the first multiplication condition. When the addition circuit 45 adds the multiplication results, the addition circuit 45 outputs the addition result to the comparison circuit 22. When the multiplication circuit 44 multiplies under the second multiplication condition and the addition circuit 45 adds the multiplication results, the addition circuit 45 outputs the addition result to the frequency conversion circuit 51.
[0031]
In the frequency conversion unit 50, the frequency conversion circuit 51 performs a predetermined calculation on the signal from the addition circuit 45 and outputs the calculation result to the PSK demodulation circuit 6.
[0032]
Returning to FIG. 1, the PSK demodulation circuit 6 demodulates the input signal based on the outputs of the TMCC correlation value detection circuit 5 and the TMCC decoder 7 and outputs the demodulated signal to the Viterbi decoding circuit 8. The TMCC decoder 7 decodes the TMCC signal from the signal input from the Viterbi decoding circuit 8 and outputs the decoded result to the PSK demodulating circuit 6 and the Viterbi decoding circuit 8. The Viterbi decoding circuit 8 performs Viterbi decoding on the signal from the PSK demodulation circuit 6 based on the outputs of the TMCC decoder 7 and the TMCC correlation value detection circuit 5 and outputs the decoded result to the TMCC decoder 7 and the deinterleave circuit 9. .
[0033]
The deinterleave circuit 9 deinterleaves the signal from the Viterbi decoding circuit 8 and outputs it to the Reed-Solomon decoding circuit 10. The Reed-Solomon decoding circuit 10 decodes the Reed-Solomon code corresponding to the Reed-Solomon encoding on the transmission side. The MPEG decoder 11 performs an MPEG code decoding process on the signal from the Reed-Solomon decoding circuit 10 to reproduce a video digital signal and an audio digital signal. The D / A converter 12 D / A converts the signal from the MPEG decoder 11.
[0034]
Next, the operation will be described.
[0035]
A modulated signal transmitted by a carrier having a predetermined frequency via a predetermined transmission path is received by the RF block 2 via the antenna 1 and converted into an intermediate frequency (IF) signal. The IF signal output from the RF block 2 is A / D converted by the A / D converter 3. The output of the A / D converter 3 is input to the unique word detection circuit 4, the TMCC correlation value detection circuit 5, and the PSK demodulation circuit 6.
[0036]
The unique word detection circuit 4 detects a known data pattern arranged as a frame synchronization signal at the head of each frame, that is, a so-called unique word as a frame synchronization signal. When a unique word is detected, the detection signal is detected as a TMCC correlation value. The data is output to the AND circuit 31 of the detection circuit 5. The unique word detection circuit 4 can detect the frame synchronization by detecting the unique pattern of the frame synchronization signal.
[0037]
The TMCC signal is transmission control information, and its contents are not often changed. In most cases, the same contents are repeatedly transmitted. The TMCC correlation value detection circuit 5 uses this characteristic to detect TMCC signals repeatedly transmitted, calculates a correlation value between TMCC signals, and detects a frequency deviation Δθ from the phase difference Δθ at the detection timing of the TMCC signal. f is calculated and output to the PSK demodulating circuit 6.
[0038]
This principle will be described in detail with reference to FIG.
[0039]
In the correlation value calculation unit 40, a signal that is a modulation signal that is currently input and a signal that is a modulation signal delayed by one block (one frame) from the signals from the output terminals 43-1 to 43-N of the shift register 43. Signals from the output terminals 42-1 to 42-N (first multiplication condition) of the register 42 are multiplied in the multiplication circuit 44 and added in the addition circuit 45. This is to obtain the correlation value of the TMCC signal, and is maximized when the TMCC signal is input.
[0040]
The current modulation signal S1 (t) supplied from the shift register 43 is
S1 (t) = Acos (wt + θs1 + θ1)
The modulated signal S2 (t) delayed by one block (one frame) supplied from the shift resist 42 under the first multiplication condition is
S2 (t) = Acos (wt + θs2 + θ1 + θe)
It is expressed. In the above equation, A is the amplitude of the signal, w is the carrier angular frequency, t is the time, θs1 and θs2 are the signal phase, θ1 is the initial phase of the carrier, and θe is the frequency drift (frequency deviation) by the delay circuit 41. is there. Since θs1 is a BPSK modulated TMCC signal, 0 takes the value of π, and θs2 is θs1 when the TMCC signal is received (when the same contents are repeated in the TMCC signal). The same value as
[0041]
Multiplying the above two signals (corresponding to the processing in the multiplication circuit 44),
S1 (t) × S2 (t) = (Acos (wt + θs1 + θ1)) × (Acos (wt + θs2 + θ1 + θe))
^{= (A 2/2) ×} (cos (2wt + θs1 + θs2 + θ1 + θ1 + θe) + cos (θs1 over? S2 + .theta.1 over .theta.1 over .theta.e))
Furthermore, if the 2wt component that can be removed with a low-pass filter (not shown) is deleted,
S1 (t) × S2 (t ) = (A 2/2) × cos (θs1 over θs2 + θe) - (1)
It becomes. This corresponds to the result of multiplying 1 byte.
[0042]
Here, in the equation (1), when the TMCC signal is input, θs2 becomes the same value as θs1, so the multiplication result of 1 byte in the multiplication circuit 44 is
Multiplication result of 1 byte when TMCC signal of modulation signal is input
^{= (A 2/2) ×} cos ( over .theta.e)
^{= (A 2/2) ×} cos (θe)
It becomes the maximum value of the multiplication value of 1 byte. Next, the addition result in the addition circuit 45 in this case is
Addition result in the adder circuit ^{45 = (A 2/2)} × cos (θe) × N - (2)
This is also the maximum value of the addition value in the addition circuit 45.
[0043]
As described above, when the TMCC signal is input, the addition result in the addition circuit 45 becomes the largest, that is, the correlation value of the TMCC signal becomes the maximum. Therefore, when a predetermined value is substituted into θe in the equation (2), the calculated value is set as a threshold value, and the value output from the threshold value generation circuit 21 of the threshold value comparison unit 20, the signal from the addition circuit 45 is the TMCC signal. Since it becomes larger than the threshold value at the input timing, the comparison circuit 22 of the threshold value comparison unit 20 compares the signal from the addition circuit 45 with the magnitude of the signal (threshold value) from the threshold value generation circuit 21, whereby TMCC A signal can be detected.
[0044]
As described above, when the addition circuit 45 adds the multiplication results based on the first multiplication condition in the multiplication circuit 44, the addition circuit 45 outputs the addition result to the comparison circuit 22. When the correlation value from the adder circuit 45 exceeds the threshold value, the comparison circuit 22 outputs the detection signal of the TMCC signal to the AND circuit 31 of the frame sync output unit 30.
[0045]
When the TMCC signal is detected, the unique word detection circuit 4 should have detected a unique word (frame synchronization signal). The AND circuit 31 ANDs the detection signal from the comparison circuit 22 and the unique word detection signal from the unique word detection circuit 4 and outputs the result to the Viterbi decoding circuit 8 and the frequency conversion circuit 51 as a frame sync signal. .
[0046]
As described above, the TMCC signal is detected. Next, the phase difference of the TMCC signal is calculated to obtain the frequency deviation. In the correlation value calculation unit 40, a signal from the output terminals 43-1 to 43-N of the shift register 43, which is a currently input modulation signal, and a shift register 42, which is a modulation signal delayed by one block (one frame) this time. The signals from the output terminals 42-2 to 42- (N + 1) (second multiplication condition) are multiplied in the multiplication circuit 44 and added in the addition circuit 45. From this, the phase difference (Δθ) of the TMCC signal is obtained.
[0047]
The currently input modulation signal S1 (t) supplied from the shift register 43 is
S1 (t) = Acos (wt + θs1 + θ1)
The modulated signal S3 (t) delayed by one block (one frame) supplied from the shift register 42 under the second multiplication condition is
S3 (t) = Asin (wt + θs2 + θ1 + θe)
It is expressed. In the above equation, A is the amplitude of the signal, w is the angular frequency of the carrier, t is the time, θs1 and θs2 are the signal phase, θ1 is the initial phase of the carrier, and θe is the frequency drift (frequency deviation) by the delay circuit 41. is there. Since θs1 is a BPSK modulated TMCC signal, 0 takes the value of π, and θs2 is θs1 when the TMCC signal is received (when the same contents are repeated in the TMCC signal). The same value as
[0048]
Multiplying the above two signals (corresponding to the processing in the multiplication circuit 44),
S1 (t) × S3 (t) = (Acos (wt + θs1 + θ1)) × (Asin (wt + θs2 + θ1 + θe))
^{= (A 2/2) ×} (sin (2wt + θs1 + θs2 + θ1 + θ1 + θe) -sin (θs1 over? S2 + .theta.1 over .theta.1 over .theta.e))
Furthermore, if the 2wt component that can be removed with a low-pass filter (not shown) is deleted,
S1 (t) × S3 (t ) = (A 2/2) × sin (θs1 over? S2 + .theta.e)
It becomes. This is a result of multiplication of 1 byte, and the addition circuit 45 adds N bytes of multiplication results, and the addition result is the phase difference (Δθ) of the TMCC signal, and the frequency conversion of the frequency conversion unit 50 is performed. It is output to the circuit 51.
[0049]
The frequency conversion circuit 51 calculates the frequency knitting number Δf by the following equation based on the signal (Δθ) from the addition circuit 45 in synchronization with the frame sync signal from the AND circuit 31.
Δf = (Δθ / (cycle of TMCC signal)) × (1 / 2π)
Since the TMCC signal is received at the timing when the AND circuit 31 outputs the frame sync signal, the frequency conversion circuit 51 calculates the frequency deviation (Δf) of the TMCC signal when the TMCC signal is received. It will be. The calculated frequency deviation Δf is output to be supplied to the PSK demodulating circuit 6.
[0050]
The multiplication circuit 44 repeats multiplication by the first multiplication condition and the second multiplication condition every time the signals input to the shift registration 42 and the shift registration 43 are shifted.
[0051]
Based on such a principle, the TMCC correlation value detection circuit 5 detects TMCC signals repeatedly transmitted, calculates a correlation value between the TMCC signals, and deviates from the phase difference (Δθ) at the detection timing of the TMCC signal. Δf is calculated and output to the PSK demodulation circuit 6.
[0052]
The PSK demodulation circuit 6 determines the carrier frequency based on the frequency deviation Δf output from the TMCC correlation value detection circuit 5, and demodulates the modulation signal. Thus, the demodulation process can be executed with high accuracy. Further, the PSK demodulating circuit 6 demodulates each modulation signal based on the transmission control information extracted by the TMCC decoder 7 in accordance with the modulation method of the modulation signal. The frame synchronization signal and the TMCC signal are demodulated corresponding to BPSK, the low layer signal LQ is demodulated corresponding to QPSK, and the high layer signal HQ is demodulated corresponding to 8PSK.
[0053]
The TMCC decoder 7 decodes the TMCC signal from the signal input from the Viterbi decoding circuit 8 and extracts transmission control information such as a modulation method and a coding rate. The extracted result is the PSK demodulating circuit 6 and the Viterbi decoding circuit. 8 is output. Thereafter, the PSK demodulating circuit 6 and the Viterbi decoding circuit 8 process the input main signal in accordance with the transmission control information from the TMCC decoder 7.
[0054]
Next, the signal from the PSK demodulating circuit 6 is Viterbi decoded by the Viterbi decoding circuit 8. The Viterbi decoding circuit 8 performs a convolution decoding process corresponding to the transmission control signal output from the TMCC decoder 7 and the frame sync signal output from the TMCC correlation value detection circuit 5. The deinterleave circuit 9 deinterleaves the signal from the Viterbi decoding circuit 8 and then outputs the signal to the Reed-Solomon decoding circuit 10. The Reed-Solomon decoding circuit 10 performs Reed-Solomon decoding on the signal output from the deinterleave circuit 9 and outputs it to the MPEG decoder 11. The MPEG decoder 11 decodes a signal from the Reed-Solomon decoding circuit 10 and reproduces a video digital signal or an audio digital signal. The D / A converter 12 D / A converts the signal from the MPEG decoder 11.
[0055]
The above operation has been described based on an example in which the frequency deviation Δf is calculated using the entire TMCC signal. For example, TMCC signal 3-1 (the first byte of the third packet) and 4- The frequency deviation Δf can be calculated by combining signals of 1 (the first byte of the fourth packet), or the frequency deviation Δf can be calculated for each byte. Also, the frequency deviation can be weighted by the magnitude of the correlation value, that is, the control amount can be adaptively adjusted by the S / N ratio.
[0056]
As a transmission medium for transmitting a computer program for performing the above processing to a user, a communication medium such as a network or a satellite can be used in addition to a recording medium such as a magnetic disk, a CD-ROM, or a solid memory. .
[0057]
【The invention's effect】
According to the present invention, it is possible to generate a carrier having an accurate frequency and perform accurate demodulation.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration example of a receiving apparatus to which the present invention is applied.
2 is a block diagram showing a configuration example of a TMCC correlation value detection circuit 5 in FIG.
FIG. 3 is a diagram illustrating a data structure of a transmission frame.
FIG. 4 is a diagram illustrating a bit stream of a frame signal.
FIG. 5 is a block diagram illustrating a configuration example of a conventional receiving apparatus.
[Explanation of symbols]
1 antenna, 2 RF block, 3 A / D converter, 4 unique word detection circuit, 5 TMCC correlation value detection circuit, 6 PSK demodulation circuit, 7 TMCC decoder, 8 Viterbi decoding circuit, 9 deinterleave circuit, 10 Reed-Solomon decoding Circuit, 11 MPEG decoder, 12 D / A converter, 20 threshold comparison unit, 21 threshold generation circuit, 22 comparison circuit, 30 frame sync output unit, 31 AND circuit, 40 correlation value calculation unit, 41 delay circuit, 42 shift register , 43 shift register, 44 multiplication circuit, 45 addition circuit, 50 frequency conversion unit, 51 frequency conversion circuit, 61 frame synchronization detection circuit, 62 PSK demodulation circuit, 63 phase detection circuit, 64 Viterbi decoding circuit, 65 TMCC decoder, 66 data Interleave circuit, 67 Reed-Solomon decoding circuit, 68 MPEG decoder

Claims (4)

A plurality of packets including the main signal are encoded, two-dimensionally arranged to form a frame, and the carrier is modulated with a signal obtained by replacing the synchronization signal of the packet with a frame synchronization signal or another signal and transmitted. In a receiving device that receives a modulated signal,
Receiving means for receiving the transmitted modulated signal;
Correlation value calculating means for calculating a correlation value of the modulated signal received by the receiving means;
Frequency deviation calculating means for calculating the frequency deviation of the modulation signal received by the receiving means;
Frequency determining means for determining a frequency of a carrier for demodulating the modulated signal received by the receiving means based on the frequency deviation calculated by the frequency deviation calculating means;
With
The frequency determining means includes
A carrier frequency for demodulating the received modulated signal is determined based on a frequency deviation of the modulated signal whose correlation value is greater than a predetermined threshold.
A receiving apparatus. The threshold value calculation means and the frequency deviation calculation means calculate a correlation value and a frequency deviation between the modulation signals constituting the preceding and following frames.
  The receiving device according to claim 1. A plurality of packets including the main signal are encoded, two-dimensionally arranged to form a frame, and the carrier is modulated with a signal in which the synchronization signal of the packet is replaced with a frame synchronization signal or another signal and transmitted. In a receiving method for receiving a modulated signal,
  A receiving step for receiving the transmitted modulated signal;
  A correlation value calculating step of calculating a correlation value of the modulated signal received in the processing of the receiving step;
  A frequency deviation calculating step of calculating a frequency deviation of the modulated signal received in the processing of the receiving step;
  A frequency determining step for determining a frequency of a carrier for demodulating the modulation signal received in the processing in the receiving step based on the frequency deviation calculated in the processing in the frequency deviation calculating step;
  Including
  The frequency determination step includes
  A carrier frequency for demodulating the received modulated signal is determined based on a frequency deviation of the modulated signal whose correlation value is greater than a predetermined threshold.
  And a receiving method. A plurality of packets including the main signal are encoded, two-dimensionally arranged to form a frame, and the carrier is modulated with a signal in which the synchronization signal of the packet is replaced with a frame synchronization signal or another signal and transmitted. In a program for causing a computer to perform reception processing for receiving a modulated signal,
  A receiving step for receiving the transmitted modulated signal;
  A correlation value calculating step of calculating a correlation value of the modulated signal received in the processing of the receiving step;
  A frequency deviation calculating step of calculating a frequency deviation of the modulated signal received in the processing of the receiving step;
  A frequency determining step for determining a frequency of a carrier for demodulating the modulation signal received in the processing in the receiving step based on the frequency deviation calculated in the processing in the frequency deviation calculating step;
  Including
  The frequency determination step includes
  A carrier frequency for demodulating the received modulated signal is determined based on a frequency deviation of the modulated signal whose correlation value is greater than a predetermined threshold.
  A transmission medium for transmitting a program for causing a computer to execute reception processing.

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