JP2007028200A - Frame synchronization protection controller and method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frame synchronization protection controller and its method capable of achieving more stable frame synchronization protection. <P>SOLUTION: A state 3 is composed of a state 3(0, 0) to be a completely synchronized state in which synchronization is established and a forward protection state in which the other synchronization is established. In the state 3, the state is transited in accordance with a state transition diagram where the number of synchronization protection steps is "2" and the number of error protection steps is "2". A state machine 50 adds "1" to the number of synchronization protection steps when a synchronization decision signal is "NG", and adds "1" to the number of error protection steps when an error correction result signal is "NG". Then the state machine 50 calculates the number of forward protection steps which is the weighted sum of the number of synchronization protection steps and the number of error protection steps and compares the number of forward protection steps with a threshold to discriminate whether the number of forward protection steps is in a protection range or not. When the number of forward protection steps is in the protection range as the result of discrimination, the state is transited to a state corresponding to the present number of synchronization protection steps and the present number of error protection steps. When the number of forward protection steps is out of the protection range on the other hand, synchronization is canceled and the state is transited to a state 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a frame synchronization control apparatus and method suitable for use in demodulating a transmission data sequence from an orthogonal frequency division multiplexing (OFDM) signal.

  As a method for modulating digital data, a modulation method called an Orthogonal Frequency Division Multiplexing (OFDM) method (hereinafter referred to as an OFDM method) is known.

  In the OFDM method, a large number of orthogonal subcarriers (subcarriers) are provided in the transmission band, and data is assigned to the amplitude and phase of each subcarrier by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). Modulation method. Since the OFDM scheme divides the transmission band by a large number of subcarriers, the band per subcarrier wave becomes narrow and the modulation speed becomes slow, but the total transmission speed is the same as the conventional modulation system. is doing. In addition, in the OFDM scheme, since a number of subcarriers are transmitted in parallel, the symbol rate is slow, the time length of the multipath relative to the time length of the symbol can be shortened, and the multipath interference is not easily received. It has the characteristics. In addition, since the OFDM scheme allocates data to a plurality of subcarriers, an IFFT (Inverse Fast Fourier Transform) arithmetic circuit that performs inverse Fourier transform during modulation, and an FFT (Fast Fourier Transform) that performs Fourier transform during demodulation. ) It has a feature that a transmission / reception circuit can be configured by using an arithmetic circuit.

The OFDM system is often applied to terrestrial digital broadcasting that is strongly affected by multipath interference. The digital terrestrial broadcasting employing the OFDM method, for example, there are standards such as _{ISDB-T SB (Integrated Services Digital} Broadcasting -Terrestrial Sound Broadcasting) ( see Non-Patent Document 1).

Here, the ISDB- _TSB standard defines that a TMCC (Transmission and Multiplexing Configuration Control) signal subjected to differential BPSK modulation using 204-bit information as one unit is transmitted to a predetermined subcarrier in an OFDM symbol. Has been. In the differential BPSK modulation, a data string to be transmitted is differentially encoded, and (+4/3, 0) and (−4/3, 0) of information (0, 1) after differential encoding, respectively. This is a modulation system for converting a complex signal (I, Q signal) having signal points.

  The TMCC signal, which is a unit of 204-bit information, includes a 1-bit differential modulation reference signal, a 16-bit synchronization signal, a 3-bit segment format identification, 102-bit TMCC information, and 82 bits from the beginning. Of parity bits. The reference signal is a signal that becomes a reference amplitude and a reference phase of the differential modulation method. The synchronization signal is information indicating the head position of a 204-bit information unit. Specifically, W0 = “0011010111101110” and its inverted word W1 = “1100101000010001” are alternately inserted in units of frames. The segment format identification is information indicating whether transmission data is differentially modulated or synchronously modulated. The TMCC information is information indicating a carrier modulation scheme of a received signal, a time direction interleave pattern, a coding rate of a convolutional code, and the like. The parity bit is an error correction code for the TMCC information of 102 bits, and a shortened code (184, 102) of the difference set cyclic code (273, 191) is adopted as the system.

In the TMCC signal, 1-bit information is modulated for one OFDM symbol. Therefore, a TMCC signal, which is a unit of 204 bits, is transmitted every 204 OFDM symbols. In the ISDB- _TSB standard, a unit for transmitting this TMCC signal is called an OFDM frame.

Therefore, in the OFDM receiver compliant with the ISDB-T _SB standard, in order to demodulate the received transmission wave, first, the synchronization signal in the TMCC signal is detected and the OFDM frame is synchronized, and then in the TMCC signal After detecting various TMCC information and retrieving various setting information and performing various demodulation settings of the apparatus, demodulation of the entity information is started.

"Digital terrestrial audio broadcasting receiver standard (desired specification) ARIB STD-B30", The Radio Industry JP 2001-136158 A JP-A-11-298467

By the way, in an OFDM receiver compliant with the ISDB- _TSB standard, the synchronization word in the TMCC signal is usually detected and the OFDM frame is synchronized. However, in order to stabilize the frame synchronization protection, A method of performing frame synchronization protection using a decoding result of an error correction code in addition to a detection result has been proposed (see Patent Documents 1 and 2).

  However, in such a conventional frame synchronization protection control method, for example, a synchronization word is not detected, and a transition from a synchronous state to an asynchronous state is performed only when error correction fails, so that an erroneous synchronous state is maintained. This is not always sufficient for stable frame synchronization protection.

  The present invention has been proposed in view of such a conventional situation, and an object thereof is to provide a frame synchronization protection control apparatus and method for realizing more stable frame synchronization protection.

  In order to achieve the above-described object, a frame synchronization protection control apparatus according to the present invention performs synchronization protection control of the transmission frame based on a synchronization word included in the transmission frame and transmission control information encoded with error correction coding. A frame synchronization protection control device that detects a synchronization position based on the synchronization word and determines whether or not the synchronization position matches a synchronization position detected one frame before; Error correction means for performing error correction decoding on the information, and synchronization protection in the synchronization state in which synchronization of the transmission frame is established at least based on the determination result of the synchronization position and the success or failure of error correction based on the determination result of the error correction Synchronization state control means for performing control, the synchronization state control means, a first count value that counts the number of times the synchronization positions do not match, Ri If the value obtained from the second count value obtained by counting the number of times that the correction has failed is greater than a predetermined threshold value, characterized in that the transition from the synchronized state to the asynchronous state.

  The frame synchronization protection control method according to the present invention is a frame synchronization protection control method for performing synchronization protection control of the transmission frame based on a synchronization word included in the transmission frame and transmission control information encoded with error correction coding. A synchronization position is detected based on the synchronization word, a synchronization position determination step is performed to determine whether the synchronization position is detected one frame before, and the transmission control information is subjected to error correction decoding. An error correction step for determining success or failure of error correction, and a synchronization state control step for performing synchronization protection control at least in the synchronization state in which synchronization of the transmission frame is established based on the determination result of synchronization position and the success or failure of error correction In the synchronization state control step, a first count value that counts the number of times that the synchronization positions do not match, and the number of times error correction has failed If the value obtained from the second count value counted is larger than a predetermined threshold value, characterized in that the transition from the synchronized state to the asynchronous state.

  According to the frame synchronization protection control apparatus and method according to the present invention, the synchronization protection control in the synchronization state in which the synchronization of the transmission frame is established is performed independently using the determination result of the synchronization position and the success or failure of the error correction. Therefore, more stable frame synchronization protection can be realized.

  Hereinafter, an ISDB-T standard OFDM receiver to which the present invention is applied will be described as an embodiment of the present invention.

  FIG. 1 shows a block configuration diagram of OFDM receiving apparatus 10 in the present embodiment.

  As shown in FIG. 1, the OFDM receiver 10 includes an antenna 11, a tuner 12, a bandpass filter (BPF) 13, an A / D conversion circuit 14, a DC cancellation circuit 15, a digital orthogonal demodulation circuit 16, and , FFT operation circuit 17, frame detection / transmission control information decoding circuit 18, synchronization circuit 19, carrier demodulation circuit 20, frequency deinterleave circuit 21, time deinterleave circuit 22, demapping circuit 23, bit Deinterleave circuit 24, depuncture circuit 25, Viterbi decoding circuit 26, byte deinterleave circuit 27, spread signal removal circuit 28, transport stream generation circuit 29, RS decoding circuit 30, channel selection circuit 31 It has.

  A transmission wave transmitted from the OFDM transmitter is received by the antenna 11 of the OFDM receiver 10 and supplied to the tuner 12 as an RF signal.

  The RF signal received by the antenna 11 is frequency-converted into an IF signal by a tuner 12 including a multiplier 12a and a local oscillator 12b, and is supplied to the BPF 13. The oscillation frequency of the reception carrier signal oscillated from the local oscillator 12 b is switched according to the channel selection signal supplied from the channel selection circuit 31.

  The IF signal output from the tuner 12 is filtered by the BPF 13 and then digitized by the A / D conversion circuit 14. The digitized IF signal has its DC component removed by the DC cancellation circuit 15 and is supplied to the digital quadrature demodulation circuit 16.

  The digital orthogonal demodulation circuit 16 orthogonally demodulates the digitized IF signal using a carrier signal having a predetermined frequency (carrier frequency), and outputs a baseband OFDM signal. As a result of orthogonal demodulation, the baseband OFDM signal becomes a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). The baseband OFDM signal output from the digital quadrature demodulation circuit 16 is supplied to the FFT operation circuit 17 and the synchronization circuit 19.

  The FFT operation circuit 17 performs an FFT operation on the baseband OFDM signal, and extracts and outputs a signal that is orthogonally modulated on each subcarrier. The FFT operation circuit 17 extracts a signal for an effective symbol length from one OFDM symbol, and performs an FFT operation on the extracted signal. That is, the FFT operation circuit 17 removes a signal corresponding to the guard interval length from one OFDM symbol, and performs an FFT operation on the remaining signal.

  The signal modulated by each subcarrier extracted by the FFT operation circuit 17 is a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). The signal extracted by the FFT operation circuit 17 is supplied to the frame detection / transmission control information decoding circuit 18, the synchronization circuit 19, and the carrier demodulation circuit 20.

  The frame detection / transmission control information decoding circuit 18 extracts a TMCC signal from a predetermined subcarrier of the signal demodulated by the FFT operation circuit 17, detects a synchronization signal from the TMCC signal, detects an OFDM frame boundary, and detects A frame synchronization signal indicating the boundary position of the frame is supplied to the synchronization circuit 19 and the like. Further, the frame detection / transmission control information decoding circuit 18 performs error correction decoding on TMCC information (transmission control information) included in the TMCC signal after synchronization with a difference set cyclic code. The frame detection / transmission control information decoding circuit 18 supplies the decoded TMCC information to the carrier demodulation circuit 20, the time deinterleaving circuit 22, the demapping circuit 23, the bit deinterleaving circuit 24, and the transport stream generating circuit 29. Then, control such as demodulation and reproduction of each circuit is performed.

  The synchronization circuit 19 uses a baseband OFDM signal, a signal modulated on each subcarrier after being demodulated by the FFT operation circuit 17, an OFDM symbol boundary, a channel selection signal supplied from the channel selection circuit 31, and the like. Thus, various types of synchronization processing such as synchronization processing of the FFT calculation calculation range and its timing are performed on the FFT calculation circuit 17.

  The carrier demodulation circuit 20 is supplied with the demodulated signal from each subcarrier output from the FFT operation circuit 17 and performs carrier demodulation on the signal. Specifically, the carrier demodulation circuit 20 performs differential demodulation processing on the differential modulation signal (DQPSK) and equalization processing on the synchronous modulation signal (QPSK, 16QAM, 64QAM).

  The carrier demodulated signal is deinterleaved in the frequency direction by the frequency deinterleave circuit 21, subsequently deinterleaved in the time direction by the time deinterleave circuit 22, and then supplied to the demapping circuit 23. .

The demapping circuit 23 performs data reassignment processing (demapping processing) on the carrier demodulated signal (complex signal) to restore the transmission data sequence. For example, in the case of demodulating an OFDM signal conforming to the ISDB- _TSB standard, the demapping circuit 23 performs demapping processing corresponding to QPSK, 16QAM, or 64QAM.

  The transmission data sequence output from the demapping circuit 23 passes through the bit deinterleave circuit 24, the depuncture circuit 25, the Viterbi decoding circuit 26, the byte deinterleave circuit 27, and the spread signal removal circuit 28, thereby causing an error in the multilevel symbol. Deinterleaving processing corresponding to bit interleaving for distribution, depuncturing processing corresponding to puncturing processing for reducing transmission bits, Viterbi decoding processing for decoding convolutionally encoded bit strings, in byte units Energy despreading processing corresponding to deinterleaving processing and energy diffusion processing is performed and input to the transport stream generation circuit 29.

  The transport stream generation circuit 29 inserts data defined by each broadcasting system, such as a null packet, at a predetermined position in the stream. In addition, the transport stream generation circuit 29 performs so-called smoothing processing in which the bit interval of the intermittently supplied stream is smoothed to make a temporally continuous stream. The transmission data sequence subjected to the smoothing process is supplied to the RS decoding circuit 30.

  The RS decoding circuit 30 performs a Reed-Solomon decoding process on the input transmission data series and outputs it as a transport stream defined by MPEG-2 Systems.

  Next, the frame detection / transmission control information decoding circuit 18 will be further described.

  FIG. 2 is a block diagram of the frame detection / transmission control information decoding circuit 18.

  As shown in FIG. 2, the frame detection / transmission control information decoding circuit 18 includes a differential demodulation circuit 41, a bit determination circuit 42, a frame synchronization determination circuit 43, a synchronization position storage unit 44, a comparison circuit 45, A delay circuit 46, a mismatch signal determination unit 47, an error correction circuit 48, and a synchronization control circuit 49 are provided.

  The frame detection / transmission control information decoding circuit 18 receives a TMCC signal (I, Q signal) modulated on a predetermined subcarrier of the OFDM symbol.

  The differential demodulation circuit 41 differentially demodulates the input TMCC signal and generates a complex signal (I, Q signal) at a signal point corresponding to the original information bit. The differentially demodulated signals (I and Q signals) are supplied to the bit determination circuit 42.

  The bit determination circuit 42 performs bit determination based on the differentially demodulated signals (I and Q signals). That is, it is determined whether the value modulated from the signal point on the IQ plane of the differentially demodulated signal is “0” or “1”, and one of the bit values is output. Accordingly, the bit determination circuit 42 outputs a TMCC signal that has been converted into a bit stream. The bit stream TMCC signal output from the bit determination circuit 42 is supplied to the frame synchronization determination circuit 43 and the delay circuit 46.

  The frame synchronization determination circuit 43 detects a synchronization word included in the bit stream TMCC signal and detects a synchronization position of the OFDM frame. Specifically, the frame synchronization determination circuit 43 first performs a correlation operation between the bit stream TMCC signal and the synchronization word (W0, W1). That is, the correlation value between the synchronization word (W0, W1) and the 16-bit width data string at each position in the bitstream is sequentially calculated. This correlation value is the highest value when the synchronization word (W0, W1) matches the bit string. Next, the frame synchronization determination circuit 43 detects a synchronization position that represents the timing at which the calculated correlation value is maximized. The detected synchronization position is supplied to the synchronization position storage unit 44, the comparison circuit 45, and the delay circuit 46.

  The synchronization position storage unit 44 stores and holds the synchronization position detected by the frame synchronization determination circuit 43. When the synchronization position of the next OFDM frame is supplied from the frame synchronization determination circuit 43, the synchronization position storage unit 44 outputs the held synchronization position to the comparison circuit 45.

  The comparison circuit 45 compares the synchronization position of a certain OFDM frame supplied from the frame synchronization determination circuit 43 with the synchronization position of the previous OFDM frame supplied from the synchronization position storage unit 44, and whether or not the synchronization positions match. To detect. Based on this detection result, the comparison circuit 45 outputs to the synchronization control circuit 49 a synchronization determination signal indicating “OK” if the synchronization positions match, and “NG” if they do not match.

  The delay circuit 46 is a circuit that delays the TMCC signal (bit stream) by the time required for the frame synchronization determination circuit 43 to detect the synchronization position. The TMCC signal delayed by a predetermined time by the delay circuit 46 and synchronized by the synchronization position supplied from the frame synchronization determination circuit 43 is supplied to the mismatch signal determination unit 47 and the error correction circuit 48.

  The mismatch signal determination unit 47 determines whether the TMCC signal converted into a bit stream is a signal that cannot occur in the system. Based on the determination result, the mismatch signal determination unit 47 outputs to the synchronization control circuit 49 a mismatch determination signal indicating “NG” if the signal is not possible in the system, and “OK” otherwise. To do. For example, when the TMCC signal is all 0, since there is a high possibility of signal disconnection or the like, the mismatch signal determination unit 47 outputs a mismatch determination signal indicating “NG” to the synchronization control circuit 49.

  The error correction circuit 48 performs error correction decoding on the TMCC information included in the bit streamed TMCC signal using a difference set cyclic code, and outputs the decoded TMCC information to the carrier demodulation circuit 20 or the like. Further, the error correction circuit 48 outputs an error correction success / failure signal indicating success / failure of the error correction to the synchronization control circuit 49. The error correction success / failure signal indicates “OK” if the error correction is successful, and “NG” if the error correction fails.

  The synchronization control circuit 49 controls the output of the frame synchronization signal and the synchronization establishment information based on the synchronization determination signal, the mismatch determination signal, and the error correction success / failure signal. The frame synchronization signal is a flag that periodically generates the boundary position of the OFDM frame such that it becomes “H” (high) at the timing of the start position of the OFDM frame and “L” (low) at other timings. . The synchronization control circuit 49 generates a first flag when a certain trigger is given (the flag is set to “H” (high)), and thereafter generates a flag periodically by counting, for example, an operation clock. Then, a frame synchronization signal is generated. The synchronization establishment information is information for notifying an external circuit whether or not the frame synchronization signal is synchronized with the received signal, that is, information indicating whether or not frame synchronization is established. The synchronization establishment information indicates “OK” if frame synchronization is established, and “NG” if it is not established.

  In the synchronization control circuit 49, the output of the frame synchronization signal and the output of the synchronization establishment information are controlled by the state machine 50 having the state transition diagram as shown in FIG. Hereinafter, the state machine 50 will be described.

  States 0 to 2 are backward protection states in which the synchronization of the OFDM frame is not established. In the state 0 to the state 2, the synchronization control circuit 49 does not output the frame synchronization signal, and further notifies the outside that the frame synchronization is not established by setting the synchronization establishment signal to “NG”.

  State 3 is a state 3 (0, 0) that is a complete synchronization state in which synchronization is established, a state 3 (0, 1) that is a forward protection state in which synchronization is established, and a state 3 (0, 2). , State 3 (1, 0), state 3 (2, 0), and state 3 (1, 1). In this state 3, as shown in FIG. 3, the state transitions according to a substantially triangular state transition diagram having two synchronization protection stages and two error protection stages. In the state 3, the synchronization control circuit 49 outputs a frame synchronization signal, and further notifies the outside that the frame synchronization is established by setting the synchronization establishment signal to “OK”.

  In the state machine 50, transitions between the states 0 to 3 are performed under the conditions shown in the flowchart of FIG.

  First, when the synchronization control circuit 49 is reset, the state machine 50 transitions to the initial state 0 (step S1). When bits for one ODFM frame are accumulated in the frame synchronization determination circuit 43 (step S2), the state transitions to the state 1 that is the correlation value calculation state (step S3).

  Next, when the frame synchronization determination circuit 43 calculates the correlation value and detects the maximum value of the correlation value (step S4), the state machine 50 transitions to state 2 which is the synchronization pull-in state (step S5). At this time, the delay circuit 46 synchronizes the ODFM frame by shifting the head position of the ODFM frame to a position where the correlation value is maximized (step S6).

  In the state 2, the state machine 50 determines the mismatch determination signal and the error correction success / failure signal (steps S6 and S7). If the error correction success / failure signal indicates “NG” or the error correction success / failure signal indicates “OK”, the state machine 50 returns to the state 1 again when the inconsistency determination signal indicates “NG”. Transition to. On the other hand, when both the error correction success / failure signal and the mismatch determination signal indicate “OK”, the state transits to the state 3 (0, 0), which is a complete synchronization state, and TMCC information is output (step S9). .

  Subsequently, when the frame synchronization determination circuit 43 calculates the correlation value and detects the maximum value of the correlation value (step S10), the state machine 50 determines the synchronization determination signal and the error correction success / failure signal (steps S11 and S13). . When the synchronization determination signal indicates “NG”, the state machine 50 adds 1 to the number of synchronization protection stages as the first count value, and when the error correction success / failure signal indicates “NG”. Adds 1 to the number of error protection stages as the second count value (steps S12 and S14).

  Thereafter, the state machine 50 calculates the number of forward protection steps, which is a weighted sum of the number of synchronization protection steps and the number of error protection steps (step S15), and compares the number of forward protection steps with a threshold value to determine whether or not it is within the protection range. Is determined (step S16). This threshold is such that if the weighted sum is less than or equal to the threshold, the corresponding state is present in state 3, and if the weighted sum is greater than the threshold, the corresponding state is not present in state 3. Set to the correct value. If the state machine 50 is within the protection range as a result of determination, the state machine 50 transitions to a state corresponding to the current number of synchronization protection stages and error protection stages. That is, when the current number of synchronization protection stages is i and the number of error protection stages is j, the state transitions to state 3 (i, j). On the other hand, if it is not within the protection range, that is, if there is no state 3 (i, j) corresponding to the current synchronization protection stage number i and error protection stage number j, the synchronization is removed and the state transitions to state 1.

  In each state of state 3, when both the synchronization determination signal and the error correction success / failure signal indicate “OK”, the number of synchronization protection stages and the number of error protection stages are initialized to 0, and the state is in a completely synchronized state Transition to 3 (0, 0). Furthermore, since the error correction success / failure signal indicates “OK”, the TMCC information is updated.

  As described above, in the state machine 50 in the synchronization control circuit 49, the number of synchronization protection stages and the number of error protection stages are set independently to perform forward synchronization protection control.

  Here, in the state machine 50 described above, the number of synchronization protection stages and the number of error protection stages are set to two, but each is set to an arbitrary number of stages according to the strength of the frame structure of the OFDM frame and the error correction capability. be able to. As a result, the synchronization control circuit 49 can realize more stable frame synchronization protection. Further, more stable frame synchronization protection can be realized by changing the number of synchronization protection stages and the number of error protection stages depending on the reception state of the OFDM receiver 10, bit error rate, or fixed reception / mobile reception. .

  In the above description, in the control between the states of state 3, when only one of the synchronization determination signal and the error correction success / failure signal indicates “OK”, the state is not changed. Of the synchronization determination signal and the error correction success / failure signal, 1 may be subtracted from the number of protection stages indicating “OK”, and the corresponding state may be changed.

  Next, a first modification of the state machine in the synchronization control circuit 49 will be described.

  FIG. 5 shows a state transition diagram of the state machine 60 in the first modification. Since the state 0 to the state 2 are backward protection states in which the synchronization of the OFDM frame is not established and are the same as the state 0 to the state 2 of the state machine 50 described above, description thereof is omitted. State 3-0 is a fully synchronized state in which synchronization is established, and states 3-1 to 3-α are forward protection states in which synchronization is established.

  In each of the states 3-0 to 3-α, when the frame synchronization determination circuit 43 calculates the correlation value and detects the maximum correlation value, the state machine 60 determines the synchronization determination signal and the error correction success / failure signal. To do. The state machine 60 adds 1 to the number of protection stages both when the synchronization determination signal indicates “NG” and when the error correction success / failure signal indicates “NG”. Therefore, in state 3-i, when only one of the synchronization determination signal and the error correction success / failure signal indicates “NG”, the state transitions to state 3- (i + 1), and the synchronization determination signal and the error correction success / failure signal When both indicate “NG”, the state transits to 3- (i + 2). In particular, when the error correction success / failure signal indicates “OK”, the TMCC information is updated.

  When both the synchronization determination signal and the error correction success / failure signal indicate “NG” in the state 3- (α−1), the state machine 60 loses synchronization because the state 3- (α + 1) does not exist. To state 1. Similarly, if any one of the synchronization determination signal and the error correction success / failure signal indicates “NG” in the state 3-α, the synchronization is removed and the state transitions to the state 1.

  Even in the first modification as described above, more stable frame synchronization protection can be realized.

  Next, a second modification of the state machine in the synchronization control circuit 49 will be described.

  FIG. 6 shows a state transition diagram of the state machine 70 in the second modification. Since the state 0 to the state 2 are backward protection states in which the synchronization of the OFDM frame is not established and are the same as the state 0 to the state 2 of the state machine 50 described above, description thereof is omitted. State 3-0 is a complete synchronization state in which synchronization is established, and states 3-1 to 3-β are forward protection states in which synchronization is established.

  In each of the states 3-0 to 3-β, when the frame synchronization determination circuit 43 calculates the correlation value and detects the maximum correlation value, the state machine 70 determines the synchronization determination signal and the error correction success / failure signal. To do. When either one of the synchronization determination signal and the error correction success / failure signal indicates “NG”, the state machine 70 adds 1 to the number of protection stages. Therefore, in state 3-i, if either of the synchronization determination signal and the error correction success / failure signal indicates “NG”, the state transitions to state 3- (i + 1). In particular, when the error correction success / failure signal indicates “OK”, the TMCC information is updated.

  If any one of the synchronization determination signal and the error correction success / failure signal indicates “NG” in state 3-β, state 3- (β + 1) does not exist, and therefore the state machine 70 is out of synchronization. Transition to 1.

  Even in the second modified example as described above, more stable frame synchronization protection can be realized.

  In the above description, when the error correction success / failure signal indicates “OK”, the TMCC information is updated. However, since the reliability of error correction is low in the forward protection state, the TMCC information is updated. The TMCC information in the completely synchronized state may be held continuously.

  Although the best mode for carrying out the present invention has been described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Of course.

It is a block block diagram of the OFDM receiver in this Embodiment. It is a block block diagram of the frame detection / transmission control information decoding circuit in the said OFDM receiver. It is a figure which shows an example of the state machine in the synchronous control circuit in the said frame detection / transmission control information decoding circuit. It is a flowchart explaining the state transition in the said state machine. It is a figure which shows the 1st modification of the state machine in the said synchronous control circuit. It is a figure which shows the 2nd modification of the state machine in the said synchronous control circuit.

Explanation of symbols

10 OFDM receiver, 18 frame detection / transmission control information decoding circuit, 41 differential demodulation circuit, 42 bit determination circuit, 43 frame synchronization determination circuit, 44 synchronization position storage unit, 45 comparison circuit, 46 delay circuit, 47 mismatch signal Determination unit, 48 error correction circuit, 49 synchronization control circuit, 50, 60, 70 state machine

Claims (5)

A frame synchronization protection control device for performing synchronization protection control of the transmission frame based on a synchronization word included in the transmission frame and transmission control information encoded with error correction coding,
Synchronization position determination means for detecting a synchronization position based on the synchronization word and determining whether or not the synchronization position matches the synchronization position detected one frame before;
Error correction decoding the transmission control information, error correction means for determining the success or failure of the error correction,
Synchronization state control means for performing synchronization protection control in at least a synchronization state in which synchronization of the transmission frame is established based on the determination result of the synchronization position and the success or failure of error correction;
The synchronization state control means is configured such that a value obtained from a first count value that counts the number of times that the synchronization positions do not match and a second count value that counts the number of times that error correction has failed is less than a predetermined threshold value. A frame synchronization protection control device characterized by transitioning from a synchronous state to an asynchronous state when larger.   2. The synchronization state control means subtracts the number of times that the synchronization positions coincide with each other from the first count value, and subtracts the number of times error correction has been successfully performed from the second count value. Frame synchronization protection control device.   The synchronization state control means initializes the first count value and the second count value to 0 when the synchronization positions match and error correction is successful. 1. The frame synchronization protection control device according to 1.   2. The frame synchronization protection control apparatus according to claim 1, wherein the synchronization state control means compares a weighted sum of the first count value and the second count value with the predetermined threshold value. A frame synchronization protection control method for performing synchronization protection control of the transmission frame based on a synchronization word included in the transmission frame and transmission control information encoded with error correction coding,
A synchronization position determination step of detecting a synchronization position based on the synchronization word and determining whether or not the synchronization position matches with the synchronization position detected one frame before;
An error correction step of performing error correction decoding on the transmission control information and determining success or failure of error correction;
A synchronization state control step for performing synchronization protection control in at least a synchronization state in which synchronization of the transmission frame is established based on a determination result of synchronization position and success or failure of error correction;
In the synchronization state control step, a value obtained from the first count value that counts the number of times that the synchronization positions do not match and the second count value that counts the number of times that error correction has failed is greater than a predetermined threshold value. A frame synchronization protection control method characterized by transitioning from a synchronous state to an asynchronous state when the value is large.

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