JP2008099263A - Frame synchronization control device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high-speed and stable operation by solving the following problem: in a conventional frame synchronization protection control method, transition is made from a synchronous state to an asynchronous state only when, for example, a synchronous word cannot be detected and error correction fails, so that erroneous synchronous state may be maintained, and it is insufficient for frame synchronization protection. <P>SOLUTION: A first frame synchronization control part 50 establishes frame synchronization by detecting a synchronous word from TMCC data demodulated from a received digital broadcast signal, and a second frame synchronization control part 60 establishes frame synchronization by obtaining correlation between the TMCC data demodulated from the received digital broadcast signal and one or more reference data of at least a part of predicted TMCC data. When the synchronization is established by the first frame synchronization control part 50, a selector block 70 switches the second frame synchronization control part 60 to the first frame synchronization control part 50. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a frame synchronization control apparatus and a frame synchronization control method suitable for use in demodulating a transmission data sequence from an orthogonal frequency division multiplexing (OFDM) signal.

  As a method for modulating digital data, a modulation method called an Orthogonal Frequency Division Multiplexing (OFDM) method (hereinafter referred to as an OFDM method) is known.

  In the OFDM method, a large number of orthogonal subcarriers (subcarriers) are provided in the transmission band, and data is assigned to the amplitude and phase of each subcarrier by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). Modulation method. Since the OFDM scheme divides the transmission band by a large number of subcarriers, the band per subcarrier wave becomes narrow and the modulation speed becomes slow, but the total transmission speed is the same as the conventional modulation system. is doing. In addition, in the OFDM scheme, since a number of subcarriers are transmitted in parallel, the symbol rate is slow, the time length of the multipath relative to the time length of the symbol can be shortened, and the multipath interference is not easily received. It has the characteristics. In addition, since the OFDM scheme allocates data to a plurality of subcarriers, an IFFT (Inverse Fast Fourier Transform) arithmetic circuit that performs inverse Fourier transform during modulation, and an FFT (Fast Fourier Transform) that performs Fourier transform during demodulation. ) It has a feature that a transmission / reception circuit can be configured by using an arithmetic circuit.

  The OFDM system is often applied to terrestrial digital broadcasting that is strongly affected by multipath interference. As terrestrial digital broadcasting employing the OFDM system, for example, there is a standard such as ISDB-TSB (Integrated Services Digital Broadcasting-Terrestrial Sound Broadcasting) (see Non-Patent Document 1).

  Here, in the ISDB-TSB standard, differential BPSK modulation using 204-bit information as a unit as a control signal for transmitting information about the type of modulation scheme currently used, the error correction coding rate, and the like to the receiver. It is defined that a transmitted transmission and multiplexing configuration control (TMCC) signal is transmitted to a predetermined subcarrier in an OFDM symbol. In the differential BPSK modulation, a data string to be transmitted is differentially encoded, and (+4/3, 0) and (−4/3, 0) of information (0, 1) after differential encoding, respectively. This is a modulation system for converting a complex signal (I, Q signal) having signal points.

  The TMCC signal, which is a unit of 204-bit information, includes a 1-bit differential modulation reference signal, a 16-bit synchronization signal, a 3-bit segment format identification, 102-bit TMCC information, and 82 bits from the beginning. Of parity bits. The reference signal is a signal that becomes a reference amplitude and a reference phase of the differential modulation method. The synchronization signal is information indicating the head position of a 204-bit information unit. Specifically, W0 = “0011010111101110” and its inverted word W1 = “1100101000010001” are alternately inserted in units of frames.

  The segment format identification is information indicating whether transmission data is differentially modulated or synchronously modulated.

  The TMCC information is information that assists the demodulation and decoding operations of the receiver, such as system information, transmission parameter switching index, emergency warning broadcast activation flag, current information, and next information. Current information indicates the current hierarchical configuration and transmission parameters, and next information indicates the transmission parameters after switching. The transmission parameters include a carrier modulation scheme (3 bits), a convolutional coding rate (3 bits), an interrib length (3 bits), and the number of segments (4 bits).

  The parity bit is an error correction code for the TMCC information of 102 bits, and a shortened code (184, 102) of the difference set cyclic code (273, 191) is adopted as the system.

  In the TMCC signal, 1-bit information is modulated for one OFDM symbol. Therefore, a TMCC signal, which is a unit of 204 bits, is transmitted every 204 OFDM symbols. In the ISDB-TSB standard, a unit for transmitting this TMCC signal is called an OFDM frame.

  Therefore, in the OFDM receiver corresponding to the ISDB-TSB standard, in order to demodulate the received transmission wave, first, the synchronization signal in the TMCC signal is detected to synchronize the OFDM frame, and then, in the TMCC signal. After detecting TMCC information and extracting various setting information and performing various demodulation settings of the apparatus, demodulation of the entity information is started.

"Digital terrestrial audio broadcasting receiver standard (desired specification) ARIB STD-B30", The Radio Industry JP 2001-136158 A JP-A-11-298467

  By the way, in an OFDM receiver compliant with the ISDB-TSB standard, a synchronization word in a TMCC signal is usually detected to synchronize the OFDM frame. However, in order to stabilize frame synchronization protection, detection of a synchronization word has been conventionally performed. In addition to the result, a method of performing frame synchronization protection using a decoding result of an error correction code has been proposed (see Patent Documents 1 and 2).

  However, in such a conventional frame synchronization protection control method, for example, a synchronization word is not detected, and a transition from a synchronous state to an asynchronous state is performed only when error correction fails, so that an erroneous synchronous state is maintained. This is not always sufficient for stable frame synchronization protection.

  Therefore, the present applicant has previously proposed a frame synchronization protection control apparatus and method for realizing more stable frame synchronization protection as Japanese Patent Application No. 2005-207416.

  However, in the frame synchronization protection control device, frame synchronization is established (a flag in which some frame synchronization is established at the timing of receiving the head of the frame (symbol number 0) (hereinafter referred to as a frame synchronization flag or simply a synchronization flag). The minimum number of symbols (number of frames) required to output a maximum of 407 symbols (about 2 frames, 1 frame is 204 symbols), the maximum is 610 symbols (about 3 frames), and the average is 508.5 symbols (about 2.5 frames). Since post-processing cannot be performed unless frame synchronization is established, the frame synchronization time greatly affects the time from the start of operation of the digital broadcast receiving apparatus until the final data is normally output.

  An object of the present invention is to provide a frame synchronization control apparatus and a frame synchronization control method that have been proposed in view of such conventional circumstances and that operate stably at high speed.

  Other objects of the present invention and specific advantages obtained by the present invention will become more apparent from the description of embodiments described below.

  In order to achieve the above-described object, the present invention performs high-speed frame synchronization control using correlation values between actual reception control data and a plurality of reference data of channel control information in a digital broadcast receiving apparatus.

  That is, the frame synchronization control device according to the present invention includes TMCC data holding means for holding transmission and multiplexing configuration control (TMCC) data demodulated from the received digital broadcast signal, and demodulated from the received digital broadcast signal. First frame synchronization control means for establishing a frame synchronization by detecting a synchronization word from the TMCC data held in the TMCC data and the TMCC data held in the TMCC data holding means, and one or more of at least a part of expected TMCC information When the reference data is held, reference data holding means, and second frame synchronization for establishing a frame synchronization by obtaining a correlation between the TMCC data held in the TMCC data holding means and the reference data held in the reference data holding means A control means; and Synchronization control switching means for switching from the synchronization control by the second frame synchronization control means to the first frame synchronization control means from the synchronization control when the frame synchronization by the frame synchronization control means is established. And

  The frame synchronization control method according to the present invention includes a first frame synchronization control for detecting a synchronization word from TMCC data demodulated from a received digital broadcast signal and establishing frame synchronization, and a demodulation from the received digital broadcast signal. Second frame synchronization control for establishing a frame synchronization by obtaining a correlation between the TMCC data and one or more reference data of at least a part of the expected TMCC information, and performing the frame synchronization by the first frame synchronization control. When the first frame synchronization control is established, the second frame synchronization control is switched to the first frame synchronization control.

  According to the present invention, at the start of operation, the frame synchronization is immediately established by the second frame synchronization control using the correlation between the received TMCC information and the reference data, and the digital broadcast signal received by the first frame synchronization control is received. When the synchronization word is detected from the TMCC data demodulated from the above and frame synchronization is established, switching to the first frame synchronization control enables high-speed and highly reliable frame synchronization.

  Further, by increasing the number of symbols to be correlated, it becomes possible to further increase the reliability of frame synchronization, and it is possible to stably establish frame synchronization even when the noise level is high.

  In addition, by predicting TMCC information to be received in advance and preparing one or more reference data, it is possible to flexibly cope with changes in TMCC information on the transmission side.

  Normally, the received TMCC information differs depending on the selected channel, but by outputting the received TMCC information as it is to the external control unit, the external control unit references this TMCC information at the next channel selection. Can be entered as data. At this time, if there is an error in the portion of the received TMCC information that is error-protected by differential-set cyclic coding, the TMCC information that is not appropriate is output as reference data at the next channel selection. It is desirable to output TMCC information only when a flag indicating that error correction has not been performed at the time of decoding is established for the TMCC information.

  Further, the frame synchronization method using the correlation between the received TMCC information and the reference data is expected to have a lower correlation value with respect to the received TMCC information having an error, and the received TMCC information is assigned to which of the reference data. If it does not match, it will be difficult or impossible to establish frame synchronization. Therefore, as in the case of the conventional frame synchronization control method, it is necessary to detect synchronization words or succeed in differential cyclic decoding. It is desirable to use it together with a method for establishing more reliable frame synchronization. By doing this, at the start of operation, frame synchronization is immediately established using the frame synchronization method using the correlation between the received TMCC information and the reference data. When frame synchronization is established in the conventional method, switching to the conventional method is performed. High-speed and highly reliable frame synchronization can be performed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following examples, and it is needless to say that the present invention can be arbitrarily changed without departing from the gist of the present invention.

  Hereinafter, an ISDB-T standard OFDM receiver to which the present invention is applied will be described as an embodiment of the present invention.

  The present invention is applied to an OFDM receiver 10 having a configuration as shown in FIG. 1, for example.

  1 includes an antenna 11, a tuner 12, a bandpass filter (BPF) 13, an A / D conversion circuit 14, a DC cancellation circuit 15, a digital orthogonal demodulation circuit 16, and an FFT operation. Circuit 17, frame detection / transmission control information decoding circuit 18, synchronization circuit 19, carrier demodulation circuit 20, frequency deinterleave circuit 21, time deinterleave circuit 22, demapping circuit 23, and bit deinterleave circuit 24, a depuncture circuit 25, a Viterbi decoding circuit 26, a byte deinterleaving circuit 27, a spread signal removal circuit 28, a transport stream generation circuit 29, an RS decoding circuit 30, and a channel selection circuit 31. Yes.

  A transmission wave transmitted from the OFDM transmitter is received by the antenna 11 of the OFDM receiver 10 and supplied to the tuner 12 as an RF signal.

  The RF signal received by the antenna 11 is frequency-converted into an IF signal by a tuner 12 including a multiplier 12a and a local oscillator 12b, and is supplied to the BPF 13. The oscillation frequency of the reception carrier signal oscillated from the local oscillator 12 b is switched according to the channel selection signal supplied from the channel selection circuit 31.

  The IF signal output from the tuner 12 is filtered by the BPF 13 and then digitized by the A / D conversion circuit 14. The digitized IF signal has its DC component removed by the DC cancellation circuit 15 and is supplied to the digital quadrature demodulation circuit 16.

  The digital orthogonal demodulation circuit 16 orthogonally demodulates the digitized IF signal using a carrier signal having a predetermined frequency (carrier frequency), and outputs a baseband OFDM signal. As a result of orthogonal demodulation, the baseband OFDM signal becomes a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). The baseband OFDM signal output from the digital quadrature demodulation circuit 16 is supplied to the FFT operation circuit 17 and the synchronization circuit 19.

  The FFT operation circuit 17 performs an FFT operation on the baseband OFDM signal, and extracts and outputs a signal that is orthogonally modulated on each subcarrier. The FFT operation circuit 17 extracts a signal for an effective symbol length from one OFDM symbol, and performs an FFT operation on the extracted signal. That is, the FFT operation circuit 17 removes a signal corresponding to the guard interval length from one OFDM symbol, and performs an FFT operation on the remaining signal.

  The signal modulated by each subcarrier extracted by the FFT operation circuit 17 is a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). The signal extracted by the FFT operation circuit 17 is supplied to the frame detection / transmission control information decoding circuit 18, the synchronization circuit 19, and the carrier demodulation circuit 20.

  The frame detection / transmission control information decoding circuit 18 extracts a TMCC signal from a predetermined subcarrier of the signal demodulated by the FFT operation circuit 17, detects a synchronization signal from the TMCC signal, detects an OFDM frame boundary, and detects A frame synchronization signal indicating the boundary position of the frame is supplied to the synchronization circuit 19 and the like. Further, the frame detection / transmission control information decoding circuit 18 performs error correction decoding on TMCC information (transmission control information) included in the TMCC signal after synchronization with a difference set cyclic code. The frame detection / transmission control information decoding circuit 18 supplies the decoded TMCC information to the carrier demodulation circuit 20, the time deinterleaving circuit 22, the demapping circuit 23, the bit deinterleaving circuit 24, and the transport stream generating circuit 29. Then, control such as demodulation and reproduction of each circuit is performed.

  The synchronization circuit 19 uses a baseband OFDM signal, a signal modulated on each subcarrier after being demodulated by the FFT operation circuit 17, an OFDM symbol boundary, a channel selection signal supplied from the channel selection circuit 31, and the like. Thus, various types of synchronization processing such as synchronization processing of the FFT calculation calculation range and its timing are performed on the FFT calculation circuit 17.

  The carrier demodulation circuit 20 is supplied with the demodulated signal from each subcarrier output from the FFT operation circuit 17 and performs carrier demodulation on the signal. Specifically, the carrier demodulation circuit 20 performs differential demodulation processing on the differential modulation signal (DQPSK) and equalization processing on the synchronous modulation signal (QPSK, 16QAM, 64QAM).

  The carrier demodulated signal is deinterleaved in the frequency direction by the frequency deinterleave circuit 21, subsequently deinterleaved in the time direction by the time deinterleave circuit 22, and then supplied to the demapping circuit 23. .

The demapping circuit 23 performs data reassignment processing (demapping processing) on the carrier demodulated signal (complex signal) to restore the transmission data sequence. For example, in the case of demodulating an OFDM signal conforming to the ISDB- _TSB standard, the demapping circuit 23 performs demapping processing corresponding to QPSK, 16QAM, or 64QAM.

  The transmission data sequence output from the demapping circuit 23 passes through the bit deinterleave circuit 24, the depuncture circuit 25, the Viterbi decoding circuit 26, the byte deinterleave circuit 27, and the spread signal removal circuit 28, thereby causing an error in the multilevel symbol. Deinterleaving processing corresponding to bit interleaving for distribution, depuncturing processing corresponding to puncturing processing for reducing transmission bits, Viterbi decoding processing for decoding convolutionally encoded bit strings, in byte units Energy despreading processing corresponding to deinterleaving processing and energy diffusion processing is performed and input to the transport stream generation circuit 29.

  The transport stream generation circuit 29 inserts data defined by each broadcasting system, such as a null packet, at a predetermined position in the stream. In addition, the transport stream generation circuit 29 performs so-called smoothing processing in which the bit interval of the intermittently supplied stream is smoothed to make a temporally continuous stream. The transmission data sequence subjected to the smoothing process is supplied to the RS decoding circuit 30.

  The RS decoding circuit 30 performs a Reed-Solomon decoding process on the input transmission data series and outputs it as a transport stream defined by MPEG-2 Systems.

  Next, the frame detection / transmission control information decoding circuit 18 will be further described.

  FIG. 2 is a block diagram of the frame detection / transmission control information decoding circuit 18.

  As shown in FIG. 2, the frame detection / transmission control information decoding circuit 18 includes a demodulator 40 to which a TMCC signal (I, Q signal) is supplied from the FFT arithmetic circuit 17, and a TMCC demodulated by the demodulator 40. The TMCC data holding unit 44 to which signals are supplied, the reference data holding unit 48 to which reference data is supplied from the external control unit 46, and the TMCC data demodulated by the demodulating unit 40 are directly and via the TMCC data holding unit 44. The TMCC signal demodulated by the supplied first frame synchronization control unit 50 and demodulating unit 40 is supplied via the TMCC data holding unit 44 and reference data from the external control unit 46 is supplied to the reference data holding unit. 48, the second frame synchronization control unit 60 supplied via the first frame, and the first frame. And a selector block 70 including a selector 71 for switching synchronization signals generated by the frame synchronization control unit 50 and the second frame synchronization control unit 60 and a selector 72 for selectively outputting transmission parameters.

  As shown in FIG. 3, the demodulator 40 includes a differential demodulator circuit 41 to which a TMCC signal (I, Q signal) is input from the FFT arithmetic circuit 17 and a bit determination circuit 42. The differential demodulation circuit 41 differentially demodulates the input TMCC signal to generate a complex signal (I, Q signal) at a signal point corresponding to the original information bit. The differentially demodulated signals (I and Q signals) are supplied to the bit determination circuit 42. The bit determination circuit 42 performs bit determination based on the differentially demodulated signals (I and Q signals). That is, it is determined whether the value modulated from the signal point on the IQ plane of the differentially demodulated signal is “0” or “1”, and one of the bit values is output. Accordingly, the bit determination circuit 42 outputs a TMCC signal that has been converted into a bit stream.

  The bit stream TMCC signal output from the bit determination circuit 42 of the demodulator 40 is directly supplied to the first frame synchronization control unit 50 and the first frame via the TMCC data holding unit 44. This is supplied to the synchronization control unit 50 and the second frame synchronization control unit 60.

  The first frame synchronization controller 50 establishes frame synchronization by detecting a synchronization word from TMCC data demodulated by the demodulator 40 from the received digital broadcast signal and TMCC data held in the TMCC data holding unit 44. For example, as shown in FIG. 4, a frame synchronization determination circuit 51 to which a bitstream TMCC signal output from the bit determination circuit 42 of the demodulator 40 is directly input, and this frame synchronization determination The bit stream TMCC signal output from the synchronous position storage unit 52 and the comparison circuit 53 to which the determination output of the circuit 51 is supplied, and the bit determination circuit 42 of the demodulation unit 40 is supplied via the TMCC data holding unit 44. Mismatch signal determination unit 54, error correction circuit 55, comparison circuit 53, mismatch signal determination The output of 54 and error correction circuit 55 is composed of a synchronous control circuit 56 is supplied.

  In the first frame synchronization control unit 50, the frame synchronization determination circuit 51 detects the synchronization word included in the bit stream TMCC signal and detects the synchronization position of the OFDM frame. Specifically, the frame synchronization determination circuit 51 first performs a correlation operation between the bit stream TMCC signal and the synchronization word (W0, W1). That is, the correlation value between the synchronization word (W0, W1) and the 16-bit width data string at each position in the bitstream is sequentially calculated. This correlation value is the highest value when the synchronization word (W0, W1) matches the bit string. Next, the frame synchronization determination circuit 51 detects a synchronization position representing the timing at which the calculated correlation value is maximized. The detected synchronization position is supplied to the synchronization position storage unit 52, the comparison circuit 53, and the TMCC data holding unit 44.

  The synchronization position storage unit 52 stores and holds the synchronization position detected by the frame synchronization determination circuit 51. When the synchronization position of the next OFDM frame is supplied from the frame synchronization determination circuit 51, the synchronization position storage unit 52 supplies the held synchronization position to the TMCC data holding unit 44.

  The comparison circuit 53 compares the synchronization position of a certain OFDM frame supplied from the frame synchronization determination circuit 51 with the synchronization position of the previous OFDM frame supplied from the synchronization position storage unit 52, and whether or not the synchronization positions match. To detect. Based on the detection result, the comparison circuit 53 outputs to the synchronization control circuit 56 a synchronization determination signal indicating “OK” if the synchronization positions match, and “NG” if they do not match.

  Here, the TMCC data holding unit 44 functions as means for holding TMCC data obtained by demodulating the DBCCK-modulated TMCC carrier by the demodulating unit 40, and is configured by, for example, a shift register. The shift register that constitutes the TMCC data holding unit 44 has, for example, a shift register length of 220 bits and a second frame synchronization in order to secure an amount of information necessary for causing the first frame synchronization control unit 50 to function. The amount of information used to realize the function of the control unit 60 is 203 bits (one frame).

  The demodulating unit 40 inputs TMCC data output in symbol units to a TMCC data holding unit 44 configured as a shift register in a bit serial manner. TMCC data held in each register is extracted and input to the correlation calculation unit 61. The input data only needs to be necessary for correlation (203 bits in the implementation), but all the data held in the shift register is handed over in the implementation, and the correlation calculation unit 61 selects the necessary data.

  The TMCC data holding unit 44 can also be configured using a RAM instead of a shift register.

  The TMCC data holding unit 44 delays the TMCC signal (bit stream) by the time required for the detection of the synchronization position in the frame synchronization determination circuit 51, and the synchronization is obtained by the synchronization position supplied from the frame synchronization determination circuit 51. The TMCC signal is supplied to the mismatch signal determination unit 54 and the error correction circuit 55.

  The mismatch signal determination unit 54 determines whether or not the bit stream TMCC signal cannot occur in the system. Based on the determination result, the mismatch signal determination unit 54 outputs to the synchronization control circuit 56 a mismatch determination signal indicating “NG” if the signal is not possible in the system, and “OK” otherwise. To do. For example, when the TMCC signal is all 0, since there is a high possibility of signal disconnection or the like, the mismatch signal determination unit 54 outputs a mismatch determination signal indicating “NG” to the synchronization control circuit 56.

  The error correction circuit 55 performs error correction decoding on the TMCC information included in the bit streamed TMCC signal using a differential cyclic code, and outputs the decoded TMCC information to the carrier demodulation circuit 20 or the like. Further, the error correction circuit 55 outputs an error correction success / failure signal indicating success / failure of the error correction to the synchronization control circuit 56. The error correction success / failure signal indicates “OK” if the error correction is successful, and “NG” if the error correction fails.

  The synchronization control circuit 56 controls the output of the frame synchronization signal and the output of synchronization establishment information based on the synchronization determination signal, the mismatch determination signal, and the error correction success / failure signal. The frame synchronization signal is a flag that periodically generates the boundary position of the OFDM frame such that it becomes “H” (high) at the timing of the start position of the OFDM frame and “L” (low) at other timings. . The synchronization control circuit 56 generates a first flag when a certain trigger is given (the flag is set to “H” (high)), and thereafter generates a flag periodically by counting, for example, an operation clock. Then, a frame synchronization signal is generated. The synchronization establishment information is information for notifying an external circuit whether or not the frame synchronization signal is synchronized with the received signal, that is, information indicating whether or not frame synchronization is established. The synchronization establishment information indicates “OK” if frame synchronization is established, and “NG” if it is not established.

  The synchronization control circuit 56 controls the output of the frame synchronization signal and the synchronization establishment information by the state machine 80 having the state transition diagram as shown in FIG. Hereinafter, the state machine 80 will be described.

  States 0 to 2 are backward protection states in which the synchronization of the OFDM frame is not established. In the state 0 to the state 2, the synchronization control circuit 56 does not output the frame synchronization signal, and further notifies the outside that the frame synchronization is not established by setting the synchronization establishment signal to “NG”.

  State 3 is a state 3 (0, 0) that is a complete synchronization state in which synchronization is established, a state 3 (0, 1) that is a forward protection state in which synchronization is established, and a state 3 (0, 2). , State 3 (1, 0), state 3 (2, 0), and state 3 (1, 1). In this state 3, as shown in FIG. 5, the state transitions according to a substantially triangular state transition diagram having two synchronization protection stages and two error protection stages. In the state 3, the synchronization control circuit 56 outputs a frame synchronization signal, and further notifies the outside that the frame synchronization is established by setting the synchronization establishment signal to “OK”.

  In the state machine 80, transition between states 0 to 3 is performed under the conditions as shown in the flowchart of FIG.

  First, when the synchronization control circuit 56 is reset, the state machine 80 transitions to the initial state 0 (step S1). When bits for one ODFM frame are accumulated in the frame synchronization determination circuit 43 (step S2), the state transitions to the state 1 that is the correlation value calculation state (step S3).

  Next, when the frame synchronization determination circuit 51 calculates the correlation value and detects the maximum value of the correlation value (step S4), the state machine 80 transitions to state 2 which is the synchronization pull-in state (step S5). At this time, the TMCC data holding unit 44 synchronizes the ODFM frame by shifting the head position of the ODFM frame to a position where the correlation value is maximized (step S6).

  In state 2, the state machine 80 determines a mismatch determination signal and an error correction success / failure signal (steps S7 and S8). If the error correction success / failure signal indicates “NG” or the error correction success / failure signal indicates “OK”, the state machine 80 returns to the state 1 again when the inconsistency determination signal indicates “NG”. Transition to. On the other hand, when both the error correction success / failure signal and the mismatch determination signal indicate “OK”, the state transits to the state 3 (0, 0), which is a complete synchronization state, and TMCC information is output (step S9). .

  Subsequently, when the frame synchronization determination circuit 51 calculates the correlation value and detects the maximum value of the correlation value (step S10), the state machine 80 determines the synchronization determination signal and the error correction success / failure signal (steps S11 and S13). . When the synchronization determination signal indicates “NG”, the state machine 80 adds 1 to the number of synchronization protection stages as the first count value, and when the error correction success / failure signal indicates “NG”. Adds 1 to the number of error protection stages as the second count value (steps S12 and S14).

  Thereafter, the state machine 80 calculates the number of forward protection steps, which is a weighted sum of the number of synchronization protection steps and the number of error protection steps (step S15), and compares the number of forward protection steps with a threshold value to determine whether or not it is within the protection range. Is determined (step S16). This threshold is such that if the weighted sum is less than or equal to the threshold, the corresponding state is present in state 3, and if the weighted sum is greater than the threshold, the corresponding state is not present in state 3. Set to the correct value. When the state machine 80 is in the state 2 as a result of the determination, the state machine 80 determines the mismatch determination signal and the error correction success / failure signal (steps S6 and S7). If the error correction success / failure signal indicates “NG” or the error correction success / failure signal indicates “OK”, the state machine 80 returns to the state 1 again when the inconsistency determination signal indicates “NG”. Transition to. On the other hand, when both the error correction success / failure signal and the mismatch determination signal indicate “OK”, the state transitions to state 3 (0, 0), which is a complete synchronization state (step S9).

  Subsequently, when the frame synchronization determination circuit 51 calculates the correlation value and detects the maximum value of the correlation value (step S10), the state machine 50 determines the synchronization determination signal and the error correction success / failure signal (steps S11 and S13). . When the synchronization determination signal indicates “NG”, the state machine 80 adds 1 to the number of synchronization protection stages as the first count value, and when the error correction success / failure signal indicates “NG”. Adds 1 to the number of error protection stages as the second count value (steps S12 and S14).

  Thereafter, the state machine 80 calculates the number of forward protection steps, which is a weighted sum of the number of synchronization protection steps and the number of error protection steps (step S15), and compares the number of forward protection steps with a threshold value to determine whether or not it is within the protection range. Is determined (step S16). This threshold is such that if the weighted sum is less than or equal to the threshold, the corresponding state is present in state 3, and if the weighted sum is greater than the threshold, the corresponding state is not present in state 3. Set to the correct value. If the state machine 80 is within the protection range as a result of the determination, the state machine 80 transitions to a state corresponding to the current number of synchronization protection stages and error protection stages. That is, when the current number of synchronization protection stages is i and the number of error protection stages is j, the state transitions to state 3 (i, j). On the other hand, if it is not within the protection range, that is, if there is no state 3 (i, j) corresponding to the current synchronization protection stage number i and error protection stage number j, the synchronization is removed and the state transitions to state 1.

  In each state of state 3, when both the synchronization determination signal and the error correction success / failure signal indicate “OK”, the number of synchronization protection stages and the number of error protection stages are initialized to 0, and the state is in a completely synchronized state Transition to 3 (0, 0).

  If it is within the protection range, a transition is made to a state corresponding to the current number of synchronization protection stages and error protection stages. That is, when the current number of synchronization protection stages is i and the number of error protection stages is j, the state transitions to state 3 (i, j). On the other hand, if it is not within the protection range, that is, if there is no state 3 (i, j) corresponding to the current synchronization protection stage number i and error protection stage number j, the synchronization is removed and the state transitions to state 1.

  In each state of state 3, when both the synchronization determination signal and the error correction success / failure signal indicate “OK”, the number of synchronization protection stages and the number of error protection stages are initialized to 0, and the state is in a completely synchronized state Transition to 3 (0, 0). Furthermore, since the error correction correct / incorrect signal indicates “OK”, the TMCC information is updated.

  As described above, in the state machine 80 in the synchronization control circuit 56, the number of synchronization protection stages and the number of error protection stages are set independently to perform forward synchronization protection control.

  Here, in the state machine 80 described above, the number of synchronization protection stages and the number of error protection stages are set to two, but each is set to an arbitrary number of stages according to the strength of the frame structure of the OFDM frame and the error correction capability. be able to. As a result, the synchronization control circuit 56 can realize more stable frame synchronization protection. Further, more stable frame synchronization protection can be realized by changing the number of synchronization protection stages and the number of error protection stages depending on the reception state of the OFDM receiver 10, bit error rate, or fixed reception / mobile reception. .

  In the above description, in the control between the states of state 3, when only one of the synchronization determination signal and the error correction success / failure signal indicates “OK”, the state is not changed. Of the synchronization determination signal and the error correction success / failure signal, 1 may be subtracted from the number of protection stages indicating “OK”, and the corresponding state may be changed.

  Here, in frame synchronization control, every symbol TMCC data is input, but it is determined which symbol is the head of the frame (symbol number = 0), and what TMCC information is received. To do. When both of these are established, it is referred to as “establishing frame synchronization”.

  The first frame synchronization control unit 50 can perform highly reliable frame synchronization, but it takes time until the frame synchronization is established. Number of symbols required until frame synchronization is established (a flag indicating that some frame synchronization has been established at the timing of receiving the beginning of the frame (symbol number 0) (hereinafter referred to as a frame synchronization flag or simply called a synchronization flag) is output) The number of frames is 407 symbols (about 2 frames, 1 frame is 204 symbols) at the shortest, 610 symbols (about 3 frames) at the longest, and 508.5 symbols (about 2.5 frames) on the average. Since post-processing cannot be performed unless frame synchronization is established, the frame synchronization time greatly affects the time from the start of operation of the digital broadcast receiving apparatus until the final data is normally output.

  Therefore, in the frame detection / transmission control information decoding circuit 18, the second frame synchronization control unit 60 performs frame synchronization at high speed using the correlation.

  That is, if one or more reference data of at least a part of the expected TMCC information is held, it is held in the reference data holding unit 48, and the TMCC data held in the TMCC data holding unit 44 and the reference data holding unit 48, the second frame synchronization control unit 60 obtains a correlation with the reference data held in the frame 48, performs frame synchronization at high speed, and the frame synchronization is established by the second frame synchronization control unit 60. The selector 71 of the block 70 switches from the synchronization control by the first frame synchronization control unit 40 to the synchronization control by the second frame synchronization control unit 60.

  As shown in FIG. 7, the second frame synchronization control unit 60 is supplied with the TMCC signal demodulated by the demodulation unit 40 via the TMCC data holding unit 44 and also from the external control unit 46 with reference data. From the correlation calculation unit 61 supplied via the reference data holding unit 48, the frame synchronization determination unit 62 supplied with the output of the correlation calculation unit 61, the output of the frame synchronization determination unit 62, and the external control unit 46 The reference parameter data includes a transmission parameter selection unit 63 supplied via the reference data holding unit 48.

  Here, the TMCC data holding unit 44 shifts the data every time one symbol of TMCC data demodulated by the demodulating unit 40 is input, and holds TMCC data for each symbol.

  The reference data holding unit 48 holds one or more reference data of at least a part of the expected TMCC information. For example, three references (host_tmcc_bitseq, cand1_tmcc_bitseq, cand2_tmcc_bitseq, both are 187 bits) Holding. It is assumed that host_tmcc_bitseq is set by the host (external control unit 46) every time the receiving apparatus is activated. cand1_tmcc_bitseq and cand2_tmcc_bitseq hold, by default, TMCC information that is normally used (and is expected to be used) in case host_tmcc_bitseq does not match the received TMCC data, that is, when the correlation value is low ( The data can be reconfigured on the host. The specific contents of the individual reference data are all TMCC information frames except the differential reference 1 bit and the synchronization word 16 bits arranged at the head of the frame. Since the sync word is known information, it is not necessary to include it in the reference. The correlation calculation unit 61 can be set so as to select which part of the data is to be correlated, but depending on this setting, it is not always necessary to set all 187 bits. For example, the setting of only the current information that is normally expected can provide a sufficient effect. However, by setting the portion corresponding to the parity at the end of the TMCC information frame, the input of TMCC data is started from any position in the frame. However, frame synchronization can be established until approximately one frame is received. To be exact, it depends on the amount of information used for correlation at the end of the frame. In the implementation, the information amount is set to be regarded as synchronized when the default is 16 bits and the allowable error is 0, that is, all 16 bits match. When the host inputs a value from a register module that can set a value to the correlation calculation unit 61, the correlation calculation unit 61 appropriately selects information necessary for the calculation.

  The first frame synchronization control unit 40 has a function for acquiring data to be given to the reference data holding unit 48, and the data obtained by this function can be used as the next reference data. . In the first frame synchronization control unit 40, in a stable frame synchronization state, a trigger is activated at a desired timing (fsync_word_cap_en), and the received TMCC data (rcvd_tmcc_bitseq) by the number of valid bits as reference data therefrom. Is output. The main condition for triggering at this time is that error correction was not performed by a DSCC (Differential Set Cyclic Code) decoder in a stable synchronization state.

  Then, in the second frame synchronization control unit 60, as shown in FIG. 8, every time one symbol of the TMCC data is input to the TMCC data holding unit 44, the correlation calculation unit 61 uses the reference data holding unit 48. Correlation is calculated for the number of reference data held in the frame, and a frame synchronization signal is output from the frame synchronization determination unit 62 when it is determined that the correlation value calculated by the correlation calculation unit 61 exceeds the threshold. Further, the transmission parameter selection unit 63 extracts and outputs the transmission parameter from the reference data used when the frame synchronization is established.

  In the second frame synchronization control unit 60, each time one symbol of the TMCC data is input to the TMCC data holding unit 44, the correlation calculation unit 61 holds the reference data holding unit 48, as shown in FIG. Correlation is calculated as many times as the number of reference data, and the frame synchronization determination unit 62 performs frame control according to the correlation value. In addition, you may take correlation with all the reference data. Alternatively, correlation may be calculated in the descending order of priority, and the frame calculation may be established when the high correlation is detected, and the correlation calculation may be terminated.

  Here, the second frame synchronization control unit 60 determines frame synchronization from the correlation calculation between the reference data held in the reference data holding unit 48 and the input TMCC data, but sets the frame synchronization flag at the correct timing. Even if the transmission can be performed, if the transmission parameter is wrong, the subsequent process cannot be performed correctly. Therefore, the transmission parameter selection unit 63 selects information necessary for the subsequent process from the reference data obtained when the correlation is obtained (usually, Extracts current information) and sends it to the subsequent stage.

  That is, in this OFDM receiver 10, TMCC data is input from the symbol demodulation unit 40 to the first frame synchronization control unit 50 and the second frame synchronization control unit 60, and in the second frame synchronization control unit 60, As shown in FIG. 10, every time symbol TMCC data is input, pattern matching with the reference data holding unit 48 is performed in the correlation calculation unit 61. If the correlation value is equal to or greater than a threshold value, the symbol number (= 0) ) Is confirmed, and the received TMCC information is confirmed, and frame synchronization is confirmed.

  Here, in the synchronous control using the correlation, for example, as shown in FIG. 10, even if there is a symbol (a bit subjected to a shading process) that has caused an error due to noise, that is, even if there is some noise. If the number of bits to be correlated is sufficiently large, highly reliable synchronization can be established even if the threshold value is lowered.

  On the other hand, the first frame synchronization control unit 50 detects a synchronization word for TMCC data input every symbol, and corrects an error at an information position where error protection is applied, which is expected from the detected synchronization word position. If successful, frame synchronization is established.

  Normally, the two frame synchronization control units 50 and 60 are characterized by the algorithm characteristics, and as shown in FIG. 11, the second frame synchronization control unit 60 using the correlation establishes the frame synchronization quickly, The frame synchronization signal generated by the second frame synchronization control unit 60 and the TMCC information are output. Thereafter, frame synchronization is established by the first frame synchronization control unit 50, and an operation of switching to the output of the first frame synchronization control unit 50 with high reliability is performed.

  The reference data holding unit 48 generates a 1-bit differential modulation reference signal (B0) and a 16-bit synchronization signal (B1 to B16) from a TMCC signal (B0 to B203), which is a unit of 204-bit information. Excluding the 3-bit segment format identification (B17-B19), the 102-bit TMCC information (B20-B121), and the 187-bit (B17-B203) reference data consisting of the 82-bit parity bits (B122-B203) Is supplied from the external control unit 46, the reference data is held as it is. However, by mounting an encoder function in the reference data holding unit 48, for example, reference data of 187 bits (B17 to B203) is stored. Of these, 82 parity bits (B122 to B2 3) except for the current information (B27 to B66) of the TMCC information (B20 to B121) as fixed information, and only the 40-bit current information (B27 to B66) is sent from the external control unit 64 to the reference data holding unit. 48, storing 187-bit reference data encoded from the 40-bit current information (B27 to B66), or other than the current information (B27 to B66) and next information (B67 to B106) of the TMCC information As a fixed information, a copy of the current information or a fixed value (for example, all 1) is selectively given as the 40-bit next information (B67 to B106) together with the 40-bit current information (B27 to B66). Encode from current information and next information 187-bit reference data may be stored to.

  That is, in operation, the 3-bit segment format identification information (B17 to B19) is a fixed value [000] for both television broadcasting and radio broadcasting, and the system identification information of the 102-bit TMCC information (B20 to B121). (B20 to B21) is a fixed value [00] in the television broadcast, and a fixed value [10] in the radio broadcast, and the transmission parameter switching index (B22 to B25) is the fixed value [1111]. The broadcast start flag (B26) is normally a fixed value [0] for both television broadcasting and radio broadcasting, and the linked transmission phase correction amount information (B107 to B109) is a fixed value [111 for both television broadcasting and radio broadcasting. The reserve information (B110 to B121) is a fixed value [11 for both television broadcasting and radio broadcasting. The parity bits (B122 to B203) of the 187 bits (B17 to B203) of the reference data are error correction codes for the 102 bits of TMCC information (B20 to B121), and the TMCC information ( B20 to B121), the reference data holding unit 48 equipped with the encoder function excludes the 82-bit parity bits (B122 to B203) of the 187-bit (B17 to B203) reference data. The information (B20 to B26, B27 to B121) other than the current information (B27 to B66) of the TMCC information (B20 to B121) is fixed information, and only 40-bit current information (B27 to B66) is received from the external control unit 64. If given, given Based on the obtained 40-bit current information (B27 to B66) and fixed information (B20 to B26, B27 to B121), 82-bit parity bits (B122 to B203) can be generated. Bit current information (B27 to B66) can be encoded and stored in 187-bit (B17 to B203) reference data.

  Similarly, in the reference data holding unit 48 equipped with the encoder function, except for the 82-bit parity bits (B122 to B203) of the 187-bit (B17 to B203) reference data, the current information (B27 to B66) and information other than the next information (B67 to B106) as fixed information, the external control unit 64 sends the current information as 40-bit next information (B67 to B106) together with the 40-bit current information (B27 to B66). Or a fixed value (for example, all 1) is selectively given, the given 40-bit current information (B27 to B66), current information (B27 to B66), and fixed information (B20 to B26, B67 to B121) based on 82 parity bits (B1 2 to B203) can be generated, and the given 40-bit current information (B27 to B66) and current information (B27 to B66) are encoded and stored as 187-bit (B17 to B203) reference data. be able to.

  When the external control unit 64 selectively gives a copy of the current information or a fixed value (for example, all 1) as the 40-bit next information (B67 to B106), the external control unit 64 sets the copy of the current information or the fixed value (for example, all 1). Which one is used as the next information (B67 to B106), it is determined whether a good reception state such as synchronization can be obtained, and a copy or a fixed value (for example, all 1) of the current information that obtains a good reception state. Is selected and supplied as the next information (B67 to B106) to the reference data holding unit 48 equipped with the encoder function.

  Since the external control unit 46 is assumed to input only a part of data (for example, only current information) without inputting all data to the reference, in such a case, the correlation is performed only with the current information. By taking the above, frame synchronization control using correlation becomes effective. Further, by performing correlation calculation of lower-order bits (16 bits in this embodiment) of the frame, frame synchronization can be established when TMCC data of 16 symbols (= 16 bits) at the shortest is input from the start of operation.

  Here, the correlation calculation unit 61 employs pattern matching as a correlation value calculation method. The correlation calculation unit 61 includes a first correlation calculation unit implemented for frame synchronization speed-up, a TMCC information part other than the first correlation calculation unit, and a second correlation calculation unit of received data. Yes. Note that the reason why the correlation calculation unit 61 is divided into two is a mounting reason and can be constituted by one correlation calculation unit.

  The first correlation calculation unit calculates the correlation (pattern match) between the parity corresponding to the end of the TMCC information frame and the received data. As a result, as shown in FIG. 10, even if the reception is started from the end of the frame, synchronization can be established immediately if the correlation value output by the calculation unit is sufficiently reliable. On the other hand, when this calculation unit is not provided, when input is started from the end of the frame, synchronization cannot be performed in the frame, and synchronization is established in the subsequent frames.

  The second correlation calculation unit is roughly divided into a correlation calculation unit with a synchronization word and other correlation calculation units. This is because the correlation calculation is separated from information that is the same bit every frame other than the synchronization word for the standard reason that the bit of each frame synchronization word is inverted. The correlation value with the synchronization word is cor_oneside2_sel, and the correlation result with other than the synchronization word is tmcc_cor_add8. The total correlation result obtained by combining the two results is total_corr_value.

  In this correlation calculation unit 61, each time TMCC data is input every symbol in the second correlation calculation unit, data extracted from the TMCC data holding unit 44 (tmcc_csr [219: 17]) and the reference data holding unit 48 Is correlated with one tmccparams among the one or more reference data held in (1). tmccparams changes to reference data host_tmcc_bitseq, cand1_tmcc_bitseq, and cand2_tmcc_bitseq by timing control, and performs correlation calculation each time. Further, even with reference data having the same content, the correlation calculation is performed a plurality of times in accordance with the data area for which the correlation calculation is performed. There are 6 patterns of data areas, and bitmask_tmccparams is used to specify an information area to be subjected to correlation calculation, and unnecessary information is masked. After all, every time one symbol is input, one correlator performs (18 reference data (3) × correlation target area pattern (6)) = 18 correlations to share resources.

  It is possible to configure the same number of correlators according to the type of correlation calculation. In this case, although the amount of configuration increases, it is not necessary to consider timing control, and is an effective means when the supplied clock is slow. In addition, the correlation calculation is performed a plurality of times for one reference data in accordance with the correlation target data, but it is also possible to weight the correlation values of each information instead of simply performing pattern matching. . That is, a higher correlation value is given to more important information and highly reliable information areas. For example, when the external control unit 46 knows that only the current information is given as reference data, the correlation calculation of the part corresponding to the current information is more reliable by giving a larger correlation value than the other data. It is possible to perform a certain frame synchronization. For the correlation evaluation, a method using the sum of absolute values and the sum of squares can be considered in addition to the EXOR used in this embodiment and the above-mentioned weighted sum.

  The frame synchronization determination unit 62 has two functions. One is a function of performing frame synchronization determination in the previous stage by evaluating the correlation value output by the correlation calculation unit 61. The other is a function for establishing the final frame synchronization in the subsequent stage in consideration of the frame synchronization determination result in the previous stage and the information on the regularity of the frame, that is, the head of the frame comes every 204 symbols. It is. As a method of determining the frame synchronization in the previous stage, a method is implemented in which if the correlation value output from the correlation calculation unit 61 is equal to or greater than a threshold, it is regarded as a TMCC information frame break and frame synchronization is established. Although the determination unit is divided into two, it can be combined into one.

  In the previous frame synchronization determination unit, the correlation value total_corr_value and the threshold current_thrsh1 output from the correlation calculation unit 61 are input to the frame synchronization determination unit. In the previous frame synchronization determination unit, if total_corr_value is equal to or greater than current_thrsh1, it is determined that the frame is separated, frame synchronization is established, and the corr_ok flag is set. The corr_ok flag is a flag indicating a frame delimiter, and a frameend flag (≈frame head position detection flag) is set through the timing control unit.

  Further, the frame synchronization determination unit at the later stage evaluates the frameend flag obtained in the previous stage process across frames. Here, 204 symbols are counted from the timing when the last frameend is input, and if no frameend is input after 204 symbols, a synchronization flag is automatically generated. By doing this, in a noisy environment, etc., the frameend flag can be generated in the previous frame, but in the current frame, there is too much noise and the frameend flag is not generated. By complementing, the subsequent timing process can be maintained.

  The operation of the frame synchronization determination unit 62 is shown in the timing chart of FIG.

Here, as shown in FIG. 13, the preceding frame synchronization determination unit performs a plurality of correlation calculations each time one symbol is input, as shown in FIG. Therefore, total_corr_value becomes different data depending on each correlation calculation result. Accordingly, the correlation value current_thrsh1 must be set to a desired threshold value corresponding to the correlation calculation, which is synchronized with the timing control unit so that the two values correspond to each other. The order of correlation calculation is
187 bit correlation with host_tmcc_bitseq ⇒
187bit correlation with cand1_tmcc_bitseq ⇒
187 bit correlation with cand2_tmcc_bitseq ⇒
104bit correlation with host_tmcc_bitseq ⇒
104bit correlation with cand1_tmcc_bitseq ⇒
...
16bit correlation with cand1_tmcc_bitseq ⇒
16bit correlation with cand2_tmcc_bitseq
A total of 18 calculations are performed according to the priority order. In addition, the calculation result exceeding the threshold at the beginning is used in the subsequent frame synchronization determination unit, and even if the correlation value exceeds the threshold in the later correlation calculation, it is ignored.

  Further, as shown in FIG. 14 for TMCC information to be subjected to pattern matching at each level, the number of bits for correlation calculation in each reference is 187 bits, 104 bits, 104 bits, 64 bits, 24 bits, 16 bits, from level 6 to level 1. There are six levels (the higher the level, the higher the reliability), and each level can be set from the outside (ctl_fend_det_min_level, ctl_fend_det_max_level). Based on this set value, the timing control unit masks unnecessary previous processing results. In the subsequent frame synchronization determination unit, when frameend is input from the frame synchronization determination unit in the previous stage processing, the 204 symbol counter starts counting up at the same time as the synchronization flag (acc_frameend) is transmitted. When the count value becomes 204-> 0, if no frameend is input, a synchronization flag is generated by automatic completion. If frameend is input with a value other than 0, the counter is reset at the same time as sending the synchronization flag, and the count-up starts from 0.

  In the preceding process, it is conceivable to store a correlation result between 204 symbols, and use the symbol timing at which the correlation result is maximum as the head position of the frame. In addition, when the correlation value exceeds a threshold value in a certain frame, a method of validating only the level higher than the level when the correlation is obtained is effective for the correlation calculation with the subsequent frames.

  Here, in the second frame synchronization control unit 60, the number of symbols (the number of frames) necessary to establish the frame synchronization is the shortest number of correlation target symbols at the end of the frame and the longest (1 frame + the end of the frame). The number of correlation target symbols-1) and the average ((1 frame + number of correlation target symbols at the end of 2 frames-1) / 2). In the implementation example, the number of correlation target symbols at the end of the frame is 16, and in this case, the number of symbols (number of frames) required to establish frame synchronization is 16 symbols at the shortest, 219 symbols at the longest, and 117. This is 5 symbols (approximately 0.6 frames), and frame synchronization can be established approximately 1.9 frames faster than the conventional method. Further, by increasing the number of symbols to be correlated, it becomes possible to further increase the reliability of frame synchronization, and it is possible to stably establish frame synchronization even when the noise level is high. In addition, by predicting TMCC information to be received in advance and preparing one or more reference data, it is possible to flexibly cope with changes in TMCC information on the transmission side. Normally, the received TMCC information differs depending on the selected channel, but by outputting the received TMCC information as it is to the external control unit, the external control unit references this TMCC information at the next channel selection. Can be entered as data. At this time, if there is an error in the portion of the received TMCC information that is error-protected by differential-set cyclic coding, the TMCC information that is not appropriate is output as reference data at the next channel selection. It is desirable to output TMCC information only when a flag indicating that error correction has not been performed at the time of decoding is established for the TMCC information.

  Further, in the frame synchronization method using the correlation between the received TMCC information and the reference data, it is expected that the correlation value becomes lower with respect to the received TMCC information having an error, and the received TMCC information is the reference data. If it does not match, it is difficult or impossible to establish frame synchronization. Therefore, as in the first frame synchronization control unit 50, the synchronization word is detected, the differential cyclic decoding is successfully performed, etc. It is desirable to use it together with a method that establishes more reliable frame synchronization as a condition. In this way, at the start of operation, frame synchronization is established immediately using a frame synchronization method using the correlation between the received TMCC information and reference data, and the first frame synchronization control unit 50 establishes frame synchronization. Then, by switching to the first frame synchronization control unit 50, high-speed and highly reliable frame synchronization can be performed.

  Here, in the embodiment described above, as shown in FIG. 7, the correlation calculation unit 61 performs timing control with one correlator and performs a plurality of correlation calculations each time one symbol data is input. What is being performed (time division processing) is not necessarily time division processing. For example, as shown in FIG. 15, it may be possible to prepare a plurality of correlators 61a, 61b,. In the case of time-sharing processing as in the present embodiment, when the correlation with the reference data with high priority is obtained, the frame synchronization is established regardless of the correlation value with the reference data with low priority. However, in the method using a plurality of correlators 61a, 61b,... 61n shown in FIG. 15, the first priority method cannot be taken, and the frame synchronization determination according to the reliability is performed. There is a need to do.

  Further, as in the frame detection / transmission control information decoding circuit 18 shown in FIG. 2, one or more reference data of at least a part of the expected TMCC information is held in the reference data holding unit 48, and the received digital The synchronization control by the first frame synchronization control unit 50 that detects the synchronization word from the TMCC data demodulated from the broadcast signal and establishes the frame synchronization, the TMCC data demodulated from the received digital broadcast signal, and the expected TMCC information Synchronization is performed by the second frame synchronization control unit 60 that establishes frame synchronization by obtaining a correlation with at least a part of one or more reference data, and frame synchronization is established by the first frame synchronization control unit 50 At this point, the first block synchronization controller 60 sends the first frame by the selector block 70. In the above-described OFDM receiving apparatus 10, for example, the transmission parameter of each layer is given as 40-bit current information from the external control unit 46 to the reference data holding unit 48 in order to switch to the synchronization control by the frame synchronization control unit 50. The data is held in the reference data holding unit 48 as data, and the transmission parameters generated by the first frame synchronization control unit 50 and the second frame synchronization control unit 60 are selectively output as shown in FIG. A selector 73 controlled by the second frame synchronization control unit 60 is provided at the output stage of the selector 72, and the transmission parameter output from the selector 72 and the reference data output from the reference data holding unit 48 are It is switched by the selector 73 and the second Until the frame synchronization by the frame synchronization control unit 60, may be applied to the subsequent stage as an interim transmission parameter reference data outputted from the reference data holding unit 48.

It is a block diagram which shows the structure of the OFDM receiver to which this invention is applied. It is a block diagram which shows the structure of the frame detection / transmission control information decoding circuit in the said OFDM receiver. It is a block diagram which shows the structure of the demodulation part in the said frame detection / transmission control information decoding circuit. It is a block diagram which shows the structure of the 1st frame synchronization control part in the said demodulation part. It is a figure which shows an example of the state machine of the synchronous control circuit in the said frame detection / transmission control information decoding circuit. It is a flowchart explaining the state transition in the said state machine. It is a block diagram which shows the structure of the 2nd frame synchronization control part in the said demodulation part. It is a figure which shows typically the operation | movement of the synchronous control using the frame correlation in the said 2nd frame synchronous control part. It is a figure which shows typically the operation | movement of the synchronous control using the said frame correlation. It is a figure which shows typically the influence of the noise in the synchronous control using the said frame correlation. It is a figure which shows typically the speed of establishment of the frame synchronization by the 1st and 2nd frame synchronization control part in the said demodulation part. 6 is a timing chart showing an operation of the second frame synchronization determination unit. It is a timing chart which shows the process in 1 symbol by the frame synchronization determination part of the previous step in the said 2nd frame synchronization determination part. It is a figure which shows typically the TMCC information used as the object of the pattern matching of each level in the said frame synchronization determination part of the said previous step. It is a block diagram which shows the other structural example of the frame detection / transmission control information decoding circuit in the said OFDM receiver. FIG. 10 is a block diagram showing still another configuration example of the frame detection / transmission control information decoding circuit in the OFDM receiver.

Explanation of symbols

  10 OFDM receiver, 11 antenna, 12 tuner, 12a multiplier, 12b local oscillator, 13 band pass filter (BPF), 14 A / D conversion circuit, 15 DC cancellation circuit, 16 digital quadrature demodulation circuit, 17 FFT operation circuit, 18 frame detection / transmission control information decoding circuit, 19 synchronization circuit, 20 carrier demodulation circuit, 21 frequency deinterleaving circuit, 22 time deinterleaving circuit, 23 demapping circuit, 24 bit deinterleaving circuit, 25 depuncturing circuit, 26 Viterbi decoding circuit , 27 byte deinterleave circuit, 28 spread signal removal circuit, 29 transport stream generation circuit, 30 RS decoding circuit, 31 channel selection circuit, 40 demodulator, 41 differential demodulation circuit, 42 bit decision circuit, 44 TMCC data Data holding unit, 46 external control unit, 48 reference data holding unit, 50 first frame synchronization control unit, 51 frame synchronization determination circuit, 52 synchronization position storage unit, 53 comparison circuit, 54 mismatch signal determination unit, 55 error correction Circuit, 56 synchronization control circuit, 60 second frame synchronization control unit, 61 correlation calculation unit, 61a, 61b... 61n correlator, 62 frame synchronization determination unit, 63 transmission parameter selection unit, 71 selector, 72 selector, 73 Selector, 70 selector block, 80 state machine

Claims (15)

TMCC data holding means for holding Transmission Multiplexing Configuration Control (TMCC) data demodulated from the received digital broadcast signal;
First frame synchronization control means for detecting a synchronization word from TMCC data demodulated from the received digital broadcast signal and TMCC data held in the TMCC data holding means to establish frame synchronization;
Holding one or more reference data of at least a part of the expected TMCC information, and a reference data holding means;
Second frame synchronization control means for establishing a frame synchronization by obtaining a correlation between the TMCC data held in the TMCC data holding means and the reference data held in the reference data holding means;
Synchronization control switching means for switching from the synchronization control by the second frame synchronization control means to the first frame synchronization control means when the frame synchronization by the first frame synchronization control means is established. And a frame synchronization control apparatus. The second frame synchronization control means includes:
Correlation calculating means for calculating a correlation value between the TMCC data held in the TMCC data holding means and the reference data held in the reference data holding means;
The frame synchronization control device according to claim 1, further comprising: a frame synchronization determination unit that determines frame synchronization using the correlation value calculated by the correlation calculation unit.   3. The frame synchronization according to claim 2, wherein the second frame synchronization control means further comprises transmission parameter extraction means for selecting and outputting a transmission parameter from the reference data used when frame synchronization is established. Control device.   The second frame synchronization control means extracts TMCC data when it can be decoded without performing error correction, and uses this as reference data to be correlated with frame synchronization at the next channel selection. Item 3. The frame synchronization control device according to Item 2.   3. The frame synchronization control apparatus according to claim 2, wherein said correlation calculation means performs timing control with one correlator and performs correlation calculation a plurality of times each time one symbol data is input.   3. The frame synchronization control apparatus according to claim 2, wherein the correlation calculation means performs correlation calculation with a plurality of correlators every time one symbol data is input.   3. The frame synchronization control apparatus according to claim 2, wherein the correlation calculation means includes a correlation calculation unit that calculates the correlation between the parity corresponding to the end of the TMCC information frame and the received data.   The frame synchronization determination unit performs frame synchronization determination by evaluating the correlation value calculated by the correlation calculation unit, and establishes frame synchronization in consideration of the frame synchronization determination result and the regularity of the frame. The frame synchronization control device according to claim 2.   3. The frame synchronization control device according to claim 2, wherein the frame synchronization determination unit regards the correlation value calculated by the correlation calculation unit as being a threshold of the TMCC information frame and establishes frame synchronization when the correlation value is equal to or greater than a threshold value. .   3. The frame synchronization control apparatus according to claim 2, wherein the frame synchronization determination means stores a plurality of correlation results, and sets the symbol timing at which the correlation result is maximum as the head position of the frame. .   3. Transmission parameter output means for outputting the reference data held in the reference data holding means as a transmission parameter until frame synchronization is established by the second frame synchronization control means. The frame synchronization control device described.   2. The frame synchronization according to claim 1, wherein the reference data holding means is provided with current information indicating a current hierarchical configuration and transmission parameters, and has an encoding function for encoding and holding reference data from the current information. Control device.   2. The frame synchronization according to claim 1, wherein the reference data holding means is provided with current information indicating a current hierarchical configuration and transmission parameters, and has an encoding function for encoding and holding reference data from the current information. Control device.   The reference data holding means is provided with current information indicating a current hierarchical configuration and transmission parameters and next information indicating transmission parameters after switching, and has an encoding function for encoding and holding reference data from the current information and next information. 2. The frame synchronization control apparatus according to claim 1, wherein a copy of current information or a fixed value (all 1) is selectively given as the next information. First frame synchronization control for detecting a synchronization word from TMCC data demodulated from a received digital broadcast signal and establishing frame synchronization;
Performing a second frame synchronization control for establishing a frame synchronization by obtaining a correlation between TMCC data demodulated from the received digital broadcast signal and one or more reference data of at least a part of the expected TMCC information;
A frame synchronization control method comprising switching from the second frame synchronization control to the first frame synchronization control when frame synchronization is established by the first frame synchronization control.

Images