JP2010245811A - Coding device, decoding device and communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a coding device that generates a signal having high interference resistance and compatibility with other communication standards, or a decoding device that executes error correction decoding processing for either the signal or the signal of other communication standard, and to provide a communication method using the signal. <P>SOLUTION: First error correction coding processing is applied to an input signal so as to generate a signal that the input signal is added with parity based on the input signal. In addition, second error correction coding processing is independently applied to each of the input signal and parity, thereby generating a coded input signal and coded parity. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention provides an encoding device that generates an error correction encoded signal by performing error correction encoding processing on an input signal, or generates an output signal by performing error correction decoding processing on an input error correction encoded signal The present invention relates to a decoding device and a communication method.

  In recent years, digital communication technology has been used in various fields of wireless communication such as television broadcasting and mobile communication. Fields used in mobile communications include, for example, intelligent transport systems (ITS: Intelligent Transport Systems) that improve safety and convenience by communicating between cars and cars, and cars and base stations. There is. With regard to the use in ITS, communication standards are being developed in various countries around the world, and the use is scheduled to start in the near future. In particular, the use of IEEE802.11p is being studied in the West.

  In Japan, the frequency band to be allocated has already been determined as shown in FIG. 1, and the band can be used from 2012. However, there is a frequency band (715 to 725 MHz) that is scheduled to be allocated even though there is a digital television broadcast band on the low frequency side and a telecommunications band on the high frequency side. narrow. For this reason, it is difficult to further increase the bandwidth (5 MHz) of the guard band G for preventing interference provided on both sides of the frequency band, and it is likely to receive interference from other communication systems.

  Furthermore, interference can occur not only in other communication systems, but also in the communication system of its own. For example, in the CSMA / CA (Carrier Sense Multiple Access with Collision Avoidance) method adopted in IEEE802.11-2007, etc., communication is performed by an access method that broadcasts without receiving an ACK (Acknowledgement) signal from the receiving side. If the number of vehicles increases, the problem of interference becomes more prominent. Specifically, the number of terminals that cannot recognize each other increases due to carrier sense before transmission (hidden terminal problem), and signal interference (signal collision) due to these terminals transmitting almost simultaneously is likely to occur frequently. become.

  The influence of this signal collision can be suppressed by improving the interference (noise) resistance of the transmission signal, for example. In particular, if an error correction coding process having a high error correction capability is executed on the transmission side, the interference resistance of the transmission signal can be easily improved (see Patent Document 1).

JP 2008-17001 A

  However, the problem of transmission signal interference is a problem unique to Japan. If an original communication standard is formulated to improve the interference tolerance of the transmission signal, it is not compatible with the communication standard established in other countries, and is compatible. It may not be. In this case, the usable range of the transmitting device and the receiving device corresponding to this unique communication standard is limited to about domestic, and this is not preferable because versatility is lost. On the other hand, if a communication standard similar to a communication standard that can be formulated in other countries is formulated with emphasis on versatility, it becomes difficult to perform stable communication in Japan, which is a problem.

  Accordingly, the present invention provides an encoding device capable of generating a signal having high interference tolerance and compatibility with other communication standards, and error correction decoding for both the signals and signals of other communication standards. It is an object of the present invention to provide a decoding device capable of executing processing and a communication method using the signal.

  To achieve the above object, an encoding apparatus according to the present invention generates a parity by performing a first error correction encoding process on an input signal, and outputs the input signal and the parity. A second error correction encoding process is performed independently on each of the encoding unit, the input signal output from the first error correction encoding unit, and the parity, and the encoded input signal, And a second error correction encoding unit for generating the same parity.

  Further, the encoding apparatus having the above configuration further includes a packet configuration unit configured to add a predetermined signal to a signal based on the encoded input signal to configure a reference packet having a predetermined configuration, and the packet configuration unit includes A signal based on the coding parity is added to the end of the reference packet, and a signal based on the coding parity is added to the reference packet by changing a part of the predetermined signal included in the reference packet. It is also possible to display that.

  With this configuration, the packet generated by the encoding device of the present invention has a configuration in which a signal is added to the reference packet, so that it is compatible with a decoding device that decodes the reference packet. . In addition, it is possible to display that a signal based on the encoded parity is added without significantly changing the configuration of the reference packet.

  In the following embodiments, STF, LTF, and SIG are exemplified as predetermined signals, the previous data portion is exemplified as a signal based on a coded input signal, and the subsequent data portion is exemplified as a signal based on a coded parity. As an example of a part of the predetermined signal, a reserve bit of SIG is cited and described.

  Further, the encoding apparatus having the above configuration further includes a packet configuration unit configured to add a predetermined signal to a signal based on the encoded input signal to configure a reference packet having a predetermined configuration, and the packet configuration unit includes An encoded parity display signal indicating the state of the signal based on the encoded parity and a signal based on the encoded parity may be added to the end of the reference packet in this order.

  With this configuration, the packet generated by the encoding device of the present invention has a configuration in which a signal is added to the reference packet, so that it is compatible with a decoding device that decodes the reference packet. . Further, by adding the encoded parity display signal to the reference packet, it is possible to display that the signal based on the encoded parity is added to the reference packet. Furthermore, since any signal based on the encoded parity can be grasped by the encoded parity display signal, the degree of freedom of the signal based on the encoded parity can be ensured. It becomes possible.

  In the following embodiments, STF, LTF, and SIG are examples of the predetermined signal, the previous data portion is an example of the signal based on the encoded input signal, the subsequent data portion is an example of the signal based on the encoded parity, and the encoded parity. SIG2 is cited and described as an example of the display signal.

  In the encoding apparatus having the above configuration, the input signal may include an error detection code.

  If comprised in this way, when the said encoding input signal is decoded by a decoding apparatus, it will become possible to confirm whether the said said obtained signal is damaged. As a result, even when it is confirmed that the encoded parity is damaged in the decoding device, the signal can be output if the signal obtained by decoding the encoded input signal is not damaged. It becomes. Therefore, stable communication that is strong against interference can be performed.

  Also, the decoding apparatus of the present invention performs second error correction decoding processing independently on each of the encoded input signal and the encoded parity, and generates the input signal and the parity, respectively. And a first error correction decoding unit that performs a first error correction decoding process for correcting an error of the input signal based on the parity.

  Also, the communication method of the present invention performs the second error correction coding process independently on each of the input signal and the parity obtained by performing the first error correction coding process on the input signal. Communication is performed using the obtained encoded input signal and a signal based on the encoded parity.

  With the configuration of the present invention, it is possible to generate a signal including an encoded input signal and an encoded parity. Therefore, a compatible signal can be generated for a receiving apparatus that receives only a coded input signal but does not have a coded parity. In addition, since a signal subjected to the double error correction coding process is generated, the decoding apparatus performs a corresponding double error correction decoding process, thereby enabling strong error correction. Therefore, it is possible to realize stable communication with strong interference tolerance.

These are figures which show the frequency band allocated to ITS. These are block diagrams shown about the structural example of the transmitter in the embodiment of this invention, and a receiver. FIG. 3 is a schematic diagram illustrating an example of a packet configuration. These are block diagrams shown about the structural example of an error correction encoding part. These are the schematic diagrams shown about each state of the signal processed by an error correction encoding part. FIG. 4 is a schematic diagram illustrating configuration examples of various packets. These are block diagrams shown about the structural example of an error correction decoding part. These are the schematic diagrams of the structural example of the packet explaining 1st Example of a communication system. These are the schematic diagrams of the structural example of the packet explaining 2nd Example of a communication system.

  Embodiments of the present invention will be described below with reference to the drawings. First, outlines of configuration examples and operation examples of the transmission device and the reception device according to the embodiment of the present invention will be described.

<< Configuration of Transmitting Device and Receiving Device >>
First, a configuration example of the transmission apparatus according to the embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram illustrating a configuration example of the transmission device and the reception device according to the embodiment of the present invention. As illustrated in FIG. 2, the transmission device 1 includes an error correction encoding unit 2 that generates an error correction encoded signal by performing error correction encoding processing on an input signal of an input bit string, and an error correction encoding unit 2 The S / P converter 3 that outputs the error correction coded signal output from the rearranged signal into a plurality of parallel signals, and the parallel signal output from the S / P converter 3 respectively modulates the modulated signal. The mapping unit 4 to generate, and the IFFT unit 5 to generate a multiplexed signal by multiplexing each modulated signal output from the mapping unit 4 by inverse fast Fourier transform (hereinafter referred to as IFFT). A packet constructing unit 6 that generates a packet by adding various signals to the multiplexed signal output from the IFFT unit 5; Provided that the transmission unit 7, a.

  Next, a configuration example of the receiving apparatus according to the embodiment of the present invention will be described with reference to FIG. As illustrated in FIG. 2, the receiving device 10 includes a receiving unit 11 that converts an acquired received signal to obtain a packet, and a synchronizing unit 12 that performs a synchronization process on the packet output from the receiving unit 11 and obtains a multiplexed signal. And an FFT unit 13 that separates the multiplexed signal output from the synchronization unit 12 into respective modulation signals by fast Fourier transform (hereinafter referred to as FFT), and each modulation output from the FFT unit 13 A demapping unit 14 that demodulates the signal to generate a signal of each bit, and a P / S that generates an error correction encoded signal that becomes a bit string by aligning the signals of each bit output from the demapping unit 14 The error correction decoding which produces | generates and outputs an output signal by performing an error correction decoding process with respect to the error correction coding signal output from the conversion part 15 and the P / S conversion part 15 And an encoding unit 16.

<< Operation of Transmitting Device and Receiving Device >>
First, the operation of the transmission device 1 will be described with reference to the drawings. As illustrated in FIG. 2, first, the transmission device 1 acquires an input signal that is a bit string signal to be transmitted. Then, the error correction encoding unit 2 performs an error correction encoding process on the input signal to generate an error correction encoded signal. The details of the error correction encoding process performed by the error correction encoding unit 2 and the configuration of the error correction encoded signal will be described later.

  The error correction encoded signal generated by the error correction encoding unit 2 is rearranged into parallel signals by the S / P conversion unit 3 according to a predetermined rule. The parallel signals output from the S / P conversion unit 3 are modulated by the mapping unit 4 according to a predetermined modulation method, and a modulated signal is generated. As a modulation method, for example, BPSK (Binary Phase Shift Keying), QPSK (Quadrature Phase Shift Keying), QAM (Quadrature Amplitude Modulation), etc. can be applied, and different modulation methods are applied to each signal. It doesn't matter.

  The plurality of modulated signals output from the mapping unit 4 are IFFT and multiplexed by the IFFT unit 5 to be multiplexed signals. Note that in the case of multiplexing modulation by the OFDM (Orthogonal Frequency Division Multiplex) method, the carrier frequencies of the respective modulation signals are orthogonal.

  The multiplexed signal output from the IFFT unit 5 is packetized by the packet configuration unit 6 to generate, for example, a packet having a configuration as shown in FIG. FIG. 3 is a schematic diagram illustrating an example of a packet configuration, and the horizontal axis indicates a time axis. As described above, the transmission device 1 and the reception device 10 are compatible with the transmission device and the reception device corresponding to IEEE 802.11p. Therefore, the configuration of the packet generated by the packet configuration unit 6 also conforms to IEEE802.11p. In particular, the outline of the packet configuration is common, and FIG. 3 shows the common outline.

  As shown in FIG. 3, a preamble part is provided at the front part of the packet, and a data part is provided at the rear part. The preamble part is configured to include an STF (Short Training Field) and an LTF (Long Training Field) in this order. The data part is configured to include a plurality of DATA. Further, a SIG (Signal field) is provided between the preamble part and the data part. Note that DATA included in the data portion is a signal obtained by converting the input signal as described above.

  In the packet configuration unit 6, a preamble unit, SIG, GI (Guard Interval), and the like are added to DATA, whereby a packet as shown in FIG. 3 is configured. The GI is composed of a signal having the same pattern as a predetermined second half (for example, 1/4) of each of the LTF, SIG, and DATA, and is added to the head of each of the LTF, SIG, and DATA. Note that the function of each part of the packet will be described in the description of the operation of the receiving apparatus 10.

  And the transmission part 7 produces | generates a transmission signal by converting the packet output from the packet part 6 into a high frequency (for example, 715-725 MHz), or performing signal intensity amplification, and transmits.

  Next, the operation of the receiving device 10 will be described with reference to the drawings. As illustrated in FIG. 2, first, the reception device 10 obtains a reception signal by the reception unit 11 selectively acquiring a signal in a predetermined frequency band. Then, the acquired received signal is converted into a low frequency, or the signal is amplified to obtain a packet.

  The packet output from the receiving unit 11 has the same configuration as the packet shown in FIG. 3, but the input timing is not known and is distorted due to the influence of the transmission path. For this reason, the synchronization unit 12 performs synchronization processing to solve these problems. The synchronization unit 12 first performs packet detection, timing synchronization in the time direction of the signal, synchronization in the frequency direction, and the like using the STF and LTF of the preamble unit.

  The STF is formed, for example, by repeating the same signal (symbol s1) in the time direction by a plurality (for example, 10). Therefore, by calculating a correlation by giving a delay in the time direction, it is possible to detect that a packet has been input and to synchronize timing in the time direction. The STF symbol s1 is formed by multiplexing a plurality of carriers existing at predetermined intervals in the frequency direction. Therefore, synchronization in the frequency direction can be performed by synchronizing the symbols s1. Further, the signal strength can be adjusted using the STF.

  Since the synchronization performed by the STF is coarse, more accurate synchronization is performed by the LTF. The LTF includes, for example, a GI and a plurality of (for example, two) symbols s2 having a known pattern. Therefore, the time direction and the frequency direction can be synchronized by the same method as STF. In addition, distortion (transmission path characteristics) due to the influence of the transmission path is detected and combined for each symbol s2. Then, the distortion is reduced by correcting the signal so as to cancel the calculated transmission path characteristic. Further, as described above, GI is also added to SIG and DATA, and synchronization is performed by the synchronization unit 12.

  When synchronization is established by the synchronization unit 12, the SIG and data portion of the packet are input to the FFT unit 13, and are separated into respective modulation signals by being subjected to FFT. Each modulation signal is input to the demapping unit 14, and is converted into a bit signal by performing demodulation processing corresponding to the modulation method. Note that since the SIG length, modulation method, and the like are known (for example, BPSK), the information is demodulated by a predetermined method. In the SIG, information necessary for demodulation processing such as DATA length and modulation method is recorded. For this reason, the demapping unit 14 first demodulates the SIG to acquire this information, and then sequentially performs the demodulation process of the input DATA thereafter.

  A DATA bit signal demodulated by the demapping unit 14 is rearranged into a bit string by the P / S conversion unit 15 to generate an error correction encoded signal. Then, the error correction decoding unit 16 performs error correction decoding processing on the error correction encoded signal output from the P / S conversion unit 15 to generate an output signal. Details of the error correction decoding process performed by the error correction decoding unit 16 will be described later.

  Since the error correction encoded signal input to the error correction decoding unit 16 is affected by the transmission path, it is different from the error correction encoded signal output from the error correction encoding unit 2 (that is, Error). However, since an error is corrected by performing error correction decoding processing on the error correction encoded signal to which the error correction decoding unit 16 is input, the output signal output from the error correction decoding unit 16 is error correction code. It is substantially the same as the input signal input to the conversion unit 2.

  The transmission device 1 and the reception device 10 described above are merely examples, and other configurations may be used. For example, before and after each process may be interchanged if possible, and processes may be added or deleted. Specifically, for example, the S / P conversion unit 3 of the transmission device 1 changes (interleaves) the bit order of the error correction encoded signal by a predetermined method, and the P / S conversion unit 15 of the reception device 10 reverses the order. Processing to return to the original by performing processing (deinterleaving) or the like may be added as appropriate.

<< Error correction coding unit >>
Next, the error correction coding unit 2 described above will be described with reference to the drawings. FIG. 4 is a block diagram illustrating a configuration example of the error correction encoding unit.

  As shown in FIG. 4, the error correction coding unit 2 performs a first error correction coding process on an input signal that is input to generate a signal in which parity is added to the input signal. 21 and a second error correction encoding unit 22 for generating an error correction encoded signal by independently applying a second error correction encoding process to each of the input signal and parity output from the first error correction encoding unit 21 And comprising.

  As shown in FIG. 4, the error correction encoding unit 2 performs a concatenated encoding process that combines two types of error correction encoding processes (a first error correction encoding process and a second error correction encoding process) to generate an error. A corrected encoded signal is generated.

  The first error correction coding process performed by the first error correction coding unit 21 is a process of generating a parity (redundant part) corresponding to the signal to be processed and adding it to the signal to be processed. For example, block coding (Reed-Solomon coding, Hamming coding, etc.) can be applied. On the other hand, the second error correction encoding process performed by the second error correction encoding unit 22 is a process of converting and outputting the entire signal to be processed. For example, convolutional coding (Viterbi algorithm, turbo coding, etc.) can be applied.

  Next, the operation of the error correction coding unit 2 will be described with reference to the drawings. FIG. 5 is a schematic diagram showing each state of a signal processed by the error correction coding unit. First, when the input signal shown in FIG. 5A is input to the first error correction encoding unit 21 and the first error correction encoding unit 21 performs the first error correction encoding process, FIG. ), A signal in which parity is added to the input signal is generated. Then, this signal is input to the second error correction encoding unit 22 and subjected to a second error correction encoding process.

  In the second error correction encoding unit 22, the second error correction encoding process is independently performed on each of the input signal and the parity in FIG. At this time, the second error correction coding process is not continuously performed on the portion where the input signal and the parity are continuous, and a process of adding a delimiter is performed. For example, termination processing is performed on each of the input signal and parity.

  Specifically, for example, the head part and the tail part of the input signal and parity subjected to the second error correction coding process are set to a predetermined bit pattern (for example, all zeros). As a result, the second error correction coding process is continuously performed on the portion including the bit of the tail portion of the input signal and the bit of the head portion of the parity (that is, the portion where these signals are continuous). To prevent. In other words, the second error correction coding process is prevented from being continuously performed on the integrated input signal and parity.

  More specifically, the second error correction encoding unit 22 has a configuration in which shift registers that output the subsequent bits after temporarily storing the input bits are connected in series, and are stored in each of the shift registers. The case where the signal after the second error correction coding process is generated and output based on the bit (for example, by taking the exclusive OR of the bits stored in the respective shift registers) is described. To do.

  In this configuration, when the first bit of the signal to be processed is input to the first-stage shift register, if no bit is stored in the subsequent shift register, a signal related to the first bit is output. I can't. Further, if the processing is terminated immediately after the last bit is input, a signal related to the vicinity of the last bit cannot be sufficiently output. Therefore, processing for storing a predetermined bit (dummy bit) such as 0 in the shift register is performed at the time of processing the head or tail of the signal. By performing this process at least between the input signal and the parity, a separation is provided between the input signal and the parity, and the second error correction coding process is continuously performed on the integrated input signal and parity. To prevent it.

  As a result of the above operation, as shown in FIG. 5C, the input signal is generated by performing the second error correction coding process on the input signal, and the second error correction coding process is performed on the parity. Thus, an error correction encoded signal including the encoded parity generated in this way is obtained.

  Further, the characteristics of the packet configured using the error correction encoded signal output from the error correction encoding unit 2 of the present example will be described with reference to the drawings. FIG. 6 is a schematic diagram illustrating configuration examples of various packets.

  The packet PA is configured to include a data portion DA based on an error correction encoded signal (that is, an encoded input signal) obtained by performing only the second error correction encoding process on the input signal. In the packet PB, the second error correction encoding process is integrated with the signal (see FIG. 5B) in which the parity is added to the input signal obtained by performing the first error correction encoding process on the input signal. This is a configuration including a data portion DB based on an error correction encoded signal obtained by performing (continuously without providing the above-described delimiters). The packet PC is configured to include a data part DC based on the error correction encoded signal output from the error correction encoding part 2 of this example. In the data portion DC, a portion obtained from the encoded input signal is referred to as a previous data portion DC1, and a portion obtained from the encoded parity is referred to as a subsequent data portion DC2. The data parts DA to DC are obtained based on the respective error correction encoded signals obtained from the same input signal.

  Packets PA to PC are each provided with a preamble part and SIG, similarly to the packet shown in FIG. Although not shown in particular, the data parts DA to DC and SIG are provided with GI as in FIG. 3, and the preamble part and SIG and GI have a common configuration in the respective packets PA to PC. Note that, in the above-described IEEE 802.11p communication standard, the packet PA is used for communication. Therefore, in the following description, the packet PA is particularly referred to as a “reference packet”.

  When the receiving device configured to receive the reference packet PA receives the packet PB, only up to a portion (for example, a portion having a similar length) similar to the reference packet PA indicated by a broken line in FIG. It cannot be recognized. In this case, the data portion DA acquired by the receiving device from the reference packet PA and the part of the data portion DB acquired by the receiving device from the packet PB are different in the end portion. Therefore, each output signal obtained by performing error correction decoding processing on each signal obtained by demodulating part of the data part DA and the data part DB will be different. Therefore, the packet PB is not compatible with the receiving device that receives the reference packet PA.

  On the other hand, even when a receiving apparatus configured to receive the reference packet PA receives the packet PC, it can recognize only the same part as the reference packet PA indicated by the broken line in FIG. However, in this case, both the data part DA that the receiving apparatus acquires from the reference packet PA and the previous data part DC1 that is a part of the data part DC that the receiving apparatus acquires from the packet PC both contain a second error in the input signal. The signal is based on the signal (encoded input signal) that has been subjected to the correction encoding process, and is similar. Therefore, the respective output signals obtained by performing error correction decoding processing on the respective signals obtained by demodulating the data part DA and the previous data part DC1 are substantially equal. Therefore, the packet PC is compatible with the receiving device that receives the reference packet PA.

  Further, the data unit DC included in the packet PC is based on an error correction encoded signal obtained by subjecting an input signal to a double error correction encoding process of a first error correction encoding process and a second error correction encoding process. It will be. Therefore, if the receiving apparatus 10 including the error correction decoding unit 16 (details will be described later) capable of executing error correction decoding processing corresponding to the first and second error correction encoding processing receives the packet PC, Error correction can be performed. For this reason, it is possible to perform stable communication strong against interference.

<< Error correction decoding unit >>
Next, the error correction decoding unit 16 described above will be described with reference to the drawings. FIG. 7 is a block diagram illustrating a configuration example of the error correction decoding unit. Although the details will be described below, the error correction decoding apparatus 16 of this example can select either the error correction encoded signal obtained from the reference packet PA shown in FIG. 6 or the error correction encoded signal obtained from the packet PC. Also, it is possible to perform error correction decoding processing.

  As shown in FIG. 7, the error correction decoding unit 16 includes a second error correction decoding unit 161 that performs a second error correction decoding process on the input error correction encoded signal, and a second error correction decoding unit. A first error correction decoding unit 162 that performs a first error correction decoding process on the signal output from 161 as necessary and outputs an output signal.

  The second error correction decoding process is a process corresponding to the above-described second error correction encoding process, and generates an error-corrected signal by converting the entire signal to be processed. For example, convolutional decoding can be applied. On the other hand, the first error correction decoding process is a process corresponding to the first error correction encoding process described above, and a signal to which a parity is added based on the parity included in the signal to be processed (the signal to be processed). Error included in the signal excluding parity). For example, block decoding can be applied.

  The operations of the second error correction decoding unit 161 and the first error correction decoding unit 162 differ depending on the type of packet received by the receiving apparatus 10 (that is, the reference packet PA and the packet PC shown in FIG. 6). It will be a thing. For example, the demapping unit 14 of the receiving apparatus 10 recognizes the type of the received packets PA and PC, and the control unit (not shown) sends a control signal corresponding to the recognition result to the second error correction decoding unit 161 and Each operation is controlled by outputting the first error correction decoding unit 162 to each.

  Specifically, when the reference packet PA is received, the second error correction decoding unit 161 performs the second error correction decoding process on the entire error correction encoded signal (that is, the encoded input signal). Furthermore, the first error correction decoding unit 162 does not perform processing on the signal output from the second error correction decoding unit 161, and outputs the signal as it is.

  On the other hand, when the packet PC is received, the second error correction decoding unit 161 independently generates the second error for each of the encoded input signal included in the error correction encoded signal and the encoded parity. A correction decoding process is performed. Thereby, an input signal and parity as shown in FIG. 5B are obtained. And the 1st error correction decoding part 162 produces | generates and outputs an output signal by performing a 1st error correction decoding process to an input signal and a parity.

  In this way, it is possible to receive various packets PA and PC by making the error correction decoding process different depending on the types of received packets PA and PC. That is, it becomes possible to make the configuration compatible with various packets PA and PC.

  Further, when the receiving apparatus 10 recognizes that the packet PC has been received, a double error correction decoding process of the first error correction decoding process and the second error correction decoding process is performed to generate an output signal . In other words, double error correction can be performed, and stable communication that is strong against interference can be performed.

  As described above, the receiving apparatus 10 determines the type of the received packets PA and PC, and controls the operation of the error correction decoding unit 16 according to the determination result. A specific example of the determination method by the receiving apparatus 10 will be described with reference to an embodiment of a communication system shown below.

<< Example of Communication System >>
An embodiment of a communication system including the transmission device 1 and the reception device 10 described above will be described with reference to the drawings. In the communication system described below, not only the transmission device 1 and the reception device 10 of the present invention, but also a transmission device that transmits a reference packet PA (hereinafter referred to as a reference transmission device) and a reference packet PA are received. A configured receiving apparatus (hereinafter referred to as a reference receiving apparatus) is included, and these are mixed.

  Such a situation can be realized, for example, when the transmission device 1 or the reception device 10 described above is used in a country or region in which a communication standard (such as IEEE802.11p) that uses the reference packet PA is established. Further, for example, it can be realized when the communication standard is established in Japan and the above-described transmission device 1 and reception device 10 are used in Japan.

<First embodiment>
FIG. 8 is a schematic diagram of a configuration example of a packet for explaining the first embodiment of the communication system. FIG. 8 shows the packet shown in FIG. 3 in a simplified manner. In the present embodiment, the packet construction unit 6 of the transmission apparatus 10 sets the reserve bit of the SIG to a predetermined value r1 (for example, 1) when constructing the packet PC1. This predetermined value is different from the reserved bit value r0 (eg, 0) of the SIG of the reference packet PA transmitted from the reference transmitter.

  When receiving the reference packet PA, the reference receiving apparatus performs a second error correction decoding process on the encoded input signal obtained from the data unit DA to generate an output signal. On the other hand, when the packet PC1 is received, the previous data portion DC1 is recognized as described above, and the output signal is obtained by performing the second error correction decoding process on the encoded input signal obtained from the previous data portion DC1. Is generated. When receiving any of the packets PA and PC1 (regardless of the reserved bit values r0 and r1), the reference receiving apparatus only needs to perform the same operation.

  The receiving apparatus 10 can recognize the types of the received packets PA and PC1 by confirming the reserved bit values r0 and r1 in the demapping unit 14, for example. When the reserved bit value r0 is recognized (when the reference packet PA is received), the error correction decoding unit 16 performs a second error correction decoding process on the input encoded input signal to generate an output signal. To do. On the other hand, when the reserved bit value r1 is recognized (when the packet PC1 is received), the error correction decoding unit 16 performs the second error correction decoding process on each of the input encoded input signal and the encoded parity. At the same time, a first error correction decoding process is performed on the obtained input signal and parity to generate an output signal.

  In this way, the transmitting device 1 makes the SIG reserved bit value r1 of the packet PC1 different from that (r0) of the reference packet PA, so that the receiving device 10 can easily determine the types of the received packets PA and PC1. Can be determined. Furthermore, it is possible to prevent the transmission device 1, the reception device 10, and the packet PC1 from being significantly changed from the reference configuration (reference transmission device, reference reception device, and reference packet PA).

  In the present embodiment, the receiving device 10 can determine only whether or not the received data portion DC2 is included in the received packet. Therefore, it is preferable that the length, the modulation method, and the like of the rear data unit DC2 are defined in advance and the receiving apparatus 10 can reliably recognize and demodulate the rear data unit DC2.

<Second embodiment>
FIG. 9 is a schematic diagram of a configuration example of a packet for explaining the second embodiment of the communication system. FIG. 9 is a simplified view of the packet shown in FIG. 3 as in FIG. In the present embodiment, the packet configuration unit 6 of the transmission device 10 inserts SIG2 between the front data unit DC1 and the rear data unit DC2 when configuring the packet PC2. Note that SIG2 includes data indicating the length, modulation method, and the like of the subsequent data portion DC2 that follows.

  The reference receiving apparatus performs the same operation as in the first embodiment. That is, when the reference packet PA is received, a second error correction decoding process is performed on the encoded input signal obtained from the data part DA to generate an output signal, and when the packet PC2 is received, it is obtained from the previous data part DC1. A second error correction decoding process is performed on the encoded input signal to generate an output signal. Note that, when receiving any of the packets PA and PC2 (regardless of the presence or absence of SIG2), the reference receiving apparatus only needs to perform the same operation.

  The receiving device 10 can recognize the types of the received packets PA and PC2 by confirming the presence or absence of SIG2 by the demapping unit 14, for example. When it is confirmed that there is no SIG2 (when the reference packet PA is received), the error correction decoding unit 16 performs a second error correction decoding process on the input encoded input signal to generate an output signal. . On the other hand, when it is confirmed that SIG2 is present (when packet PC2 is received), error correction decoding section 16 performs second error correction decoding processing on each of the input encoded input signal and encoded parity. Then, a first error correction decoding process is performed on the obtained input signal and parity to generate an output signal.

  Further, when the receiving device 10 receives the packet PC2, the demapping unit 14 acquires information such as the length of the post-data unit DC2 and the modulation method from the signal obtained by demodulating SIG2. The demapping unit 14 accurately demodulates the rear data unit DC2 based on this information.

  As described above, the transmission apparatus 1 inserts SIG2 between the front data part DC1 and the rear data part DC2 to form the packet PC2, so that the reception apparatus 10 can easily determine the types of the received packets PA and PC2. It becomes possible to discriminate. Further, since the position where SIG2 is added is after the previous data portion DC1, the configuration of the portion before SIG2 is the same as that of the reference packet PA. For this reason, the packet PC2 is compatible with the reference receiving device.

  Furthermore, the degree of freedom of the rear data portion DC2 can be ensured by inputting the information of the rear data portion DC2 to the SIG2 added before the rear data portion DC2. For example, it is possible to freely select the length of the parity constituting the rear data portion DC2, the length of the rear data portion DC2, the modulation method, and the like.

  In the first and second embodiments, when the receiving device 10 receives the packets PC1 and PC2 transmitted from the transmitting device 1, interference (signal collision) frequently occurs only in the rear data portion DC2. There may occur a case where the obtained parity is corrupted and the result of the first error correction decoding process is an error. In such a case, if the previous data portion DC1 is normally received, a signal obtained by subjecting the encoded input signal obtained from the previous data portion DC1 to the second error correction decoding process (which has been normally received). In other words, a signal that is substantially equal to the input signal) may be used as the output signal.

  At this time, the presence or absence of damage may be confirmed using an error detection code (for example, a CRC (Cyclic Redundancy Check) code) added to the input signal. As a result of performing error detection using the error detection code on the signal obtained by subjecting the encoded input signal to the second error correction decoding process, there is no damage or an allowable range (for example, error Can be output as an output signal as it is.

  If comprised in this way, even if it is a case where back data part DC2 has not received normally, if front data part DC1 has received normally, it will become possible to output an output signal. Therefore, it is possible to perform communication that is more resistant to interference and stable.

  Further, the first embodiment and the second embodiment can be implemented in combination. For example, the transmitting device 1 may set the value of the reserved bit of SIG to r1 and insert SIG2 to configure a packet.

<< Other Embodiments >>
With respect to the transmission device 1 and the reception device 10 according to the embodiment of the present invention, each operation of the error correction encoding unit 2 and the error correction decoding unit 16 may be performed by a control device such as a microcomputer. Further, all or part of the functions realized by such a control device is described as a program, and the program is executed on a program execution device (for example, a computer) to realize all or part of the functions. It doesn't matter if you do.

  The transmission apparatus 1 and the reception apparatus 10 in FIG. 2, the error correction encoding unit 2 in FIG. 4, and the error correction decoding unit 16 in FIG. 7 are not limited to those described above. It can be realized by a combination of In addition, when the transmission device 12, the reception device 10, the error correction encoding unit 2, and the error correction decoding unit 16 are configured using software, a block diagram of a part realized by software is a functional block diagram of the part Is represented.

  As mentioned above, although embodiment in this invention was described, the range of this invention is not limited to this, It can add and implement various changes in the range which does not deviate from the main point of invention.

  The present invention provides an encoding device that generates an error correction encoded signal by performing error correction encoding processing on an input signal, or generates an output signal by performing error correction decoding processing on an input error correction encoded signal The present invention relates to a decoding device. The present invention also relates to a communication method for performing communication using a signal based on the error correction coded signal.

DESCRIPTION OF SYMBOLS 1 Transmission apparatus 2 Error correction encoding part 21 1st error correction encoding part 22 2nd error correction encoding part 3 S / P conversion part 4 Mapping part 5 IFFT part 6 Packet structure part 7 Transmitting part 10 Receiving apparatus 11 Receiving part 12 synchronization unit 13 FFT unit 14 demapping unit 15 P / S conversion unit 16 error correction decoding unit 161 second error correction decoding unit 162 first error correction decoding unit

Claims (6)

A first error correction encoding unit that performs a first error correction encoding process on the input signal to generate a parity, and outputs the input signal and the parity;
A second error correction encoding process is performed independently on each of the input signal output from the first error correction encoding unit and the parity, and an encoded input signal, an encoded parity, A second error correction encoding unit that respectively generates
An encoding device comprising: A packet composing unit configured to add a predetermined signal to the signal based on the encoded input signal to form a reference packet having a predetermined configuration;
The packet configuration unit adds the signal based on the encoded parity to the end of the reference packet, and changes the part of the predetermined signal included in the reference packet, thereby encoding the reference packet. The encoding apparatus according to claim 1, wherein a signal indicating that a signal based on parity is added is displayed. A packet composing unit configured to add a predetermined signal to the signal based on the encoded input signal to form a reference packet having a predetermined configuration;
The packet configuration unit adds an encoded parity indication signal indicating a state of a signal based on the encoded parity and a signal based on the encoded parity to the end of the reference packet in this order. The encoding device according to claim 1 or 2.   The encoding apparatus according to claim 1, wherein the input signal includes an error detection code. A second error correction decoding unit that independently performs a second error correction decoding process on each of the encoded input signal and the encoded parity, and generates an input signal and a parity, respectively;
A first error correction decoding unit for performing a first error correction decoding process for correcting an error of the input signal based on the parity;
A decoding device comprising:   Encoded input signal and encoding obtained by independently applying second error correction encoding processing to input signal and parity obtained by applying first error correction encoding processing to the input signal A communication method comprising performing communication using a signal based on parity.

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