JP2005348007A - Frame synchronization state detection circuit and signal decoder using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frame synchronization state detection circuit capable of accurately performing frame synchronization in a short period of time without waiting for one frame. <P>SOLUTION: A correlation processing part 57 calculates a correlation between a plurality of bit signals from a TMCC (transmission and multiplexing configuration control) signal bit determining part 53 and a TMCC signal obtained by reading the preceding TMCC signal from a channel preceding TMCC information memory 60 storing the preceding TMCC signal and decoding the preceding TMCC signal by a channel preceding TMCC decoding part 59, and a correlation peak detecting part 58 detects a correlation maximum value and detects a part showing the maximum correlation value as a frame synchronization part. A TMCC signal decoder 54 decodes the TMCC signal on the basis of a detected frame synchronizing signal. A decoding result is stored in the channel preceding TMCC information memory 60 as the preceding TMCC signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a frame synchronization state detection circuit in a communication system such as a terrestrial digital broadcasting system and a signal decoding device (reception device) using the frame synchronization state detection circuit.

As a communication system, a digital broadcast system, for example, a terrestrial digital broadcast system to which OFDM is applied is illustrated.
In terrestrial digital broadcasting systems, processing such as interleaving in the time direction and decoding processing of MPEG (Moving Picture Expert Group) is necessary. Compared with analog broadcasting, channels are usually selected in terrestrial digital broadcasting systems. It takes a long time for the video / audio signal to be played after the station.

In the terrestrial digital broadcasting system, for example, as disclosed in Japanese Patent Laid-Open No. 2003-51795 (Patent Document 1), a TMCC (Transmission and Multiplexing Configuration Control) signal decoded for each symbol is used. It is compared whether or not the same data pattern as the reference data pattern for synchronization detection for symbols is received, and the received data pattern matches the reference data pattern for synchronization detection as the first symbol of the frame, Perform frame synchronization detection.
However, since the reference data pattern for synchronization detection is transmitted once per frame, after the reference data pattern for synchronization detection is transmitted, the reference data pattern for synchronization detection of the next frame is transmitted. The frame synchronization cannot be detected unless the timing is reached. As a result, the detection timing of frame synchronization is delayed depending on the detection timing.

In order to improve the detection delay described above, Japanese Patent Laid-Open No. 2003-51795 does not wait for the result of the frame synchronization process, and uses the already held synchronization timing information to decode the broadcast wave by the terrestrial digital broadcasting system. A technique for initiating processing is disclosed.
JP 2003-51795 A

  However, even if the technique disclosed in Japanese Patent Application Laid-Open No. 2003-51795 is applied, the following problems are still recalled.

(1) Immediately after turning on the receiver of the terrestrial digital broadcasting system, the synchronization timing information held before the power is turned off is used. After the receiver is turned off, the receiver power is turned on. If the time until the power is turned on is long, the held synchronization timing information is completely different from the synchronization timing information when the power is turned on. As a result, inconsistent synchronization timing information is used.
(2) The above problem is that, even when a channel is selected after a predetermined time has elapsed after selecting a channel, the synchronization timing information held for that channel and the synchronization timing information on the current transmission side are Since they are different, the same problem as described above occurs. In other words, since the symbol counter in the frame synchronization state detection circuit during that time cannot be completely synchronized with the transmission side, the symbol of the transmission signal and the counter value held by the receiver are deviated, and synchronization is accurately performed. I can't take it.

(3) The clock used for reproduction at the receiver of the digital terrestrial broadcasting system is slightly shifted in time. For example, if a 1 ppm clock shift occurs for a symbol period of about 1 ms, a shift of 1 symbol occurs in 10 ³ seconds (about 16 minutes). The synchronization timing is shifted due to the shift of the symbol accompanying the shift of the clock.

(4) In a terrestrial digital broadcasting system, it is essential to perform error correction processing in order to eliminate the influence of noise, multipath, and the like.
For error correction processing, it is necessary to accurately detect symbol synchronization. However, for example, the technique disclosed in Japanese Patent Application Laid-Open No. 2003-51795 starts decoding processing without performing synchronization detection, and thus cannot be applied to a terrestrial digital broadcasting system that performs error correction processing. In other words, the technique disclosed in Japanese Patent Laid-Open No. 2003-51795 is a decoding process without an error correction process that eliminates the influence of noise, multipath, and the like.

  (5) Since the reference data pattern for synchronization detection has only a limited length of, for example, about 16 bits, the probability of detecting the synchronization state is sufficient in a poor environment where noise, multipath, etc. occur frequently. It is difficult to raise.

An object of the present invention is to provide a frame synchronization state detection circuit that can perform frame synchronization accurately and in a short time.
Another object of the present invention is to provide a decoding device or a receiving device using such a frame synchronization state detection circuit.

According to a first aspect of the present invention, there is provided a frame synchronization state detection circuit for detecting a frame synchronization state using a signal decoded for each symbol,
The correlation between each bit of the signal decoded for each symbol decoded last time and a predetermined bit of the signal decoded for each symbol to be decoded this time is obtained, and the maximum correlation value among the obtained correlations is obtained. A frame synchronization state detection circuit is provided that includes a first frame synchronization state detection circuit that detects a frame synchronization state when a portion is detected.

  Preferably, the signal decoded for each symbol includes a signal of a specific bit pattern indicating a frame synchronization state, and when the arrival of the signal of the specific bit pattern is detected, a frame synchronization state is detected. A two-frame synchronization state detection circuit is further provided, and the detection signal of the first frame synchronization state detection circuit or the one-frame synchronization state detection circuit is output as a frame synchronization signal.

  Preferably, the first and / or second frame synchronization state detection circuit is applied to a receiving apparatus of a digital communication system that performs OFDM modulation / demodulation, and the signal decoded for each symbol is a TMCC signal.

According to the second aspect of the present invention, OFDM demodulation means for OFDM-demodulating a signal in which a TMCC signal is inserted into broadcast data is OFDM-modulated, frame synchronization is detected for the OFDM demodulated data, and a TMCC signal is detected. Frame synchronization / TMCC signal decoding means for decoding, and error correction processing decoding means for decoding the OFDM demodulated data with reference to frame synchronization detected by the frame synchronization / TMCC signal decoding means and decoding the error. Prepared,
The frame synchronization / TMCC signal decoding means includes a TMCC signal extracting means for extracting a TMCC signal from the OFDM demodulated signal, a decoding means for decoding the extracted TMCC signal, and a TMCC signal for determining a bit of the decoded TMCC signal Bit determining means; TMCC signal decoding means for decoding the result of the TMCC signal bit determining means; previous TMCC signal holding means for holding the previous TMCC signal; and TMCC signal for decoding the previous held TMCC signal. A decoding means, a correlation processing means for obtaining a correlation with a predetermined bit among the bits determined by the TMCC signal bit determining means among the decoded TMCC signal and the TMCC signal to be decoded this time, and the correlation The frame when the maximum correlation value is detected for the correlation obtained by the processing means First frame synchronization state detecting means for detecting the initial state, and symbol counter means for counting symbols according to the symbol synchronization signal and stopping counting when the frame synchronization detection signal is input from the first frame synchronization state detecting means And a TMCC signal decoding means for decoding the bit data of the TMCC signal determined by the TMCC signal bit determining means with reference to the count value of the symbol counter means.

  Preferably, the TMCC signal includes a signal having a specific bit pattern indicating a frame synchronization state, and detects a frame synchronization state when detecting arrival of the signal having the specific bit pattern. Means for outputting the detection signal of the first frame synchronization state detection means or the detection signal of the one frame synchronization state detection means to the symbol counter means as a frame synchronization signal.

  More preferably, there is further provided means for outputting the previous TMCC signal held in the previous TMCC signal holding means as a decoding result of the TMCC signal decoding means before decoding one frame in the TMCC signal decoding means.

According to the frame synchronization state detection circuit of the present invention, for example, parameters embedded in a signal such as a TMCC signal are determined for each broadcast, and they are usually hardly changed. The correlation between the previous signal decoding result and the current signal is obtained, and if the degree of correlation is high, frame synchronization is detected as frame synchronization has been established. Synchronization can be detected without waiting, and the synchronization detection timing becomes quick.
As a result, the decoding apparatus using the frame synchronization state detection circuit of the present invention can perform decoding processing quickly.

  In the frame synchronization state detection circuit of the present invention, in principle, a special code for synchronization detection such as a unique word may not be used, and without waiting for the arrival of a unique word for each frame, Frame synchronization can be achieved.

  According to the frame synchronization state detection circuit of the present invention, error correction processing is performed without waiting for one frame using the previous decoded signal before the signal is decoded in the signal decoding means by utilizing the previous decoded signal. Means processing can be performed.

  Of course, according to the frame synchronization state detection circuit of the present invention, for example, frame synchronization detection processing can be performed using a synchronization detection word such as a unique word.

  In addition, in order to confirm whether or not the frame synchronization has been lost even after the frame synchronization is once taken, it is necessary to perform the same process as capturing the frame synchronization. Since the comparison with a large number of bits in the correlation processing means can be used, more accurate frame synchronization detection can be performed.

  In addition, according to the frame synchronization state detection circuit of the present invention, stable frame synchronization can be detected even in a poor environment such as noise and multipath effects.

  Furthermore, according to the frame synchronization state detection circuit of the present invention, it can be used even when the channel is first selected after the power is turned on, and operates even if the channel selection time interval is wide.

  When the above-described frame synchronization state detection circuit according to the present invention is applied to a signal decoding device, a receiving device, a television receiver, and the like, the above-described effects can be obtained.

Terrestrial digital broadcasting system An terrestrial digital broadcasting system as an example to which the frame synchronization state detection circuit and the signal decoding apparatus (receiving apparatus) of the present invention are applied will be described with reference to FIGS.
FIG. 1 shows a digital terrestrial broadcasting system to which orthogonal frequency division multiplexing (OFDM) modulation is applied as an example to which a frame synchronization state detection circuit and a signal decoding apparatus (receiving apparatus) according to the present invention are applied. For example, it is a schematic block diagram of an ISDB-T (Japan Digital Terrestrial Broadcasting) system. FIG. 1 illustrates a schematic configuration of ISDB-T, and illustrations of portions not related to the present invention are omitted.

The ISDB-T system includes a transmission device 10 and a reception device 20.
The transmission apparatus 10 includes a data generation unit 11, a TMCC signal generation unit 12, a TMCC signal insertion unit 13, an inverse fast Fourier transform (IFFT) processing unit 14, and a parallel / serial converter (P / S converter) 15, a wireless transmission unit 16, and a transmission antenna 17.
The receiving device 20 includes a receiving antenna 21, a tuner 22, a serial / parallel converter (S / P converter) 23, a fast Fourier transform (FFT) processing unit 24, and an error correction processing unit 25. And a frame synchronization / TMCC signal decoding unit 26.

The operation of the transmission device 10 will be described.
The data generation unit 11 generates a broadcast signal, for example, a video signal, an audio signal, and a control signal, which are data to be decoded in the receiving device 20.
The TMCC signal generation unit 12 generates a transmission and multiplexing configuration control signal (TMCC: Transmission and Multiplexing Configuration Control signal).
As illustrated in FIG. 2, the TMCC signal insertion unit 13 inserts a TMCC signal into the data output from the data generation unit 11.
FIG. 2 is a signal waveform diagram in which a TMCC signal is inserted into data. The horizontal axis represents frequency, and the vertical axis represents amplitude. The TMCC signal is inserted between data of a predetermined frequency.

The IFFT processing unit 14 performs OFDM modulation by collectively performing inverse fast Fourier transform processing on signals obtained by inserting TMCC signals into data.
The P / S converter 15 converts the OFDM-modulated parallel signal into a serial signal.
The wireless transmission unit 16 converts the output signal of the P / S converter 15 into a radio frequency (RF) signal and emits it from the transmitting antenna 17 toward the receiving device 20 in the air.

The operation of the receiving device 20 will be described.
The receiving antenna 21 receives the RF signal transmitted from the transmitting antenna 17.
The signal received by the receiving antenna 21 may have noise superimposed thereon or affected by multipath, but OFDM modulation has a feature that it is not easily affected by this kind of disturbance.
The tuner 22 takes out a signal of a desired channel designated by the user from the RF signals for a plurality of channels received by the receiving antenna 21 and converts it into a baseband signal.
The S / P converter 23 converts the baseband serial signal extracted by the tuner 22 into a parallel signal.
The FFT processing unit 24 performs the fast Fourier transform on the output signal of the S / P converter 23, that is, performs an OFDM demodulation process by performing the reverse process of the IFFT processing unit 14, and the TMCC signal is inserted into the data. Extract data from signal.
The error correction processing unit 25 performs error correction processing on the data extracted by the FFT processing unit 24 and decodes data corresponding to the data generated by the data generation unit 11.

  In the error correction in the error correction processing unit 25, the coding rate embedded in the TMCC signal and frame synchronization information are required. Therefore, the frame synchronization / TMCC signal decoding unit 26 detects the decoding process (decoding) of the TMCC signal and the frame synchronization signal based on the output signal of the FFT processing unit 24. Details of the frame synchronization / TMCC signal decoding unit 26 will be described later.

FIG. 3 is a configuration diagram of the TMCC signal.
In the present embodiment, a total of 204 bits are prepared for the TMCC signal. In the TMCC signal insertion unit 13, for example, the TMCC signal is modulated by a differential binary shift keying (DBPSK) method, as shown in FIG. Are allocated to predetermined subcarriers and transmitted.
At this time, the same 1-bit data is all assigned to the carriers for TMCC signals in one OFDM symbol. Therefore, 2040 OFDM symbols have one TMCC signal (204 bits). These 204 symbols are collectively referred to as one frame.

FIG. 4 is a diagram illustrating what information (signal) the 204 bits of the TMCC signal have. The TMCC signal has the following configuration.
(1) t ₀ : 1-bit differential binary shift keying modulation reference data (2) t _{1 to} t ₁₆ : _16- bit synchronization detection known as unique word for frame synchronization detection Signals The unique words W1, W2 have the following values, for example.
W1 = 001101101101110
W2 = 11001000010000010001
The unique words W1 and W2 in this embodiment have inverted values and come alternately every frame.
(3) t _{17 to} t ₁₉ : 3-bit segment identification information Information for identifying synchronous modulation or differential modulation, etc. (4) t _{20 to} t ₁₂₁ : 102-bit TMCC signal Modulation method, coding rate, interleave length (5) t _{122 to} t ₂₀₃ : 82-bit parity bits Parity bits obtained by converting data (information) of (1) to (4) into DSCC codes (difference set cyclic codes)

Thus, in order to correctly extract the TMCC signal, it is necessary to first find the location of the beginning of the frame, and a unique word is added for this purpose. That is, the unique word is reference data for detecting the synchronization of each frame.
Therefore, when the frame synchronization / TMCC signal decoding unit 26 of the receiving device 20 receives and detects whether the data output from the FFT processing unit 24 matches the unique word W1 or W2, and matches Outputs a frame synchronization detection signal S26 to the error correction processing unit 25, assuming that frame synchronization has been detected.
When the frame synchronization detection signal S50 is input, the error correction processing unit 25 performs error correction processing on the data output from the FFT processing unit 24 using the frame synchronization detection signal S26 as the start of a frame.
The receiving device 20 transmits the broadcast signal that has been subjected to the error correction processing by the error correction processing unit 25 to, for example, a television receiver for reproduction (decoding).

Frame Synchronization / TMCC Signal Decoding Unit of First Embodiment With reference to FIG. 5, the frame synchronization / TMCC signal decoding unit 50 of the first embodiment of the present invention will be described.
The frame synchronization / TMCC signal decoding unit 50 is applied to the frame synchronization / TMCC signal decoding unit 26 of the receiving device 20 of FIG.
The frame synchronization / TMCC signal decoding unit 50 according to the first embodiment of the present invention includes a TMCC signal extraction unit 51, a differential decoding unit 52, a TMCC signal bit determination unit 53, a TMCC signal decoder 54, and a symbol counter. 55 and a frame synchronization detection unit 56.

The TMCC signal extraction unit 51 extracts the TMCC signal of the channel specified by the user from the signals applied from the FFT processing unit 24 and outputs the TMCC signal to the differential decoding unit 52.
The differential decoding unit 52 differentially decodes the extracted TMCC signal.
The TMCC signal bit determination unit 53 determines the bit of the TMCC signal decoded by the differential decoding unit 52, extracts the TMCC bit, and inputs the TMCC bit to the shift register of the frame synchronization detection unit 56.

The frame synchronization signal detection unit 56 detects whether or not the TMCC bit extracted by the TMCC signal bit determination unit 53 matches any of the 16-bit unique words W1 or W2 stored in the memory.
The frame synchronization signal detection unit 56 includes, for example, a first shift register 561 configured by cascade connection of 16-bit 1-bit delay circuits (DL), a comparator 562, and a 16-bit 1-bit delay circuit (DL ) Are cascade-connected to form a second shift register 563.
The second shift register 563 holds the unique word W1 and / or W2.
The 16-bit TMCC signal extracted by the TMCC signal bit determination unit 53 is sequentially input to the first shift register 561, and the 1-bit delay circuit (DL) is sequentially transferred for each symbol received according to the symbol synchronization signal. It will be done.
The comparator 562 detects frame synchronization when the unique word held in the second shift register 563 matches the TMCC signal extracted by the TMCC signal bit determination unit 53 transferred to the first shift register 561. As a result, the frame synchronization detection signal S56 is output to the symbol counter 55.
Since the unique words W1 and W2 come alternately every frame, the second shift register 563 is configured to hold two unique words W1 and W2, and the comparator 562 alternately sets the unique words W1 or W2. It may be read and subjected to the above-described comparison determination process, or may be held in one second shift register 563 each time a unique word arrives.

The symbol counter 55 counts the input symbols according to the symbol synchronization signal. When the frame synchronization signal detection unit 56 is input, the symbol counter 55 stops the symbol counting process and outputs a frame synchronization detection timing signal S55 including the count value at that time to the TMCC signal decoder 54.
The TMCC signal decoder 54 performs decoding processing of the TMCC signal with reference to the symbol position detected in synchronization included in the frame synchronization detection timing signal S55.

As described above, the frame synchronization / TMCC signal decoding unit 50 according to the first embodiment detects whether or not the bit of the received TMCC signal matches the unique words W1 and W2, and detects the synchronization of the frame. The TMCC signal is decoded according to the detected frame synchronization timing.
According to the frame synchronization / TMCC signal decoding unit 50 of the first embodiment, the above problems (1) to (4) are overcome. That is, according to the frame synchronization / TMCC signal decoding unit 50 of the first embodiment, (a) synchronization detection immediately after power-on of the receiving device 20 is possible, and (b) a predetermined time after selecting a certain channel. Even if the channel is selected again after the elapse of time, synchronization can be achieved. (C) Even if a time lag of the clock occurs, the synchronization timing does not shift, and (d) the source of accurate synchronization. Thus, error correction processing can be performed.
However, the frame synchronization / TMCC signal decoding unit 50 of the first embodiment still encounters the following problems.

(A) Since the reference data pattern (unique word) for synchronization detection is transmitted once per frame, after the unique word for synchronization detection is transmitted, the unique word W for synchronization detection of the next frame is transmitted. The frame synchronization cannot be detected without waiting until the timing at which is transmitted. As a result, the detection timing of frame synchronization is still delayed depending on the detection timing.
(B) Since the unique word W for synchronization detection has a limited length of about 16 bits, for example, even if OFDM modulation is performed, the synchronization state is maintained in a poor environment where noise, multipath, etc. occur frequently. It may be difficult to sufficiently increase the probability of detection.

Frame Synchronization / TMCC Signal Decoding Unit of Second Embodiment With reference to FIGS. 6 and 7, the frame synchronization detection circuit of the second embodiment of the present invention will be described.
Similarly to the frame synchronization / TMCC signal decoding unit 50 of the first embodiment, the frame synchronization / TMCC signal decoding unit 50A of the second embodiment is incorporated in the frame synchronization / TMCC signal decoding unit 26 of the receiving device 20 of FIG. Applied.
The frame synchronization state detection circuit according to the second embodiment overcomes the problems (1) to (4) described above and overcomes the problems (b) and (b) described above.

The frame synchronization / TMCC signal decoding unit 50A according to the second embodiment of the present invention includes a TMCC signal extraction unit 51, a differential decoding unit 52, a TMCC signal bit determination unit 53, a TMCC signal decoder 54, and a symbol counter. 55 and a frame synchronization detection unit 56. However, the symbol counter 55 is slightly different from the symbol counter 55 in the frame synchronization / TMCC signal decoding unit 50 of the first embodiment.
The frame synchronization / TMCC signal decoding unit 50A further includes a correlation processing unit 57, a correlation peak detection unit 58, a TMCC signal decoding unit 59, a channel TMCC information memory 60, a first selector 61, a second selector 62, And a control processing unit 65.

  Before describing the details of the frame synchronization / TMCC signal decoding unit 50A of the second embodiment, the basic concept of the frame synchronization / TMCC signal decoding unit 50A of the second embodiment and the circuit configuration therefor will be described.

(1) First Basic Concept and Circuit Configuration As an actual operational background of the ISDB-T system 1, parameters embedded in the TMCC signal are determined for each broadcast, and they are usually hardly changed. . By utilizing this fact, the frame synchronization / TMCC signal decoding unit 50A according to the second embodiment of the present invention holds the decoding result of the previous TMCC signal of a certain channel in the memory, and the decoding result of the previous TMCC signal. And the correlation with the current TMCC signal. If the degree of correlation is high, it can be estimated that frame synchronization has been achieved.

Therefore, in the frame synchronization / TMCC signal decoding unit 50A of the second embodiment, the channel previous TMCC information memory 60 that holds the previous TMCC signal for each channel, and the TMCC signal of the channel designated from the channel previous TMCC information memory 60 The second selector 62 for selecting and outputting the channel, the channel previous TMCC signal decoding unit 59 for decoding the TMCC signal selected and output from the second selector 62, the result of the channel previous TMCC signal decoding unit 59, and the TMCC signal bit determining unit 53 A correlation processing unit 57 that obtains a correlation with the result and a correlation peak detection unit 58 that obtains the maximum correlation value obtained by the correlation processing unit 57 are provided.
The control processing unit 65 performs overall control processing of the frame synchronization / TMCC signal decoding unit 50A. For example, the control processor 65 holds the previous TMCC signal in the corresponding channel portion of the channel previous TMCC information memory 60, or from the second selector 62. A second selection signal SEL2 for selectively outputting the previous TMCC signal of the corresponding channel is output.

  According to such a configuration and concept, frames can be basically synchronized without using a unique word and without waiting for the arrival of a unique word in each frame.

(2) Second Basic Concept and Circuit Configuration The previous TMCC information memory 60 holds the previous TMCC signal. Accordingly, before the TMCC signal is decoded by the TMCC signal decoder 54, the TMCC signal of the previous channel held in the channel previous TMCC information memory 60 is output through the first selector 61 for one frame. The error correction processing unit 25 can perform error correction processing of the TMCC signal without waiting for the error.

  Therefore, holding the TMCC signal for each channel in the channel previous TMCC information memory 60, adding the first selector 61, and using the second selection signal SEL2 from the control processing unit 65 from the channel previous TMCC information memory 60. The TMCC signal of the corresponding channel is also output to the first selector 61, the first selection signal SEL1 is output to the first selector 61, and the previous TMCC signal selected and output from the second selector 62 is output to the first selector 61. 61 can also be output.

(3) Third Basic Concept and Circuit Configuration The third basic concept is provided with a frame synchronization signal detection unit 56 similar to the frame synchronization signal detection unit 56 in the frame synchronization / TMCC signal decoding unit 50 of the first embodiment. A frame synchronization detection process using the unique words W1 and W2 is performed.
That is, assuming that the TMCC signal held in the channel TMCC information memory 60 is different from that currently being received, a frame having the same circuit configuration as the frame synchronization / TMCC signal decoding unit 50 of the first embodiment The synchronization signal detection unit 56 performs a frame synchronization detection process using only the synchronization signals (unique words W1, W2).

  From the above, the symbol counter 55 that counts the symbol synchronization signal stops counting the symbol synchronization signal in accordance with either the correlation peak detection signal S58 or the frame synchronization detection signal S56 from the correlation peak detector 58, and The frame synchronization detection timing signal S55A is output to the signal decoder 54.

(4) Fourth basic concept and circuit configuration Even after the frame synchronization is established, it is necessary to perform the same processing as the capture of the frame synchronization in order to confirm whether the frame synchronization is lost. In the frame synchronization / TMCC signal decoding unit 50A of the second embodiment, in comparison with the 16-bit unique word (synchronization signal) in the frame synchronization detection unit 56 in the frame synchronization / TMCC signal decoding unit 50 of the first embodiment Since the comparison with 204 bits in the correlation processing unit 57 can be used, more accurate frame synchronization detection can be performed.
The circuit configuration for this is the same as the circuit configuration for the first basic concept.

Details of the operation of the frame synchronization / TMCC signal decoding unit 50A of the second embodiment will be described below.
The operations of the TMCC signal extraction unit 51, the differential decoding unit 52, the TMCC signal bit determination unit 53, and the TMCC signal decoder 54 are the same as those in the frame synchronization / TMCC signal decoding unit 50 of the first embodiment described above. 51 and the operations of the differential decoding unit 52, the TMCC signal bit determination unit 53, and the TMCC signal decoder 54.

  The TMCC signal extraction unit 51 extracts the TMCC signal of the channel specified by the user from the signals applied from the FFT processing unit 24 and outputs the TMCC signal to the differential decoding unit 52. The differential decoding unit 52 differentially decodes the extracted TMCC signal.

The control processing unit 65 extracts the TMCC signal of the channel corresponding to the channel designated by the user from the channel previous TMCC information memory 60 via the second selector 62 and outputs it to the channel previous TMCC signal decoding unit 59.
The channel previous TMCC signal decoding unit 59 decodes the input TMCC signal of the previous channel and outputs it to the correlation processing unit 57. The channel previous TMCC signal decoding unit 59 has the same circuit configuration as the TMCC signal decoder 54, but the ambassador to be decoded is different.
As described as the first basic concept, in the actual operation of the ISDB-T system 1, the parameters embedded in the TMCC signal are determined for each broadcast, and they are usually hardly changed. Therefore, the control processing unit 65 holds the decoding result of the previous TMCC signal of each channel in the corresponding area of the channel previous TMCC information memory 60, and when the frame synchronization detection is performed, the control processing unit 65 applies the corresponding result from the channel previous TMCC information memory 60. The previous TMCC signal of the channel is taken out and decoded by the channel previous TMCC signal decoding unit 59. In the correlation processing unit 57, the correlation between the decoding result and the current TMCC signal (bit) from the TMCC signal bit determining unit 53 is obtained. Let me ask.
The correlation peak detector 58 detects the one having the highest degree of correlation.

  FIG. 6 is a detailed circuit configuration diagram of the correlation processing unit 57, the correlation peak detection unit 58, and the frame synchronization signal detection unit 56.

  The circuit configuration of the frame synchronization signal detection unit 56 is the same as the circuit configuration illustrated in FIG.

The correlation processing unit 57 includes a first shift register 571 composed of a plurality of unit delay elements, a second shift register 573 composed of a plurality of unit delay elements, and a correlation processing unit 572.
The TMCC signal from the TMCC signal bit determination unit 53 is input to the first shift register 571 in a predetermined bit unit, and is sequentially transferred in the unit delay element for each reception of the symbol in accordance with the symbol synchronization signal. This operation is the same as the operation of the first shift register 561 in the frame synchronization signal detection unit 56.
The second shift register 573 holds all bits (204) of the TMCC signal decoded by the channel previous TMCC signal decoding unit 59.
The correlation processing unit 572 obtains a correlation between the TMCC signal bit data held in the first shift register 571 and the TMCC signal obtained by decoding the previous TMCC signal held in the second shift register 573.
The second shift register 573 has a capacity capable of holding all the bits (204) of the TMCC signal. On the other hand, as the number of bits of the first shift register 571 is larger, a highly reliable correlation with the TMCC signal bits held in the second shift register 573 can be obtained. However, as the number of bits increases, the circuit configuration becomes complicated and the time for obtaining the correlation becomes longer. Therefore, the number of bits of the first shift register 571 is determined in consideration of the simplification of the circuit configuration and both the correlation processing speed and the reliability. Considering that the number of bits of the unique word in the frame synchronization signal detection unit 56 is 16 bits in the present embodiment, the same level of reliability as the frame synchronization detection using the unique word in the frame synchronization signal detection unit 56 is performed. In order to maintain the characteristics, the number of bits of the first shift register 571 is set to 16 bits.

The correlation peak detection unit 58 includes a sum calculation unit 581, a maximum value detection unit 582, and a frame synchronization position detection unit 583.
The sum calculation unit 581 calculates the correlation value obtained by the correlation processing unit 572 of the correlation processing unit 57.
The maximum value detector 582 obtains the maximum correlation value calculated by the sum calculator 581. The frame synchronization position detection unit 583 detects the position where the maximum correlation value obtained by the maximum value detection unit 582 has occurred, that is, detects the frame synchronization position, and indicates the frame synchronization detection position. The correlation peak detection signal S58 is output to the symbol counter 55.

  An example of how the correlation processor 572 obtains the correlation and how the correlation peak detector 58 detects the correlation peak will be described. However, in order to simplify the description, the second shift register 573 is 14 bits and the first shift register 571 is 4 bits.

(1) The second shift register 573 holds the following 14-bit data as a result of decoding the previous TMCC signal.
[1 -1 -1 1 -1 1 1 -1 -1 1 -1 1 1 1 -1]

  (2) Bit data of [1 −1 1 1] is input to the first shift register 571 for each symbol from the TMCC signal bit determination unit 53 according to the symbol synchronization signal.

(3) When [1 −1 1 1] is transferred in the first shift register 571 and the correlation is obtained with the bit data of the second shift register 573 at the following position, the correlation processing is performed in the following positional relation. In part 572, the correlation was determined.
[1 -1 -1 1 -1 1 1 -1 -1 1 -1 1 1 1 -1]
[1 -1 1 1]

(4) When the bit value is the same as “1” and when the bit value is different, “−1”, the correlation result in the correlation processing unit 572 is as follows.
[1 1 -1 1]

The sum at this time obtained by the sum calculation unit 581 of the correlation peak detection unit 58 is 2, and the maximum value detection unit 582 shifts the bit data from the TMCC signal bit determination unit 53 in the first shift register 571, It is assumed that the sum of the correlation results when correlated with each place of the bit data of the second shift register 573 is the maximum value.
Therefore, there is a maximum correlation value in the bit arrangement.

(5) Next, the frame synchronization position detector 583 estimates the frame synchronization position where the correlation is maximized.
When this correlation result [1 1 -11] is compared with the bit data [1 -1111] input to the first shift register 571, the same time is set to "-1" and the different time is set to "1". -1 1 1 -1].
When this value is added sequentially, [−1 0 1 −1] is obtained, and the frame synchronization position detection unit 583 detects that there is frame synchronization at the time when the value changes from “0” to “1”. The position detector 583 outputs a correlation peak detection signal S58 to the symbol counter 55.

  As described above, the correlation processing in the correlation processing unit 57 and the correlation peak detecting unit 58 can be performed in a short time with a relatively simple circuit configuration.

  The frame synchronization signal detection unit 56 also performs processing to determine whether the unique words W1 and W2 match the bit data of the TMCC signal extracted from the TMCC signal bit determination unit 53.

If the bit data of the TMCC signal extracted from the TMCC signal bit determination unit 53 is exactly the unique words W1 and W2, the frame synchronization detection by the frame synchronization signal detection unit 56 and the frame by the correlation processing unit 57 are detected. The detection of synchronization is almost the same.
However, when the frame synchronization signal detection unit 56 and the correlation processing unit 57 perform the processing other than the unique words W1 and W2, the frame synchronization detection by the frame synchronization signal detection unit 56 is not performed, and the head of the next frame is detected. It must wait until there is a unique word W at. On the other hand, the correlation processing unit 57 outputs the correlation peak detection signal S58 at the portion where the correlation is highest in any bit arrangement of the TMCC signal decoded last time and the bit arrangement of the current TMCC signal. Therefore, the correlation processing unit 57 can detect frame synchronization in any part of the bit arrangement obtained by restoring the previous TMCC signal. Generally speaking, the correlation processing unit 57 detects the frame synchronization. Get faster.

As a result, if the frame synchronization detection timing signal S55 is generated from the symbol counter 55 using the correlation peak detection signal S58, and the TMCC signal is decoded by the TMCC signal decoder 54 at that timing, the frame synchronization / The TMCC signal can be decoded more quickly than the decoding in the TMCC signal decoding unit 50, and the error correction processing unit 25 can perform the error correction processing quickly using such decoded TMCC signal.
In this case, the control processing unit 65 outputs a first selection signal SEL1 for selecting and outputting the result of the TMCC signal decoder 54 to the first selector 61.
The control processing unit 65 stores the result of decoding the TMCC signal by the TMCC signal decoder 54 in the corresponding channel portion of the channel previous TMCC information memory 60 to prepare for the next processing.

  As a result of the above processing, it is possible to broadcast from a television receiver without a large time delay after selecting a channel.

As described in the third basic concept, the frame synchronization signal detection unit 56 functions in the same manner as in the first embodiment when the TMCC signal of the previous channel is not stored in the channel previous TMCC information memory 60.
That is, assuming that the TMCC signal held in the channel TMCC information memory 60 is different from that currently being received, frame synchronization detection processing using only the synchronization signals (unique words W1, W2) is also performed. The processing function of the frame synchronization / TMCC signal decoding unit 50 according to the first embodiment is also provided.

  Further, as described in the second basic concept and circuit configuration, since the previous TMCC signal is held in the channel previous TMCC information memory 60, before the TMCC signal decoder 54 decodes the TMCC signal, the channel previous TMCC signal is stored. When the TMCC signal of the previous channel held in the information memory 60 is output via the first selector 61 and the error correction processing unit 25 performs error correction processing of the TMCC signal without waiting for one frame. Therefore, the control processing unit 65 outputs the first selection signal SEL1 to the first selector 61 and the second selection signal SEL2 to the second selector 62.

  In addition, even after the frame synchronization is established by the correlation processing unit 57 and the correlation peak detection unit 58, it is necessary to perform the same process as capturing the frame synchronization in order to check whether the frame synchronization is lost. Even at this time, the comparison with the 204 bits of the TMCC signal by the correlation processing unit 57 and the correlation peak detection unit 58 is used instead of the comparison with the 16-bit unique word (synchronization signal) in the frame synchronization signal detection unit 56. Therefore, more accurate frame synchronization detection can be performed.

  In practice, some TMCC signal parameters are difficult to predict. For such bits, the TMCC signal decode output of the TMCC signal decoder 54 is set to a value between two values (0.5 for 0/1, 0 for -1 / + 1). Thus, these bits can be ignored during the cross-correlation processing in the correlation processing unit 572 of the correlation processing unit 57.

  As described above, according to the frame synchronization / TMCC signal decoding unit 50A, it is possible to quickly detect the frame synchronization of the TMCC signal in a certain unit, and as a result, the processing and decoding processing of the error correction processing unit 25 are performed quickly. be able to.

  In addition, even in a poor environment where the influence of noise and multipath is great, by applying cross-correlation using a TMCC signal of many bits in the correlation processing unit 57 and the correlation peak detection unit 58, stable frame synchronization detection is possible. Is possible.

  Of course, according to the frame synchronization / TMCC signal decoding unit 50A of the second embodiment, it can be used even when the channel is first selected from the power-on of the receiving device 20, and even if the channel selection time interval is widened. Can be used without any problem.

The above is the ISDB-T system 1 in the digital terrestrial broadcasting system as a preferred embodiment of the frame synchronization state detection circuit and the signal decoding apparatus using the same according to the present invention. The signal decoding apparatus using the same is not limited to application to a terrestrial digital broadcasting system that performs OFDM modulation / demodulation and a communication system that uses a TMCC signal.
The frame synchronization detection by the frame synchronization signal detector 56 described as the first embodiment can be applied to other communication systems.
Further, the correlation processing unit 57 correlates the previous TMCC signal stored in the channel previous TMCC information memory 60 and the current TMCC signal described as the second embodiment, and the correlation peak detection unit 58 determines the maximum value. The technique of using the position where the correlation has occurred as the frame synchronization portion is not limited to the terrestrial digital broadcasting system.

FIG. 1 is a configuration diagram of a digital terrestrial broadcasting system (ISDB-T) as an example to which a frame synchronization state detection circuit and a receiving apparatus according to the present invention are applied. FIG. 2 is a signal waveform diagram in which a TMCC signal is inserted into data in the transmission apparatus in FIG. FIG. 3 is a block diagram of the TMCC signal illustrated in FIG. FIG. 4 is a diagram illustrating the contents of the TMCC signal illustrated in FIG. FIG. 5 is a configuration diagram of the frame synchronization state detection circuit according to the first embodiment of this invention. FIG. 6 is a block diagram of a frame synchronization state detection circuit according to the second embodiment of the present invention. FIG. 7 is a circuit configuration diagram of the correlation processing unit, the correlation peak detection unit, and the frame synchronization signal detection unit in the frame synchronization state detection circuit illustrated in FIG.

Explanation of symbols

1. Digital terrestrial broadcasting system (ISDB-T system)
10: Transmitter
11: Data generation unit, 12 ... TMCC signal generation unit
13 ... TMCC signal insertion unit, 14 ... IFFT processing unit
15 ... Parallel / serial converter, 16 ... wireless transmitter
17 ... Transmitting antenna 20 ... Receiving device 20/20
21 ... Receiving antenna, 22 ... Tuner
23 ... Serial / parallel converter, 24 ... FFT processor
25. Error correction processing unit,
26 ... Frame synchronization / TMCC signal decoding unit
50, 50A: Frame synchronization / TMCC signal decoding unit
51 ... TMCC signal extraction unit, 52 ... Differential decoding unit
53 ... TMCC signal bit determination unit,
54 ... TMCC signal decoder,
55 ... Symbol counter,
S55: Frame synchronization detection timing signal
56. Frame synchronization signal detector
561: First shift register
562 ... Comparator
563 ... Second shift register
S56: Frame synchronization detection signal
57. Correlation processing unit
571: First shift register
572 ... Correlation processing unit
573: Second shift register
58. Correlation peak detector
581... Sum total calculation unit
582 ... Maximum value detection unit
583: Frame synchronization position detector
S58 ... correlation peak detection signal
59 ... Channel previous TMCC signal decoding unit
60 ... channel previous TMCC information memory
61 ... 1st selector, 62 ... 2nd selector
65. Control processing section

Claims (8)

A frame synchronization state detection circuit for detecting a frame synchronization state using a signal decoded for each symbol,
The correlation between each bit of the signal decoded for each symbol decoded last time and a predetermined bit of the signal decoded for each symbol to be decoded this time is obtained, and the maximum correlation value is obtained among the obtained correlations. A frame synchronization state detection circuit comprising: a first frame synchronization state detection circuit that detects a frame synchronization state when a portion is detected. The signal decoded for each symbol includes a signal having a specific bit pattern indicating the synchronization state of the frame,
A second frame synchronization state detection circuit for detecting a frame synchronization state when the arrival of a signal of the specific bit pattern is detected;
Outputting the detection signal of the first frame synchronization state detection circuit or the one frame synchronization state detection circuit as a frame synchronization signal;
The frame synchronization state detection circuit according to claim 1. The first and / or second frame synchronization state detection circuit is applied to a receiver of a digital communication system that performs OFDM modulation / demodulation,
The signal decoded for each symbol is a TMCC (Transmission and Multiplexing Configuration Control) signal.
The frame synchronization state detection circuit according to claim 1 or 2. The first frame synchronization state detection circuit includes:
A register holding the previously decoded TMCC signal;
A shift register that sequentially shifts predetermined bits of the TMCC signal to be decoded this time;
A correlation processing circuit for obtaining a correlation between a TMCC signal of a predetermined bit held in the shift register and data in a corresponding bit range of the TMCC signal held in the register;
A frame synchronization detection circuit that calculates a sum of the obtained correlations and detects a portion of the TMCC signal from which the maximum sum of the calculated sums is obtained as a frame synchronization position;
The frame synchronization state detection circuit according to claim 3. The second frame synchronization state detection circuit includes:
A register that holds the signal of the specific bit pattern for synchronization arranged at a predetermined position;
Among the TMCC signals to be decoded this time, a shift register that sequentially shifts the same bits of the specific bit pattern for synchronization,
A frame synchronization detection circuit that outputs a signal that detects a frame synchronization position when the bit data held in the register matches the bit data input to the shift register;
The frame synchronization state detection circuit according to claim 3. An OFDM demodulator for OFDM-demodulating a signal obtained by OFDM-modulating a signal in which a TMCC signal is inserted into broadcast data;
Frame synchronization / TMCC signal decoding means for detecting the frame synchronization of the OFDM demodulated data and decoding the TMCC signal, and detecting the OFDM demodulated data by referring to the frame synchronization detected by the frame synchronization / TMCC signal decoding means, and the error And error correction processing decoding means for performing correction processing and decoding,
The frame synchronization / TMCC signal decoding means includes:
TMCC signal extracting means for extracting a TMCC signal from the OFDM demodulated signal;
Decoding means for decoding the extracted TMCC signal;
TMCC signal bit determining means for determining the bit of the decoded TMCC signal;
TMCC signal decoding means for decoding the result of the TMCC signal bit determining means;
Previous TMCC signal holding means for holding the previous TMCC signal;
TMCC signal decoding means for decoding the previous held TMCC signal, a predetermined one of the decoded TMCC signal signal and the TMCC signal to be decoded this time among the bits determined by the TMCC signal bit determining means Correlation processing means for obtaining a correlation with a bit of
For the correlation obtained by the correlation processing means, a first frame synchronization state detecting means for detecting a frame synchronization state when detecting a portion having a maximum correlation value;
Symbol counter means for counting symbols according to the symbol synchronization signal and stopping counting when a frame synchronization detection signal is input from the first frame synchronization state detection means;
TMCC signal decoding means for decoding the bit data of the TMCC signal determined by the TMCC signal bit determining means with reference to the count value of the symbol counter means,
Signal decoding device. The TMCC signal includes a signal having a specific bit pattern indicating a frame synchronization state,
A second frame synchronization state detecting means for detecting a frame synchronization state when the arrival of the signal of the specific bit pattern is detected;
Outputting the detection signal of the first frame synchronization state detection means or the detection signal of the one frame synchronization state detection means to the symbol counter means as a frame synchronization signal;
The signal decoding device according to claim 6. Means for outputting the previous TMCC signal held in the previous TMCC signal holding means as a decoding result of the TMCC signal decoding means before decoding one frame in the TMCC signal decoding means;
The signal decoding device according to claim 6 or 7.

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