JP3356329B2 - Receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order. Industrial application Conventional technology (FIG. 5) Problems to be solved by the invention (FIG. 5) Means for solving the problems (FIG. 1) Action (FIG. 1) Example (1) Configuration of the example (FIG. 1 to 4) (2) Effects of the embodiment (3) Other embodiments Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving apparatus, and can be applied to, for example, a digital cellular phone which encodes and transmits an audio signal.

[0003]

2. Description of the Related Art Conventionally, in a digital cellular phone which is one of radio telephones, one channel is simultaneously transmitted and received by a plurality of terminal devices by applying a time division multiplexing technique by encoding and transmitting a voice signal. It has been made usable.

That is, as shown in FIG. 5, a digital cellular 1 converts analog audio signals into audio data at a transmitting side 2 of a terminal device and converts the audio data into audio data. Generate Further, the transmitting side 2 performs block coding of the source data by a block coding circuit 4, and adds a parity code for error detection and correction at this time.

Further, the transmitting side 2 performs a convolutional encoding process on the output data of the block coding circuit 4 in a convolutional encoding circuit 5, and performs an interleaving process on the output data in an interleave circuit 6. Thus, the transmitting side 2 orthogonally modulates the output data of the interleave circuit 6 with the data modulation circuit 7, converts the output data into a transmission signal of a predetermined frequency, and transmits the transmission signal with the time slot allocated to the own station. A voice signal can be transmitted to a desired terminal device via the Internet.

[0006] On the other hand, the receiving side 10 of the terminal device receives the time slot allocated to the own station, thereby receiving the voice signal of the call target transmitted from the base station. Here, the receiving side 10 includes a data demodulation circuit 11
Then, the received signal is frequency-converted and subjected to quadrature detection, thereby demodulating the I data and Q data generated in the communication target, and outputting the I data and Q data to the data equalization circuit 12. Here, the data equalization circuit 12 forms an equalizer circuit, corrects the I data and Q data, removes the effects of fading and multipath, and outputs demodulated data. The deinterleave circuit 13 outputs the demodulated data. The output data of the data equalization circuit 12 is deinterleaved and output.

At this time, the data equalization circuit 12 outputs reliability data (that is, a confidence bit) representing the certainty of the output data based on the amplitude information and phase information of the I data and Q data. Convolutional decoding circuit 1
Numeral 4 is formed by, for example, a Viterbi decoding circuit, and convolutionally decodes the output data of the deinterleave circuit 13 and outputs it. At this time, the maximum likelihood judgment is made and the soft decoding is performed on the basis of the confidence bit to decode the data. Performs an error correction process.

On the other hand, a block decoding circuit 15 performs block decoding on the output data of the convolutional decoding circuit 14 and outputs the data. At this time, the output data has an error based on the parity code added to the output data. The error correction processing is performed and output, and the error correction processing result is output as error information. Thus, the terminal device demodulates the output data into audio data, and then decompresses the audio data to convert it into an analog signal, thereby demodulating the audio signal transmitted from the communication target. .

At this time, in the digital cellular, by adding an error correction code and then performing convolutional coding processing to transmit the voice data, the voice signal can be reliably transmitted even when the communication environment is deteriorated. In this way, a stable call can be secured.

[0010] In the terminal device, the voice decompression process is switched based on the error information, and the error information is transmitted to the base station to switch the transmission power.
The operation of the digital cellular as a whole is switched according to the characteristics of the transmission path, so that the audio signal can be reliably transmitted and received.

[0011]

However, this type of terminal apparatus has a feature that the reception environment changes greatly, and an error occurrence rate of received data changes greatly. On the other hand, in the error correction using this kind of parity code, when the error occurrence rate is small, the error correction can be surely performed, but when the error occurrence rate exceeds a certain value determined by the code length of the parity code or the like. If the number increases, erroneous correction occurs, and the quality of the received data deteriorates.

One way to solve this problem is to select a parity code so that errors can be corrected sufficiently even when the reception environment changes. In practice, however, the parity code is limited due to limitations on the data band. There is a feature that a parity code cannot be added.

The present invention has been made in view of the above points, and it is an object of the present invention to propose a receiving apparatus capable of effectively avoiding quality degradation of received data and correcting errors efficiently.

[0014]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, according to the present invention, after a code for error detection and correction is added and convolutional-coded, a signal transmitted through a predetermined transmission path is received. The receiving device 21 decodes the received signal as input data IQ.
In addition to correcting Q, a branch metric BM, which is a distance between the input data and the branch, is detected according to the characteristics of the transmission path, and a branch metric BM is accumulated for each transition path of the input data IQ, and each state is input to each state. A state metric PS, which is a distance between the data IQ, is generated, a transition path of the input data IQ is selected based on a comparison result of the state metric PS, and output data subjected to maximum likelihood determination is generated based on the selection result. A state metric PS for state transition based on a result of selecting a transition path of the data IQ.
An equalizer circuit 23 for generating an absolute value of a difference between the minimum value of the state metric PS and the reliability value CF representing the reliability of the quality of the transmission path, and an output data of the equalizer circuit 23. Circuit 25 for convolutional decoding of reliability data CF and decoding circuit 2
5 based on the likelihood data representing the likelihood of the output data, and based on the reliability data obtained by the processing of the equalizer circuit 23 and the certainty data obtained by the processing of the decoding circuit 25. Then, the error occurrence rate of the output data of the decoding circuit 25 that is sequentially input is estimated, and the error detection processing or the error correction processing of the output data of the decoding circuit 25 based on the error detection and correction code is performed according to the estimated result. Error detection and correction circuit 2
6, 27, 28 and 29 are provided.

[0015]

[0016]

[0017]

[0018]

A branch metric BM, which is the distance between the input data IQ and the branch, is detected in accordance with the characteristics of the transmission path, and a branch metric BM is generated by accumulating the branch metric BM for each transition path of the input data IQ. A transition path of the input data IQ is selected based on the selected path, an absolute value of the difference between the state metric PS of the state transition and the minimum value of the state metric PS is generated based on the result of the transition path selection, and the absolute value is transmitted to the transmission path. Is used as the reliability data CF indicating the reliability of the quality of the data, and the error occurrence rate of the output data is estimated based on the reliability data CF and the certainty data indicating the certainty of the decoded data obtained by the processing of the decoding circuit 25. By switching between error detection processing and error correction processing according to the estimation result, The greater the absolute value of the difference between the marks, the higher the reliability can be objectively determined by numerical values, so that the accuracy in estimating the error rate of output data can be further improved, and the reliability of the transmission path can be improved. It is possible to effectively avoid the quality degradation of decoded data and to perform error correction more efficiently as compared with the case where the error occurrence rate is determined only by using the error rate alone or the case where the error occurrence rate is determined only by the certainty of the decoded data.

[0019]

[0020]

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

(1) Configuration of the embodiment In FIG. 1 in which the same reference numerals are assigned to parts corresponding to those in FIG. 5, reference numeral 20 denotes a digital cellular as a whole, and a transmission signal transmitted from a base station is transmitted by a terminal device 21. Receive. Here, after receiving the transmission signal via the antenna, the terminal device 21 performs frequency conversion and quadrature detection, thereby demodulating the I signal synchronized with the reference phase of the received signal in the data demodulation circuit 11 and A Q signal having a phase different from that of the signal by 90 degrees is demodulated, and the I signal and the Q signal are converted into digital values by a built-in analog digital conversion circuit.

The data equalizing circuit 23 is formed of a digital signal processor for processing the I data and the Q data. The data equalizing circuit 23 corrects the distortion of the I data and the Q data by waveform equalization, thereby performing fading and multi-pass. Reduce the impact. Further, in this embodiment, the data equalization circuit 23 is formed of a Viterbi equalizer, and corrects data by applying a Viterbi algorithm. Further, the data equalization circuit 23 generates reliability data CF of the received data using an operation result obtained when applying the Viterbi algorithm, and outputs the reliability data CF together with the data.

Here, as shown in FIG.
3 inputs the IQ data to the branch metric operation circuit 31, where the branch metric BM is detected. Here, in the Viterbi algorithm, a possible bit combination of the input data is called a branch, and the distance between the actual input data and each branch is referred to as a branch metric B.
Call it M.

That is, the branch metric operation circuit 31
Detects the branch metric BM corresponding to each branch by detecting the distance between the input data and each branch, and detects the detected branch metric B
M is output to an ACS (add compare select) operation circuit 32.

The ACS operation circuit 32 accumulates this branch metric BM for each path and accumulates the state metric P
S is generated, and a path is selected based on the comparison result of the state metric PS. Here, in the Viterbi algorithm, each value of a bit sequence that can be selected at the time of encoding is defined as a state, and the distance between each state and input data is defined as a state metric PS.

Here, in the case of digital cellular, there are, for example, 32 states in all, and the ACS operation circuit 32 adds a branch metric BM corresponding to the state metric PS of each state, thereby obtaining each path. The branch metric BM is accumulated. Further AC
The S operation circuit 32 detects the minimum value of the state metric PS accumulated and generated for each path, and selects the path with the smallest state metric PS as the most likely path.

That is, as shown in FIG. 3 which shows a part of the 32 states, the current state (symbol PS)
When the state (represented by the symbol NS) following the state (represented by the symbol NS) has the value (00010), two states of the value (00100) and (00101) are considered as the current state PS.

At this time, a state metric PS (x) having a value of 20 is detected in the current state PS having a value of (00100), and a value 7 as a branch metric BM is correspondingly obtained.
If the branch metric BM (k) of
The CS operation circuit 32 sets a value 27 obtained by adding the state metric PS (x) and the branch metric BM (k) to the state metric PS of the path from the current state PS to the following state NS.

Similarly, a state metric PS (y) having a value of 24 is detected in the current state PS having a value of (00101), and the value 1 is set as a branch metric BM in response to this.
When the branch metric BM (k + 1) is detected, the ACS operation circuit 32 outputs the state metric PS
(Y) and the value 25 obtained by adding the branch metric BM (k + 1) to the state N following the current state PS.
The state metric PS of the path leading to S is set.

Further, the ACS operation circuit 32 obtains the comparison result of the state metrics PS of the values 27 and 25, whereby the path from the current state PS of the value (00101) to the succeeding state NS is the most probable path. Then, this path is selected, and the state metric PS having the value 25 is set as the state metric PS of the subsequent state NS.

That is, in this case, the ACS operation circuit 32 calculates

(Equation 1) And the state metric PS of the subsequent state NS is set.

The ACS operation circuit 32 detects the state metric PS for each of the 32 current states, and stores the detected state metric PS in the state metric memory 33. Further, the ACS operation circuit 32 detects the state metric PS for each of the following 32 states with reference to the state metric PS stored in the state metric memory 33, and stores the path selection result in the path memory 34.

At this time, the ACS operation circuit 32 calculates the case corresponding to the expression (1) as follows:

(Equation 2) As shown by, the absolute value of the difference between the state metrics PS to the corresponding state (that is, the difference between the state metrics of the state transition) is detected, and this absolute value is output as reliability data. Thus, in the reliability data CF, it can be determined that the higher the value is, the higher the reliability is. By the way, in the case shown in FIG.
become.

Thus, the data equalization circuit 23 stores the path selection result in the path memory 34 for each state and stores the corresponding reliability data CF in the path memory 34. Further, the data equalization circuit 23 includes a path memory 34
The maximum likelihood circuit 35 determines the maximum path on the basis of the path selection result stored in the. And outputs this IQ data together with the corresponding reliability data CF. In this way, the absolute value of the difference between the state metrics PS can be easily generated using the result of the arithmetic processing at the time of path selection in the Viterbi algorithm. Characteristic data can be generated, and the power consumption of the terminal device as a whole can be reduced accordingly.

Further, in this state metric PS, the probability of reaching each state is expressed by:
If the absolute value of the difference between the state metrics PS is used as the reliability data CF, the reliability of the output data can be correctly represented. In this embodiment, the data equalization circuit 23 determines the value of the reliability data CF to generate a confidence bit, and the convolution decoding circuit 2
5 is output.

By the way, in the reliability data CF representing the certainty of each output data, it can be determined that the larger the value is, the more likely it is to be, and the smaller the bit error is. Thus, in this embodiment, the terminal device 21 estimates the error occurrence rate based on the reliability data and switches the error detection and correction processing.

On the other hand, the synchronizing word detecting circuit 29 detects a synchronizing signal from the output data of the data equalizing circuit 23 and outputs the result of the synchronizing signal detection. That is, in this type of digital cellular, after performing interleaving processing in a predetermined data unit, the source data 3 is transmitted with a predetermined synchronization signal interposed therebetween, thereby demodulating the source data with reference to the synchronization signal. It is made to be able to do.

The synchronizing word detecting circuit 29 generates a reference pattern in which data is continuous in the same bit array as the synchronizing signal, and calculates a correlation value between the reference pattern and the output data sequentially output from the data equalizing circuit 23. Is detected so that the timing of the synchronization signal is detected by detecting the rise of the correlation value, and the synchronization signal is removed from the subsequent data to be processed by the deinterleave circuit 24. . In the terminal device 21, the timing of decoding the received data is corrected based on the result of the detection of the synchronization signal, whereby the data is decoded at the timing synchronized with the base station.

Incidentally, in this correlation value detection result,
When the value is large, it can be determined that the bit error is small if only the synchronization signal is used. Further, in the synchronization signal, the entire error occurrence rate can be estimated based on the correlation value by being inserted into the source data 3 at a predetermined cycle. Thereby, the terminal device 21
Estimates the overall error occurrence rate based on the correlation value in addition to the reliability data, and switches the error detection and correction processing based on the estimation result.

The deinterleave circuit 24 fetches the output data of the data equalization circuit 23 in units of 4 bursts and performs a deinterleave process. The convolution decoding circuit 25 convolutionally decodes the output data of the deinterleave circuit 24. At this time, the decoding circuit 25 converts this data having a continuous logic "1" or "0" into multi-valued data based on the confidence bit.

That is, when the likelihood of this data is small, the convolution decoding circuit 25 converts the data of logic "1" or logic "0" into, for example, logic "0.8" or logic "0.
2 ". On the contrary, if the likelihood of the data is large, the data of logic" 1 "or logic" 0 "is held at the same logic level and converted to the corresponding multi-valued data. Further, the decoding circuit 25 sets the data thus converted into multi-valued data as input data, generates the original source data by applying the above-mentioned Viterbi algorithm, and thereby applies the soft decision method to the source data. Decrypt the data.

At this time, the decoding circuit 25 generates reliability data in the same manner as the data equalization circuit 23 described above. That is, in the reliability data, the probability of error occurrence can be estimated based on the reliability data by representing the likelihood of each decoded data decoded by applying the Viterbi algorithm.

Thus, in this embodiment, the block decoding circuit 26 includes the reliability data CF output from the data equalization circuit 23, the correlation value detection result output from the synchronizing word detection circuit 29, and the convolution decoding circuit 25. The operation is switched based on the reliability data output from the. That is, in the terminal device 21, the error rate state estimation circuit 27 outputs the reliability data CF output from the data equalization circuit 23, the correlation value detection result output from the synchronizing word detection circuit 29, and the output from the convolution decoding circuit 25. The reliability data is accumulated for a predetermined period to obtain an average value, and based on a comparison result between the average value and a predetermined reference value, it is determined whether or not the error occurrence rate exceeds a predetermined reference value.

The error detection / correction switching circuit 28 switches the operation of the block decoding circuit 26 based on the judgment result of the error rate state estimation circuit 27, whereby the terminal device 10 judges that the error occurrence rate is high. In such a case, the error correction processing using the parity code is stopped and only the error detection processing is executed. That is, for example, in a shortened cyclic code in which a 3-bit parity code is added to 50-bit data, a maximum of 2 bit errors can be generated.
In contrast to the case where a bit can be detected, when an error is corrected, the error correction capability is one bit.

Thus, in this case, the error occurrence rate is 1/50
If the error rate is equal to or less than 1/50, the error may be erroneously corrected. In this case, it is possible to effectively avoid the quality deterioration of the output data by performing the error detection processing. On the other hand, when the error occurrence rate is low, error correction can be performed by effectively using the error correction capability of the parity code, and thereby quality degradation of output data can be effectively avoided. Based on this correction principle, the error detection / correction switching circuit 28 switches the operation of the block decoding circuit 26, thereby effectively avoiding deterioration of the quality of the decoded data and efficiently performing error correction processing.

Since it is conceivable that a bit error may occur between consecutive data, the error rate state estimating circuit 27 provides the error occurrence rate with a predetermined margin with a certain margin as compared with the above-described example. It is determined whether or not the value has exceeded the value, so that even if a bit error occurs between consecutive data, the terminal device 21 can effectively avoid erroneous correction and effectively reduce the quality deterioration of decoded data. It has been made so that it can be avoided.

Thus, the terminal device 21 executes the processing procedure shown in FIG. 4 to sequentially process the received data, so that the terminal device 21 can receive the voice signal of the call target transmitted via the base station. Has been made. That is, in the terminal device 21, the process proceeds from the step SP1 to the step SP2, the data is demodulated by the data demodulation circuit 11, the data is equalized and demodulated by the data equalization circuit 23 in the subsequent step SP3, and the deinterleave circuit is performed in the subsequent step SP4 At 24, deinterleave processing is performed.

Further, the terminal device 21 convolutionally decodes the output data of the deinterleave circuit 24 in the subsequent step SP5 by the convolution decoding circuit 25, and in the subsequent step SP6, performs block decoding by the block decoding circuit 26. At the time of this block decoding, the terminal device 21 outputs the reliability data CF generated by the data equalization circuit, the correlation value detection result detected by the synchronization word detection circuit 29, and the reliability data generated by the convolution decoding circuit 25. Based on the data, the error occurrence rate of the received data is estimated, and based on the estimation result, error correction processing and error detection processing are switched to effectively avoid quality degradation of decoded data.
In step SP7, the decoded data is output to the following audio data processing circuit.

(2) Effects of the Embodiment According to the above configuration, the reliability data detected by the data equalization circuit and the reliability data detected by the convolution decoding circuit, and the synchronization word detection circuit 2
The error occurrence rate of the input data is estimated based on the correlation value detected in step 9, and the error correction processing and the error detection processing are switched based on the estimation result. An error detection process can be performed, thereby effectively avoiding erroneous correction of the decoded data, and when the error occurrence rate is low, the parity code can be effectively used to correct the error, thereby improving the quality of the decoded data. Deterioration can be effectively avoided and error correction can be performed efficiently.

(3) Other Embodiments In the above-described embodiment, a case has been described in which the data equalization circuit detects difference data from state metric obtained by applying the Viterbi algorithm to generate reliability data. However, the present invention is not limited to this, and the reliability data may be generated based on the branch metric, and further, the reliability data may be generated based on the phase information and the amplitude information.

Further, in the above-described embodiment, the case where reliability data is generated in the convolution decoding circuit in the same manner as in the data equalization circuit has been described. However, the present invention is not limited to this, and the state metric is output as it is. In this case, various methods of generating reliability data can be widely applied, and convolutional decoding circuits themselves and decoding circuits other than Viterbi decoding circuits can be widely applied.

Further, in the above-described embodiment, the case where the error occurrence rate is estimated based on the processing results of the data equalization circuit, the convolution decoding circuit, and the synchronizing word detection circuit has been described. However, the present invention is not limited to this. Instead, the error occurrence rate may be estimated based on any one of the processing results as needed.

Further, in the above-described embodiment, the case where the present invention is applied to a digital cellular terminal apparatus has been described. However, the present invention is not limited to this, and is widely applied to a receiving apparatus which receives convolutionally encoded data. Can be applied.

[0055]

As described above, according to the present invention, the branch metric which is the distance between the input data and the branch is detected according to the characteristics of the transmission path, and the branch metric is accumulated for each transition path of the input data. A transition path of input data is selected based on the generated state metric, and an absolute value of a difference between the state metric between the state transitions and the minimum value of the state metric is generated based on the result of the transition path selection. The value is used as reliability data indicating the reliability of the quality of the transmission path, and the error occurrence rate of output data is estimated based on the reliability data and the certainty data indicating the certainty of the decoded data obtained by the processing of the decoding circuit. By switching between the error detection processing and the error correction processing according to the estimation result, the state metric between the state transitions is changed. The higher the absolute value of the difference between the state metric and the minimum value of the state metric, the higher the reliability can be objectively determined as a numerical value, so that the accuracy in estimating the error rate of output data can be further improved, Compared to the case where the error occurrence rate is determined only based on the reliability of the transmission path or the case where the error occurrence rate is determined only based on the reliability of the decoded data, the quality degradation of the decoded data can be effectively avoided and the error correction can be performed efficiently. A receiving device can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating digital cellular according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a data equalization circuit.

FIG. 3 is a schematic diagram for explaining the operation.

FIG. 4 is a flowchart for explaining the entire data processing.

FIG. 5 is a block diagram showing a conventional digital cellular.

[Explanation of symbols]

21 terminal device, 10 data demodulation circuit, 12, 2
3 Data equalizing circuit 13, 24 Deinterleaving circuit 15, 26 Block coding circuit 2,
5 convolution decoding circuit 27 error rate state estimation circuit 28 error detection / correction switching circuit 29 synchronization word detection circuit 31 branch metric calculation circuit
32 ... ACS operation circuit, 33 ... State metric memory, 34 ... Path memory, 35 ... Maximum likelihood determination circuit.

Continuation of the front page (56) References JP-A-2-53330 (JP, A) JP-A-58-218254 (JP, A) JP-A-64-44644 (JP, A) JP-A-3-284021 (JP, A) JP-A-58-206252 (JP, A) JP-A-1-198131 (JP, A) JP-A-60-183840 (JP, A) JP-A-4-261238 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 1/00 H03M 13/00

Claims (1)

(57) [Claims] (1)Convolutional code with error detection and correction code added
After being encoded, the signal transmitted through a predetermined transmission path is
Receive and decode the received signal as input data
Receiving device, While correcting the above input data, Between the input data and the branch according to the characteristics of the transmission path
Branch metric, which is the distance of
The above branch metrics are accumulated for each data transition path.
State method, which is the distance between each state and the above input data
Generate a trick and compare the above state metrics
The transition path of the input data based on the
Generate output data with maximum likelihood determination based on the selection result, Based on the transition path selection result of the input data,
State between transition state metrics
Generates the absolute value of the difference from the minimum value of
Output as reliability data indicating the reliability of transmission line quality
Do An equalizer circuit, and decoding for convolutionally decoding output data of the equalizer circuit.
Circuit andConfirmation of the reliability data and the output data of the decoding circuit
Output data based on the likelihood data
Data error rate, The reliability data obtained by the processing of the equalizer circuit
Data obtained from the data and the processing of the decoding circuit
Of the decoding circuit sequentially input based on the
Estimate the error rate of output data and the result of the estimation
The decoding time based on the error detection and correction code
Performs error detection or error correction on the output data of the path
 Receiving apparatus comprising an error detection and correction circuit
Place.