JP2005064741A - Apparatus and method of reproducing transmission data - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the capacity of a buffer to be used for conversion while preventing overflow or underflow of the buffer in converting decoded data after performing OFDM modulation and transmission path decoding into a data stream synchronized with the clock of a stabilized frequency. <P>SOLUTION: An OFDM receiving device is provided with a TS reproducing circuit 17 for outputting a smoothed transport stream (TS). The TS reproducing circuit 17 is provided with a buffer 17, a writing address counter 22 for writing a packet outputted from a transmission path decoding circuit into the buffer 17, a reading address counter 23 for reading the packet from the buffer 17 to output the smoothed TS, and a determining circuit 30 for synchronizing the multiplexed frame of the TS with an OFDM frame delayed by a transmission path decoding time. Upon detecting synchronization deviation between the multiplexed frame and the delayed OFDM frame, the determining circuit 30 resets each of the counters 22, 23. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is applied to, for example, a receiver for digital terrestrial broadcasting, demodulates a bit sequence from an orthogonal frequency division multiplexing (OFDM) signal, and decodes the demodulated bit string, for example, as a data stream by decoding a transmission path such as error correction. The present invention relates to an apparatus and method for reproducing transmission data.

  As a method for modulating digital data, a modulation method called orthogonal frequency division multiplexing (hereinafter referred to as OFDM method; OFDM: Orthogonal Frequency Division Multiplexing) is known.

  With the OFDM modulation method, a number of orthogonal subcarriers (subcarriers) are provided in the transmission band, and data is allocated to the amplitude and phase of each subcarrier by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation), This is a digital modulation method. Since the OFDM scheme divides the transmission band by a large number of subcarriers, the band per subcarrier wave becomes narrow and the modulation speed becomes slow, but the total transmission speed is the same as the conventional modulation system. doing. In addition, in the OFDM scheme, since a number of subcarriers are transmitted in parallel, the symbol rate is slow, the time length of the multipath relative to the time length of the symbol can be shortened, and the multipath interference is not easily received. It has the characteristics. In addition, since the OFDM scheme allocates data to a plurality of subcarriers, an IFFT (Inverse Fast Fourier Transform) arithmetic circuit that performs inverse Fourier transform during modulation, and an FFT (Fast Fourier Transform) that performs Fourier transform during demodulation. ) It has a feature that a transmission / reception circuit can be configured by using an arithmetic circuit.

The OFDM system is often applied to terrestrial digital broadcasting that is strongly affected by multipath interference. The digital terrestrial broadcasting employing the OFDM method, for example, DVB-T (Digital Video Broadcasting -Terrestrial) and _{ISDB-T SB (Integrated Services Digital} Broadcasting -Terrestrial Sound Broadcasting) has standards such (Non-Patent Document 1, Non (See Patent Document 2).

  Non-Patent Document 1 shows one form of an OFDM receiver. An OFDM receiver manufactured based on this non-patent document 1 will be described with reference to FIG.

  As shown in FIG. 14, the OFDM receiver 100 includes an antenna 101, a tuner 102, a bandpass filter (BPF) 103, an A / D conversion circuit 104, a DC cancellation circuit 105, a digital orthogonal demodulation circuit 106, FFT operation circuit 107, frame extraction circuit 108, synchronization circuit 109, carrier demodulation circuit 110, frequency deinterleave circuit 111, time deinterleave circuit 112, demapping circuit 113, and bit deinterleave circuit 114 Depuncture circuit 115, Viterbi circuit 116, byte deinterleave circuit 117, spread signal removal circuit 118, transport stream generation circuit 119, RS decoding circuit 120, transmission control information decoding circuit 121, and CPU channel selection Circuit 122.

  A broadcast wave of a digital broadcast broadcast from a broadcast station is received by the antenna 101 of the OFDM receiver 100 and supplied to the tuner 102 as an RF signal.

  The RF signal received by the antenna 101 is frequency-converted into an IF signal by a tuner 102 including a multiplier 102 a and a local oscillator 102 b and is supplied to the BPF 103. The oscillation frequency of the reception carrier signal oscillated from the local oscillator 102 b is switched according to the channel selection signal supplied from the CPU channel selection circuit 122.

  The IF signal output from the tuner 102 is filtered by the BPF 103 and then digitized by the A / D conversion circuit 104. The digitized IF signal has its DC component removed by the DC cancellation circuit 105 and is supplied to the digital quadrature demodulation circuit 106.

  The digital orthogonal demodulation circuit 106 orthogonally demodulates a digitized IF signal using a carrier signal having a predetermined frequency (carrier frequency), and outputs a baseband OFDM signal. As a result of orthogonal demodulation, the baseband OFDM signal becomes a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). The baseband OFDM signal output from the digital quadrature demodulation circuit 106 is supplied to the FFT operation circuit 107 and the synchronization circuit 109.

  The FFT operation circuit 107 performs an FFT operation on the baseband OFDM signal, and extracts and outputs a signal that is orthogonally modulated on each subcarrier.

  The FFT operation circuit 107 extracts a signal for an effective symbol length from one OFDM symbol, and performs an FFT operation on the extracted signal. That is, the FFT operation circuit 107 removes a signal corresponding to the guard interval length from one OFDM symbol, and performs an FFT operation on the remaining signal. The range of the signal extracted for performing the FFT operation may be an arbitrary position of one OFDM symbol as long as the extracted signal points are continuous. That is, the start position of the extracted signal range is any position between the leading boundary position of the OFDM symbol and the end position of the guard interval.

  The signal modulated by each subcarrier extracted by the FFT operation circuit 107 is a complex signal composed of a real axis component (I channel signal) and an imaginary axis component (Q channel signal). The signal extracted by the FFT operation circuit 107 is supplied to the frame extraction circuit 108, the synchronization circuit 109, and the carrier demodulation circuit 110.

  The frame extraction circuit 108 extracts the boundary of the OFDM transmission frame based on the signal demodulated by the FFT operation circuit 107, and controls transmission of pilot signals such as CP and SP, TMCC, etc. included in the OFDM transmission frame Information is demodulated and supplied to the synchronization circuit 109 and the transmission control information decoding circuit 121.

  The synchronization circuit 109 includes a baseband OFDM signal, a signal modulated on each subcarrier after being demodulated by the FFT operation circuit 107, a pilot signal such as CP and SP detected by the frame extraction circuit 108, and a CPU An OFDM symbol boundary is calculated using a channel selection signal supplied from the channel selection circuit 122, and calculation start timing of FFT calculation is set for the FFT circuit 107.

The carrier demodulation circuit 110 is supplied with a demodulated signal from each subcarrier output from the FFT operation circuit 107, and performs carrier demodulation on the signal. For example, when demodulating an OFDM signal conforming to the ISDB- _TSB standard, the carrier demodulation circuit 110 performs, for example, DQPSK differential demodulation or QPSK, 16QAM, and 64QAM synchronous demodulation.

  The carrier demodulated signal is deinterleaved in the frequency direction by the frequency deinterleave circuit 111, and then deinterleaved in the time direction by the time deinterleave circuit 112, and then supplied to the demapping circuit 113. .

The demapping circuit 113 performs data reassignment processing (demapping processing) on the carrier demodulated signal (complex signal) to restore the transmission data sequence. For example, in the case of demodulating an ISDB- _TSB standard OFDM signal, the demapping circuit 113 performs demapping processing corresponding to QPSK, 16QAM, or 64QAM.

  The transmission data series output from the demapping circuit 113 passes through a bit deinterleave circuit 114, a depuncture circuit 115, a Viterbi circuit 116, a byte deinterleave circuit 117, and a spread signal removal circuit 118, thereby allowing error dispersion of multilevel symbols. Deinterleaving processing corresponding to bit interleaving, depuncturing processing corresponding to puncturing processing for reducing transmission bits, Viterbi decoding processing for decoding convolutionally encoded bit strings, deinterleaving in byte units The energy despreading process corresponding to the process and the energy diffusion process is performed and input to the transport stream reproduction circuit 119.

  The transport stream reproduction circuit 119 inserts data defined by each broadcasting system, such as a null packet, at a predetermined position in the stream. Further, the transport stream reproduction circuit 119 performs a so-called smoothing process in which the bit interval of the intermittently supplied stream is smoothed to obtain a temporally continuous stream. The transmission data sequence subjected to the smoothing process is supplied to the RS decoding circuit 120.

  The RS decoding circuit 120 performs Reed-Solomon decoding processing on the input transmission data sequence and outputs it as a transport stream defined by MPEG-2 Systems.

  The transmission control information decoding circuit 121 decodes transmission control information such as TMCC modulated at a predetermined position of the OFDM transmission frame. The decoded transmission control information is supplied to a carrier demodulation circuit 110, a time deinterleaving circuit 112, a demapping circuit 113, a bit deinterleaving circuit 114, and a transport stream reproduction circuit 119, and is used for demodulation and reproduction of each circuit. Used for control.

"Receiving equipment standard for terrestrial digital audio broadcasting (preferred specification) ARIB STD-B30 version 1.1", Radio Industry, established on May 31, 2001, revised on March 28, 2002 1.1 "Transmission system for digital terrestrial audio broadcasting ARIB STD-B29 version 1.1", Radio Industry, formulated on May 31, 2001, revised on March 28, 2002 1.1

  Here, in the transport stream reproduction circuit 119 of the OFDM receiver 100, a smoothing buffer having a very large capacity is incorporated, and data at an average clock rate is obtained by averaging the data stream supplied in a burst manner from the spread signal removal circuit. A so-called smoothing process for converting to a stream is performed. Further, the transport stream reproduction circuit 119 generates a transport stream by appropriately inserting a null packet that is not transmitted by the OFDM signal into the data stream (see Non-Patent Document 2 P14).

  By the way, it is desirable to reduce the capacity of the smoothing buffer as much as possible within the condition that overflow and underflow do not occur.

  However, in an apparatus that performs smoothing and considers the insertion of a null packet as in the OFDM receiving apparatus 100, the processing timing of the null packet is very complicated, and therefore, there is a condition that overflow and underflow do not occur. It is very difficult to reduce the capacity of the smoothing buffer while ensuring it.

  The present invention solves the above-described problems, and when converting decoded data after OFDM demodulation and transmission path decoding into a data stream synchronized with a clock having a stabilized frequency, It is an object of the present invention to provide a transmission data reproducing apparatus and method in which a buffer used at the time of conversion does not overflow and underflow and the capacity of the buffer is reduced.

  The transmission data reproducing apparatus according to the present invention is configured such that an effective symbol generated by time-division-dividing a bit sequence and orthogonally modulating a plurality of subcarriers and a signal waveform at the end of the effective symbol are cyclically connected to the other. OFDM demodulating means for demodulating the bit sequence from an orthogonal frequency division multiplex (OFDM) signal having a transmission symbol composed of a guard interval generated by copying at the end as a transmission unit; A transmission path decoding means that performs decoding processing corresponding to the standard of the transmission path on which the OFDM signal is transmitted on the demodulated bit sequence and outputs decoded data, and a transmission composed of a predetermined number of transmission symbols OFDM frame detection that detects the start timing (OFDM frame start timing) of the unit OFDM frame A delay means for delaying the OFDM frame start timing by a time determined based on a processing delay time of the transmission path decoding means, and the decoded data output from the transmission path decoding means are stored, and the frequency is stabilized. A stream generation unit that generates a data stream synchronized with the output clock by reading out the decoded data stored in synchronization with the output clock (output clock), and the stream generation unit reads and writes data A buffer that can be performed simultaneously; a writing unit that writes the decoded data output from the transmission path decoding means to the buffer; and the data is read from the buffer and the read data is synchronized with the output clock. A reading unit that outputs the data stream; Having an output start timing of the multiplexed frame from the time the number of packets corresponding to the length of the arm is a transmission unit of composed data stream, and a synchronization control unit to synchronize the OFDM frame start timing output from said delay means.

  In the transmission data reproducing apparatus according to the present invention, when the data stream is generated, the output start timing of the multiplexed frame, which is a data stream transmission unit composed of the number of packets corresponding to the time length of the OFDM frame, is delayed. The OFDM frame start timing is synchronized.

  In the transmission data recovery method according to the present invention, an effective symbol generated by time-division-dividing a bit sequence and orthogonally modulating a plurality of subcarriers and a signal waveform at the end of the effective symbol are cyclically connected to the other. The bit sequence is demodulated from an orthogonal frequency division multiplex (OFDM) signal whose transmission unit is a transmission symbol composed of a guard interval generated by copying at the end, and the demodulated bit sequence is Then, decoding processing corresponding to the standard of the transmission path through which the OFDM signal is transmitted is generated, decoded data is generated, and OFDM frame start timing (OFDM frame start timing) which is a transmission unit composed of a predetermined number of transmission symbols And detecting the OFDM frame start timing based on the processing delay time of the transmission path decoding process. The output clock is delayed by a predetermined time, the decoded data generated by the transmission path decoding process is stored, and the decoded data stored in synchronization with the frequency-stabilized clock (output clock) is read out. In addition, when generating the data stream, an output start timing of a multiplex frame, which is a data stream transmission unit composed of the number of packets corresponding to the time length of the OFDM frame, Synchronize with the delayed OFDM frame start timing.

  In the transmission data reproduction method according to the present invention, when generating a data stream, the output start timing of a multiplexed frame, which is a transmission unit of a data stream composed of the number of packets corresponding to the time length of the OFDM frame, and delayed OFDM The frame start timing is synchronized.

  In the transmission data reproduction apparatus and method according to the present invention, when generating a data stream, the output start timing of a multiplex frame that is a transmission unit of a data stream composed of the number of packets corresponding to the time length of the OFDM frame, The OFDM frame start timing is synchronized.

  Thus, according to the present invention, when the decoded data after OFDM demodulation and transmission path decoding is converted into a data stream synchronized with a clock having a stabilized frequency, the buffer used during conversion overflows and underflows. And the capacity of the buffer can be reduced.

  As the best mode for carrying out the present invention, an orthogonal frequency division multiplex receiving apparatus (OFDM receiving apparatus) to which the present invention is applied will be described.

The OFDM receiver according to the best mode for carrying out the present invention is a receiver compatible with the ISDB- _TSB standard. That is, the OFDM receiver 10 is a device that receives a transmitted OFDM signal modulated into a radio wave, demodulates and decodes the received OFDM signal, and outputs a transport stream (TS).

Before describing the OFDM signal OFDM receiving apparatus, first, the signal configuration of the OFDM signal and the transport stream will be briefly described.

  As shown in FIG. 1, an OFDM signal symbol (hereinafter referred to as an OFDM symbol) is obtained by copying an effective symbol that is a signal period during which IFFT is performed at the time of transmission and a waveform of a part of the latter half of the effective symbol. It consists of a guard interval. The guard interval is provided in the first half of the OFDM symbol. Therefore, the start position of the range of the signal extracted at the time of FFT calculation is between the leading boundary position of the OFDM symbol (position A in FIG. 1) and the end position of the guard interval (position B in FIG. 1). Either position. By providing such a guard interval, intersymbol interference due to multipath is allowed and multipath tolerance is improved.

In the ISDB- _TSB standard, there are three modes (mode 1, mode 2, and mode 3) in which the time length of the effective symbol is different. The time length of the effective symbol in mode 1 is 252 μsec, the time length of the effective symbol in mode 2 is 504 μsec, and the time length of the effective symbol in mode 3 is 1.008 msec. The time length of the guard interval is any one of 1/4, 1/8, 1/16, and 1/32 of the time length of the effective symbol in each mode. In addition, the number of subcarriers of the ISDB- _TSB standard one-segment method (a method of transmitting only a narrow band portion in the case of hierarchical transmission) is 108 in mode 1, 192 in mode 2, and 384 in mode 3. It is a book. The three-segment method (a method for performing broadband transmission in the case of hierarchical transmission) is three times the one-segment method.

In the OFDM signal, differential modulation or synchronous modulation is performed on each subcarrier. For example, in the case of an OFDM signal conforming to the ISDB-T _SB standard, DQPSK differential modulation or QPSK, 16QAM, and 64QAM synchronous modulation is performed. In the OFDM signal, convolutional encoding using puncturing is generally performed on a bit sequence to be modulated. For example, in the case of ISDB- _TSB standard, 1/2, 2/3, 3/4, 5/6, or 7/8 is adopted as the coding rate of convolutional coding.

  The OFDM signal constitutes a transmission unit called an OFDM frame by a plurality of continuous OFDM symbols. In the OFDM signal, various transmission parameters necessary for demodulation and decoding, which are called OFDM signal transmission control information, are transmitted for each OFDM frame, and the transmission parameters are changed for each OFDM frame.

For example, in the ISDB-T _SB standard, one OFDM frame is defined by 204 OFDM symbols. In the ISDB- _TSB standard, a TMCC (Transmission and Multiplexing Configuration Control) signal is DBPSK modulated at a predetermined subcarrier position of an OFDM symbol. The TMCC signal is one unit (204 bits) of information in one OFDM frame, and includes a synchronization word, transmission parameters (segment format (1-segment system or 3-segment system), mode identification (mode 1, mode 2 or mode 3). Identification), carrier modulation scheme, time direction interleave pattern, convolutional code coding rate), and the like.

The transport stream output from the OFDM receiver is a 204-byte packet (TSP) sequence. TSP is data obtained by adding 16-byte redundant data to a 188-byte MPEG2 Systems TS packet. In addition, the transport stream output from the OFDM receiver has a basic transmission unit of a multiplex frame composed of a plurality of TSPs. In the case of the ISDB-TS _SB standard, when the transport stream is transmitted with an ideal transmission clock (1.0158 MHz × 2 for the 1-segment format, 2.0317 MHz × 4 for the 3-segment format), the time of multiple frames The length matches the time length of the OFDM frame. Further, the total number of TSPs included in one multiplex frame differs according to the segment format of the OFDM signal, the mode distinction, and the guard interval ratio. Table 1 below shows the number of TSPs (total number of valid packets and null packets) included in one multiplexed frame in the case of the ISDB- _TSB standard.

The TSP included in the multiplexed frame is a valid packet (TSP _A ) transmitted in the A layer of the OFDM signal, a valid packet (TSP _B ) transmitted in the B layer, or a null packet (TSP _null) not transmitted in the OFDM signal. ). A null packet is a packet with no information in the packet.

The effective number of packets excluding null packets included in the multiplex frame differs depending on the mode distinction, the carrier modulation scheme, and the convolutional coding rate. Tables 2 and 3 below show the number of valid packets included in one multiplexed frame in the case of the ISDB- _TSB standard.

  Furthermore, the TSP arrangement in the multiplex frame differs for each transmission parameter (segment format, mode distinction, combination of guard interval ratio, carrier modulation scheme, convolution coding rate) shown in Tables 1 to 3 above. However, if the transmission parameters are determined, the TSP arrangement is uniquely determined based on the model receiver shown in the conventional example (see Non-Patent Document 2).

Next, an OFDM receiving apparatus according to the best mode for carrying out the present invention will be described. FIG. 2 shows a block diagram of the OFMD receiving apparatus 10.

  As shown in FIG. 2, the OFDM receiver 10 includes a tuner 11, an OFDM demodulation circuit 12, a frame detection circuit 13, a transmission path decoding circuit 14, a delay circuit 15, a transmission parameter decoding circuit 16, and a transport. And a stream reproduction (TS reproduction) circuit 17.

  The OFDM receiver 10 operates based on two basic clocks, an internal clock (WCK) and an output clock (RCK). The internal clock (WCK) is used as a clock for OFDM demodulation processing and error correction processing. The output clock (RCK) is a clock for smoothing and transmitting the transport stream to be output. Transfer from the internal clock (WCK) to the output clock (RCK) is performed by the TS reproduction circuit 17. In addition, the frequency of the internal clock (WCK) does not vary and is fixed, but the output clock (RCK) varies appropriately to an optimal value according to the reception state, demodulation and decoding state, and the like. However, the output clock (RCK) is controlled by, for example, a clock control circuit (not shown) so that the pre-buffer of the subsequent device that receives the transport stream does not fail, so that the output clock (RCK) is maintained at a stable and average frequency. Has been.

  A broadcast wave of a digital broadcast broadcast from a broadcast station is received by the antenna of the OFDM receiver 10 and supplied to the tuner 11 as an RF signal.

  The tuner 11 performs frequency conversion and band pass filtering on the RF signal received by the antenna to generate an IF signal. The IF signal output from the tuner 11 is supplied to the OFDM demodulation circuit 12.

  The OFDM demodulation circuit 12 performs orthogonal demodulation on the input IF signal to generate a baseband OFDM signal, performs FFT operation while performing various synchronization processes on the baseband OFDM signal, Demodulate the signal modulated on the carrier. Subsequently, the OFDM demodulation circuit 12 performs carrier demodulation (DQPSK differential demodulation or QPSK, 16QAM, 64QAM synchronous demodulation), frequency deinterleaving on the signal modulated on each subcarrier extracted by the FFT calculation process. Processing, time deinterleaving processing, and data reallocation processing (demapping processing) are performed to demodulate bit sequence data. The data (bit sequence) output from the OFDM demodulation circuit 12 is supplied to the data transmission path decoding circuit 14. Of the signals after the FFT calculation, a signal modulated to a predetermined subcarrier (TMCC carrier) is supplied to the OFDM frame detection circuit 13.

  The OFDM frame detection circuit 13 performs DBPSK demodulation on the signal modulated on the TMCC carrier to generate a TMCC signal. The OFDM frame detection circuit 13 detects a synchronization word from the TMCC signal, and detects the start timing of the OFDM frame based on the detected timing of the synchronization word. The OFDM frame detection circuit 13 outputs a flag (OFDM frame start flag) indicating the start timing of the OFDM frame. The OFDM frame start flag is supplied to the OFDM demodulation circuit 12, the transmission path decoding circuit 14, and the delay circuit 15. The OFDM demodulation circuit 12 controls synchronization processing, equalization processing timing, and the like based on the OFDM frame start flag. The OFDM frame detection circuit 13 detects a synchronization word, extracts a 204-bit TMCC signal including the synchronization word, and supplies the extracted TMCC signal to the transmission parameter decoding circuit 16.

The transmission path decoding circuit 14 receives data (bit string) after OFDM demodulation, and performs various decoding processes defined by the ISDB- _TSB standard on the data. Specifically, the transmission path decoding circuit 14 performs deinterleaving processing corresponding to bit interleaving for error dispersion of multilevel symbols, depuncturing processing corresponding to puncturing processing for reducing transmission bits, and a convolutional code. Viterbi decoding processing for decoding the converted bit string, deinterleaving processing in byte units, energy despreading processing corresponding to energy spreading processing, and finally 204 bytes (16 bytes out of 204 bytes are error correction) Error correction processing by Reed-Solomon decoding is performed for each packet of code).

  The transmission path decoding circuit 14 outputs the data for which Reed-Solomon decoding has been completed to the TS reproduction circuit 17 in TSP units (204-bit packet units). Data (packets) output from the transmission path decoding circuit 14 is transferred to the TS reproduction circuit 17 in a burst manner. The transmission path decoding circuit 14 also transfers to the TS reproduction circuit 17 an enable signal indicating whether or not the data (packet) to be transferred is valid and a packet start flag indicating the start timing of the packet to be transferred. Further, the transmission path decoding circuit 14 delays the OFDM frame start flag together with the processing of the data input simultaneously with the flag, and outputs it in synchronization with the output timing of the data input simultaneously with the flag. This flag is called an FEC frame start flag. The transmission path decoding circuit 14 also transfers the FEC frame start flag to the TS reproduction circuit 17.

  The delay circuit 15 delays the OFDM frame start flag output from the OFDM frame detection circuit 13 by a predetermined time. The flag delayed by the delay circuit 15 is hereinafter referred to as a multiple frame start flag. The delay amount of the OFDM frame start flag by the delay circuit 15 is a delay amount corresponding to the processing delay time of the transmission path decoding circuit 14 (for example, the average value of the processing time of the transmission path decoding circuit 14). Since the processing delay time by the transmission path decoding circuit 14 varies depending on the transmission parameter, the delay circuit 15 also changes the delay time when the transmission parameter is changed. The delay circuit 15 transfers the multiple frame start flag to the TS reproduction circuit 17.

  The transmission parameter decoding circuit 16 decodes the TMCC signal supplied from the OFDM frame detection circuit 13 to extract parameters such as segment format identification, carrier modulation scheme and convolutional code coding rate, and an OFDM demodulator To 12 and the mode interval and the guard interval ratio are estimated from the guard interval ratio estimation information, or the transmission mode is output by selecting the set mode and the guard interval ratio. . The transmission parameter decoding circuit 16 supplies these pieces of information to the OFDM demodulation circuit 12 and the transmission path decoding circuit 13, and performs various settings necessary for demodulation and decoding. The transmission parameter decoding circuit 16 supplies the transmission parameter to the TS reproduction circuit 17.

As described above, the TS reproduction circuit 17 performs so-called smoothing processing in which the bit interval of the intermittently supplied valid packet (TSP _A or TSP _B ) is smoothed to form a temporally continuous transport stream. , Null packet insertion processing for inserting a null packet (TSP _null ) that was not included in the OFDM signal into a predetermined position of the stream is performed. As a result, the TS reproduction circuit 17 can output the transport stream in which the null packet (TSP _null ) is inserted to the outside in synchronization with the output clock (RCK).

TS reproducing circuit will now be described in detail the internal structure of the TS reproduction circuit 17.

(Smoothing process)
As shown in FIG. 3, the TS reproduction circuit 17 includes a buffer memory 21 for storing data, a write address counter 22, and a read address counter 23.

  The buffer memory 21 is a 2-port type memory capable of writing and reading simultaneously. In the following description, it is assumed that the buffer memory is written and read in units of bytes.

  The data output from the transmission path decoding circuit 14 is input to the buffer memory 21. The buffer memory 21 writes the data input to the data write port WDT when the write enable port WEN is asserted (1). Data writing is performed in units of 1 byte. The data write address is specified by the write address counter 22 in units of 1 byte. Note that data is written to the buffer memory 21 in synchronization with the internal clock (WCK).

  Data is output to the buffer memory 21 from the data read port RDT to a selector 29 described later. Data is read from the data read port RDT. Data reading is performed in units of 1 byte. The data read address is designated by the read address counter 23 in units of 1 byte. Note that data is read from the buffer memory 21 in synchronization with the output clock (RCK).

  The write address counter 22 is a circuit that designates a write address for the buffer memory 21 in units of 1 byte. However, the write address counter 22 counts up the write address only when the write data enable signal (en) is valid (1). That is, the count-up is performed only when valid write data is transferred. The write address is counted up cyclically within the address range in the buffer memory 21. That is, when the write address is counted up and the address reaches the maximum value (that is, when the capacity of the buffer memory 21 becomes full), the address is returned to the minimum value by the next count up (that is, , Go back to the beginning and do overwriting). As a result, the buffer memory 21 generates the data for one packet input to the data write port WDT intermittently in units of 1 byte, and is generated from the write address counter 22 at a timing synchronized with the internal clock (WCK). Write to the address location.

  The read address counter 23 is a circuit that designates a read address in units of 1 byte with respect to the buffer memory 21. However, the read address counter 23 counts up the read address only when the packet identification flag (described later in detail) is valid (1) (that is, when valid data is transmitted). Further, the read address is counted up cyclically within the address range in the buffer memory 21. That is, when the read address is counted up and the address reaches the maximum value, the address is returned to the minimum value by the next count up.

  As described above, the TS reproduction circuit 17 writes the data output from the transmission path decoding circuit 14 to the buffer memory 21 in synchronization with the internal clock (WCK), temporarily accumulates it, and then outputs it to the output clock (RCK). Output synchronously. As a result, the TS reproduction circuit 17 can convert the clock rate of the data output from the transmission path decoding circuit 14 from the internal clock (WCK) to the output clock (RCK), and is further burst transferred. Packets can be smoothed.

(Packet multiplexing)
As shown in FIG. 3, the TS reproduction circuit 17 includes a byte counter 25, a packet counter 26, a table memory 27, a null packet generation circuit 28, and a selector 29.

The byte counter 25 is a counter that counts the amount of bytes of the TS output from the TS reproduction circuit 17 by counting the output clock (RCK). The count value N ₁ of the byte counter 25 takes a value from 0 to 203, and when it exceeds 203, it returns to 0. That is, the byte counter 25 is a circuit that cyclically counts the byte positions in one packet. If the count value N ₁ of the byte counter 25 is a cyclic one, so that the data for one packet from the TS reproduction circuit 17 (204 bytes) is sent. The byte counter 25 outputs the count value N ₁ and the carry flag (flag generated at the timing when N ₁ changes from 203 to 0) CO ₁ to the outside.

The packet counter 26 is a counter that counts the number of TS packets output from the TS reproduction circuit 17 by counting the carry flag CO ₁ of the byte counter 25. Count value _{N 2} of the packet counter 26 takes a value from 0 to (M-1), the flow returns to 0 when it exceeds (M-1). Here, M is the total number of TPS in one multiplexed frame (see Table 1). The value of M is set based on the transmission parameter supplied from the transmission parameter decoding circuit 16. That is, the packet counter 26 is a circuit that cyclically counts the packet position within one multiplexed frame. When the count value N ₂ of the packet counter 26 circulates once, so that the packet of one multiplex frame from the TS reproduction circuit 17 (M-number of packets) is sent. The packet counter 26 outputs the count value N ₂ and the carry flag (flag generated when N ₂ changes from (M−1) to 0) CO ₂ to the outside.

The table memory 27 stores an array information table 27-1 indicating a packet array indicating whether the TSP at each packet position in one multiplexed frame is a valid packet or a null packet. Specifically, as shown in FIG. 4, the array information table 27-1 is composed of addresses that increase from 0 to (M-1) every step and a packet identification flag represented by 1 or 0. Has been. The address indicates the position of the packet in the multiple frame. The packet identification flag is a flag for identifying whether the packet at the address is a valid packet or a null packet. Here, when the packet identification flag is 1, a valid flag is indicated, and when it is 0, a null packet is indicated. Table memory 27, the count value N ₂ outputted from the packet counter 26 is inputted as an address, it generates a packet identification flag corresponding to the count value N _2. That is, the count value N _2, since it indicates the packet position in the multiplex frame to be output, the packet identification flag, so that the either invalid packet or packets currently output is valid packet is shown.

  The TSP arrangement in the multiplex frame differs for each OFDM signal transmission parameter (combination of segment format, mode distinction, guard interval ratio, modulation scheme, and coding rate). A plurality of array information tables corresponding to packet arrays of combinations of respective transmission parameters are stored. In the table memory 27, one of the plurality of array information tables is selected as one array information table 27-1 based on the transmission parameter supplied from the transmission parameter decoding circuit 16.

  The null packet generation circuit 28 is a circuit that stores null packets.

  The selector 29 selects either the buffer memory 21 or the null packet generation circuit 28, reads one packet of data from the selected circuit in byte units, and synchronizes the read data with the output clock (RCK). The circuit that outputs to The selector 29 performs switching according to the packet identification flag generated from the table memory 27. When the valid packet is indicated in the packet identification flag (that is, when the packet identification flag is 1), the selector 29 selects the buffer memory 21 and reads the valid packet from the buffer memory 21 in units of bytes. Output to the outside. Further, when a null packet is indicated in the packet identification flag (that is, when the packet identification flag is 0), the selector 29 selects the null packet generation circuit 28 and enters the null packet generation circuit 28. The stored null packet is read for one packet (204 bytes) and output to the outside.

  The selector 29 reads data for one packet from an address on the buffer memory 21 specified by a read address counter 23 described later. The address of the read address counter 23 is incremented every time one valid packet is read, and moves to the read position of the next packet.

  As described above, the TS reproduction circuit 17 generates a TS by time-division multiplexing the valid packet and the null packet by the selector 29. Further, the TS reproduction circuit 17 refers to an array information table showing an array of packet identification (identification of valid packet or null packet) for a packet position in a multiplexed frame when multiplexing. Packet multiplexing is performed. Therefore, the TS reproducing circuit 17 can generate a TS that conforms to the standard without having the same configuration as that of the model receiver. Therefore, the OFDM receiver 10 can perform processing to generate a TS after the Viterbi decoding process or the Reed-Solomon decoding process, and the Viterbi decoding process or the Reed-Solomon decoding process for data having no meaning in information content such as a null packet. This makes it possible to reduce the power consumption and the processing speed.

(Judgment of synchronization status)
Further, as shown in FIG. 3, the TS reproduction circuit 17 includes an internal state determination circuit 30, a first reset circuit 31, and a second reset circuit 32.

The internal state determination circuit 30 receives the multiple frame start flag and the count values N ₁ and N _{2 of} the byte counter 25 and the packet counter 26.

  The multiframe start flag is a flag obtained by delaying the start flag of the OFDM frame of the OFDM signal by the processing delay time of the transmission path decoding circuit 14. For this reason, even if packets are input to the buffer memory 21 in bursts, it can be considered that the packets are input in synchronization with the multiple frame start flag on average. The internal state determination circuit 30 determines whether the time difference between the multiplex frame boundary of the actually output TS and the multiplex frame start flag is a time difference that does not overflow or underflow in consideration of the capacity of the buffer memory 21. Whether it is detected. Further, the internal state determination circuit 30 determines whether the buffer memory 21 is in a state of overflowing or underflowing or not overflowing or underflowing based on the detected time difference, and the buffer memory 21 If it is in a state of failure, the write address counter 22, the read address counter 23, the byte counter 25 and the packet counter 26 are reset once, and the boundary of the multiplex frame of the TS actually output is synchronized with the multiplex frame start flag. To perform the process.

The count value N ₁ and the count value N ₂ indicate the position in the multiplexed frame of the TS that is actually output because the multiplexing control of the valid packet and the null packet is performed based on this value. . Therefore, if the count value N ₁ and the count value N ₂ at the generation timing of the multi-frame start flag are detected, the values are regarded as a time difference between the multi-frame boundary of the TS that is actually output and the multi-frame start flag. Can do.

Therefore, the internal state determining circuit 30 detects the count value N ₁ and the count value N ₂ in the generation timing of the multiplex frame start flag, if within the range of the time difference predetermined amount based on these FIGS. 5 (A) As shown in FIG. 5, a state where synchronization is established (synchronization establishment state), and if not, a state where the above-described reset operation is once performed and synchronization is captured again (synchronization acquisition state) as shown in FIG. It is said.

  FIG. 6 shows a specific circuit configuration diagram of the internal state determination circuit 30.

  The internal state determination circuit 30 includes a first register circuit 41, a second register circuit 42, a time difference calculation circuit 43, and a comparator 44.

The first register circuit 41 and the second register circuit 42 receive an internal clock (WCK) as a clock signal and a multiple frame start flag as an enable signal. Then, the first register circuit 41 the count value N ₁ of the byte counter 25 is input, the second register circuit 42 the count value N ₂ of the packet counter 26 is input. Therefore, inside the first register circuit 41, the count value N ₁ of the byte counter 25 with the generation timing of multiplexed frame start flag is held in the interior of the second register circuit 42, the multi-frame start flag count value N ₂ of the packet counter 26 at the occurrence timing is maintained.

The time difference calculation circuit 43 multiplies the value (number of packets) of the count value N ₂ held in the second register circuit 42 by the number of bytes (204) of one packet, and uses the multiplied value as the first register circuit 41. It is added to the count value N ₁ held in, obtaining the time difference N. That is, N = (N ₂ × 204) + N ₁ is calculated. This byte N is a time difference between the boundary of the actually output TS multiple frame and the multiple frame start flag. The time difference calculation circuit 43 outputs the obtained time difference N to the comparator 44.

The comparator 44, the time difference N obtained by the time difference calculating circuit 43 compares determines whether the minimum value N maximum value N _MAX less the range of _MIN. As a result of the comparison determination, when the time difference N is in the range from the minimum value N _{MIN to the} maximum value N _MAX (when N _MIN ≦ N ≦ N _MAX ), the synchronization is established, and the time difference N is the minimum value N _MIN or more. When it is in the range of the maximum value N _MAX or less (when N <N _MIN or N _MAX <N), the synchronization acquisition state is set. Details of the minimum value N _{MIN and the} maximum value N _MAX will be described later.

  The first reset circuit 31 continues from the timing at which the synchronization determination result output from the internal state determination circuit 30 transitions to the synchronization capture state (from the synchronization established state to the synchronization capture state, or from the synchronization capture state The first reset signal is activated by one output clock (RCK) at the timing when the synchronization acquisition state is reached, and is deactivated at other times. Such a first reset signal is supplied to the byte counter 25, the packet counter 26, and the read address counter 23.

Byte counter 25, when the first reset signal becomes active, the internal count value N ₁ at the timing is reset to 0, and other counts up the count value N ₁ when the.

Packet counter 26, when the first reset signal becomes active, resets the internal count value N ₂ at that timing to a predetermined initial value, other counts up the count value N ₂ when the. The predetermined initial value is a value that _falls within a range of at least the minimum value N _{MIN and the} maximum value N _MAX . Therefore, if the next multi-frame start flag is generated and the multi-frame boundary of the TS actually output coincides with the multi-frame start timing, a transition is made to the synchronization establishment state.

  When the first reset signal becomes active, the read address counter 23 resets the internal address to the initial value (read initial value) at that timing, and counts up the internal address at other times. For this reason, the address is read and reset to the initial value at the timing of transition from the synchronization establishment state to the synchronization acquisition state, and the count-up is continued as long as the synchronization establishment state continues thereafter.

  The second reset circuit 32 continues from the timing at which the synchronization determination result output from the internal state determination circuit 30 transitions to the synchronization capture state (from the synchronization established state to the synchronization capture state, or from the synchronization capture state. When the synchronization acquisition state is detected, the second reset signal is activated by one internal clock (WCK) at the next FEC frame start timing. The reason why the second reset signal is activated at the FEC frame start timing is that a packet is input in a burst manner, so that the input timing is shifted. In addition, the second reset circuit 32 makes the second reset signal non-active at other times. Such a second reset signal is supplied to the write address counter 22.

  When the second reset signal becomes active, the write address counter 22 resets the internal address to an initial value (write initial value) at that timing, and counts up the internal address at other times. For this reason, the address is reset to the write initial value at the timing of transition from the synchronization establishment state to the synchronization acquisition state, and the count-up is continued as long as the subsequent synchronization establishment state continues.

  Note that the read initial value of the read address counter 23 is set to be a predetermined negative value when compared with the write initial value of the write address counter 22. That is, the count directions of the write address counter 22 and the read address counter 23 are the same, and when the reset is released at the same time (when the count up starts), the read address starts from a predetermined negative value. It is set to be. It is determined in consideration of the maximum time from when a packet is written to when the packet is read.

  Also, how much the negative amount is desirable is determined so as to satisfy the input / output packet timing for the parameter with the slowest rate. However, since the O multiple frame start flag has jitter, it is desirable to take into account the delay profile in order to consider the jitter, and the jitter to the negative amount.

  As described above, the TS reproduction circuit 17 resets the address positions of the write address counter 23 and the read address counter 24 when the synchronization between the multi-frame start timing and the multi-frame boundary of the actually output TS is shifted. ing. Therefore, the worst case (the longest case) from when the buffer memory 21 writes data to the buffer memory 21 until the data is read from the buffer memory 21 can be shortened, and the capacity of the buffer memory 21 can be reduced. it can.

(Scope of synchronization establishment and buffer capacity)
Next, setting values of the minimum value N _MIN and the maximum value N _MAX and the capacity of the buffer memory 21 will be described.

  The generation timing of the OFDM start flag ideally matches the effective symbol boundary position. Therefore, it is expected that a multiframe start flag (delayed OFDM start flag) is always generated at the effective symbol boundary position. However, in practice, since the shift of the extraction timing of the FFT operation has to be taken into account, in the worst case, the generation timing of the OFDM start flag is the guard interval when moving from the previous OFDM frame to the next OFDM frame. There is a possibility to move forward by the period. That is, in the worst case, when the generation timing of the multiple frame start flag (delayed OFDM start flag) captured in the synchronization acquisition state (frame number n) is the guard interval in the next OFDM frame period (frame number n + 1) Minute generation timing may be delayed.

  The minimum capacity of the buffer memory 12 is set to a capacity corresponding to the guard interval period so that underflow does not occur even in such a case.

  Similarly, when the OFDM start flag is generated from the previous OFDM frame to the next OFDM frame, there is a possibility that it will be delayed by the guard interval period.

The range from the minimum value N _{MIN to the} maximum value N _MAX is set to a value corresponding to the guard interval period so that it can be determined that the synchronization is established even when such a shift for the guard interval period occurs.

  Since the guard interval period has a different length depending on the transmission parameter, the above setting is performed in the longest guard interval period.

In addition, the above-described variation of the OFDM start flag is likely to occur in the multipath transmission path. In other words, when the synchronization timing moves from the fundamental wave to the delayed wave, there is a high possibility that this occurs because the extraction window of the FFT calculation varies. Therefore, to generate a delay profile of the received signals, calculates the worst value of the deviation of the OFDM start flag based on the delay profile, it may be reflected the worst value to the minimum value N _MIN and the maximum value N _MAX. If the delay profile is used in this way, the range from the minimum value N _MIN to the maximum value N _MAX can be shortened.

(Modification of array information table)
Next, a modified example of the description of the array information table stored in the table memory 27 will be described.

  The table memory 27 stores an array information table indicating a packet array indicating whether the TSP at each packet position in the multiplexed frame is a valid packet or a null packet. May not be the method shown in FIG. For example, as shown in FIG. 7, it may be an array information table 27-2 in which only packet numbers of valid packets are described.

However, in the case of sequence information table 27-2 that contains only the packet number of valid packets can not be directly used as the address of the table memory 27 the count value N ₂ of the packet counter 26. Therefore, as shown in FIG. 8, the TS reproducing circuit 17 further counts the packet identification flag to generate the address of the table memory 27, the packet number output from the table memory 27, and the packet counter 26. it may be provided a comparison circuit 52 which compares the count value N ₂ output from.

In such a TS reproduction circuit 17, the address counter 51 counts the packet identification flag. Therefore, the address counter 51 can increment the count value by one when a valid packet is generated once. The table memory 27 generates a valid packet number based on the address value generated from the address counter 51. Comparison circuit 52, a packet number that is generated from the table memory 27, when the count value N ₂ generated from the packet counter 51 matches, the packet identification flag valid (1), the packet identification flag when they do not match Is invalid (0).

  When the TS reproduction circuit 17 has such a circuit configuration, the array information table 27-2 describing only valid packet numbers can be used. The array information table 27-2 may describe only the null packet number instead of describing only the valid packet number.

Further, as shown in FIG. 9, instead of the address counter 51, it is provided with the address calculation circuit 53 for calculating the calculated address of the table memory 27 from the count value N ₂ of the packet counter 26, described only valid packet number The array information table 27-2 can be used.

  When the transmission parameters are mode 2 and mode 3, as shown in FIGS. 10 and 11, the packet arrangement in one multiplexed frame is a repetition of a predetermined arrangement pattern (subframe). In the case of mode 2, one multiplex frame is composed of two subframes. In mode 3, one multiplex frame is composed of four subframes. Therefore, in the case of mode 2 and mode 3, the arrangement information tables 27-1 and 27-2 stored in the table memory 27 are stored in the packet arrangement within one subframe as shown in FIGS. Only need to be described.

  Also, when performing partial reception of an OFDM signal transmitted by the 3-segment scheme, only the TSP of the A layer is included in the transport stream, and the TSP of the B layer is not included in the transport stream.

  For this reason, when performing partial reception, as shown in FIG. 12, the TSP transmitted to the B layer may be regarded as a null packet and the array information table may be described. That is, in the case of the array information table 27-1 that describes whether it is a valid packet or a null packet over one multiplex frame, the TSP of the A layer is described as 1, and the TSP of the B layer and the null packet is What is necessary is just to describe as 0. In the case of the array information table 27-2 describing only the packet number of the valid packet, only the TSP number of the A layer needs to be described.

(Modification of internal state determination circuit)
FIG. 13 shows a circuit configuration of an internal state determination circuit 60 which is a modification of the internal state determination circuit 30, and this circuit will be described. The same components as those of the internal state determination circuit 30 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The internal state determination circuit 60 includes a first register circuit 41, a second register circuit 42, a first comparator (A) 61, a second comparator (B) 62, and a third comparator. (C) 63 and a determiner 64.

The first register circuit 41 and the second register circuit 42 receive an internal clock (WCK) as a clock signal and a multiple frame start flag as an enable signal. Then, the first register circuit 41 the count value N ₁ of the byte counter 25 is input, the second register circuit 42 the count value N ₂ of the packet counter 26 is input. Therefore, inside the first register circuit 41, the count value N ₁ of the byte counter 25 with the generation timing of multiplexed frame start flag is held in the interior of the second register circuit 42, the multi-frame start flag count value N ₂ of the packet counter 26 at the occurrence timing is maintained.

The first comparator (A) 61 and the third comparator (C) 63 have values (count value N ₁ and count value N) held by the first register circuit 41 and the second register circuit 42. ₂ ) is input. The value (count value N ₂ ) held by the second register circuit 42 is input to the second comparator (B) 62.

Here, it is assumed that the minimum value N _MIN and the maximum value N _MAX used in the internal state determination circuit 30 are as follows.
N _MIN = P _MIN × 204 + B _MIN
N _MAX = P _MAX × 204 + B _MAX
At this time, the first comparator (A) 61, the second comparator (B) 62, and the third comparator (C) 63 perform the following comparison.

The first comparator (A) 61 outputs valid (1) if the count value N ₂ of the packet counter 26 is equal to P _MAX and the count value N ₁ of the byte counter 25 is equal to or less than B _MAX. Otherwise, invalid (0) is output.

Second comparator (B) 62 is a small count value _{N 2} is from _{P MAX} of the packet counter 26 and the count value _{N 2} of the packet counter 26 is equal greater than _{P MIN,} effective (1) Is output, otherwise invalid (0) is output.

The third comparator (C) 63 outputs valid (1) if the count value N ₂ of the packet counter 26 is equal to P _MIN and the count value N ₁ of the byte counter 25 is greater than or equal to B _MAX. Otherwise, invalid (0) is output.

  The output results of the first comparator (A) 61, the second comparator (B) 62, and the third comparator (C) 63 are output to the determiner 64.

  If any one of the three inputs is valid (1), the determiner 64 determines that the synchronization is established, and if all are invalid (0), sets the synchronization acquisition state.

Even when the internal state determination circuit 60 configured as described above is used, the internal state determination process can be performed in the same manner as the internal state determination circuit 30. If there is a relationship of P _MAX = P _MIN +1, the second comparator (B) 62 may not be provided.

It is a figure for demonstrating the transmission symbol of an OFDM signal. It is a block block diagram of the OFDM receiver of embodiment of this invention. It is a block block diagram of TS reproduction circuit in the said OFDM receiver. It is a figure which shows the arrangement | sequence information table stored in the table memory in the said TS reproduction circuit. It is a figure for demonstrating the determination range of the internal state determination circuit in the said TS reproduction circuit. It is a block block diagram of the internal state determination circuit in the said TS reproduction circuit. It is a figure which shows the modification of the arrangement | sequence information table stored in the table memory in the said TS reproduction circuit. FIG. 8 is a block configuration diagram illustrating a first circuit configuration example of a TS reproduction circuit for applying the array information table illustrated in FIG. 7. FIG. 8 is a block configuration diagram illustrating a second circuit configuration example of a TS reproduction circuit for applying the array information table illustrated in FIG. 7. It is a figure which shows the arrangement | sequence information table in the case of receiving the OFDM signal of mode 2. It is a figure which shows the arrangement | sequence information table in the case of receiving the OFDM signal of mode 3. It is a figure which shows the arrangement | sequence information table in the case of performing partial reception. It is a figure which shows the modification of an internal state determination circuit. It is a block block diagram of the conventional OFDM receiver.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 OFDM receiver, 11 Tuner, 12 OFDM demodulation circuit, 13 OFDM frame detection circuit, 14 Transmission path decoding circuit, 15 Delay circuit, 16 Transmission parameter decoding circuit, 17 TS reproduction circuit

Claims (16)

An effective symbol generated by time-division-dividing the bit sequence and orthogonally modulating into a plurality of subcarriers and a signal waveform at the end of the effective symbol are cyclically copied to the other end. OFDM demodulating means for demodulating the bit sequence from an orthogonal frequency division multiplexing (OFDM) signal whose transmission unit is a transmission symbol composed of a guard interval;
Transmission path decoding means for performing decoding processing corresponding to the standard of the transmission path on which the OFDM signal is transmitted with respect to the bit sequence demodulated by the OFDM demodulation means, and outputting decoded data;
OFDM frame detection means for detecting the OFDM frame start timing (OFDM frame start timing), which is a transmission unit composed of a predetermined number of transmission symbols;
Delay means for delaying the OFDM frame start timing by a time determined based on the processing delay time of the transmission path decoding means;
The decoded data output from the transmission path decoding means is stored, and the decoded data stored in synchronization with the frequency-stabilized clock (output clock) is read to generate a data stream synchronized with the output clock. Stream generating means,
The stream generation means includes
A buffer capable of simultaneously writing and reading data;
A writing unit for writing the decoded data output from the transmission path decoding unit to the buffer;
A reading unit that reads data from the buffer and outputs the read data as a data stream synchronized with the output clock;
A synchronization control unit that synchronizes the output start timing of a multiplexed frame, which is a transmission unit of a data stream composed of the number of packets corresponding to the time length of the OFDM frame, and the OFDM frame start timing output from the delay means; A transmission data reproducing apparatus characterized by the above. The stream generation means further includes a counting unit that performs a cyclic count of the total number of bytes of the multiplexed frame based on the output clock,
The synchronization control unit of the stream generation unit compares the count value of the count unit with the OFDM frame start timing output from the delay unit, and if the count value deviates from the OFDM frame start timing by a certain amount or more, The transmission data reproducing apparatus according to claim 1, wherein the count value of the count unit and the addresses of the writing unit and the reading unit are reset. The synchronization control unit captures the count value of the count unit at the OFDM frame start timing output from the delay unit, and outputs the acquired count value to the output start timing of the multiplexed frame and the OFDM frame start timing output from the delay unit. The count value of the counting unit and the address of the writing unit and the reading unit are reset when the time difference is out of a predetermined range. Transmission data playback device. The transmission data reproducing apparatus according to claim 3, wherein the predetermined range is set based on a guard interval length of the OFDM signal. The transmission data reproducing apparatus according to claim 3, wherein the predetermined range is set based on a delay profile of a transmission path through which the OFDM signal is transmitted. The transmission data reproducing apparatus according to claim 5, wherein the delay profile is calculated using a channel estimation value. 6. The transmission data reproducing apparatus according to claim 5, wherein the predetermined range is set based on a processing delay amount of the transmission path decoding means for an OFDM signal having the slowest bit rate. 4. The transmission data reproducing apparatus according to claim 3, wherein the range from the minimum value to the maximum value of the count value is changed according to a change in the configuration of the multiplexed frame. An effective symbol generated by time-division-dividing the bit sequence and orthogonally modulating into a plurality of subcarriers and a signal waveform at the end of the effective symbol are cyclically copied to the other end. The bit sequence is demodulated from an orthogonal frequency division multiplex (OFDM) signal whose transmission unit is a transmission symbol composed of a guard interval,
Performing a decoding process corresponding to the standard of the transmission path on which the OFDM signal is transmitted to the demodulated bit sequence, and generating decoded data;
Detecting the OFDM frame start timing (OFDM frame start timing), which is a transmission unit composed of a predetermined number of transmission symbols,
Delay the OFDM frame start timing by a time determined based on the processing delay time of the transmission path decoding process,
The decoded data generated by the transmission path decoding process is stored, and the decoded data stored in synchronization with the frequency-stabilized clock (output clock) is read to generate a data stream synchronized with the output clock. ,
Furthermore, when generating the data stream, the output start timing of the multiplexed frame, which is a data stream transmission unit composed of the number of packets corresponding to the time length of the OFDM frame, is synchronized with the delayed OFDM frame start timing. A transmission data reproduction method characterized by comprising: Generate a count value that cyclically counts the total number of bytes of the multiplex frame based on the output clock,
The count value is compared with the OFDM frame start timing output from the delay means, and when the count value deviates from the OFDM frame start timing by a certain amount or more, the count value of the count unit, the writing unit, and the reading The transmission data reproduction method according to claim 9, further comprising: resetting an address of the unit. When the count value at the delayed OFDM frame start timing is captured, and the captured count value is regarded as the time difference between the output start timing of the multiplexed frame and the delayed OFDM frame start timing, and the time difference is outside the predetermined range 11. The transmission data reproduction method according to claim 10, wherein the count value of the count unit and the addresses of the writing unit and the reading unit are reset. The transmission data reproduction method according to claim 11, wherein the predetermined range is set based on a guard interval length of the OFDM signal. The transmission data reproduction method according to claim 11, wherein the predetermined range is set based on a delay profile of a transmission path through which the OFDM signal is transmitted. The transmission data reproduction method according to claim 13, wherein the delay profile is calculated using a channel estimation value. The transmission data reproduction method according to claim 13, wherein the predetermined range is set based on a processing delay amount of the transmission path decoding process for an OFDM signal having the slowest bit rate. The transmission data reproduction method according to claim 12, wherein the range from the minimum value to the maximum value of the count value is changed in accordance with the change of the configuration of the multiplexed frame.

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