WO2013137222A1

WO2013137222A1 - Satellite communication reception device and reception method

Info

Publication number: WO2013137222A1
Application number: PCT/JP2013/056726
Authority: WO
Inventors: 康浩井戸
Original assignee: 三菱電機株式会社
Priority date: 2012-03-14
Filing date: 2013-03-12
Publication date: 2013-09-19

Abstract

Provided is a satellite communication reception device comprising the following: a reception means for receiving signals transmitted through a communication satellite; a plurality of frequency shift circuits (41-4n) for shifting the frequency of signals received by the reception means by different frequency shift amounts for each; a synchronization processing means for performing synchronization processing on the respective signals output by the frequency shift circuits (41-4n); and a line selection unit (9) for selecting, as the reception signals, the frequency shift circuit (41-4n) output signals for which synchronization was established by the synchronization means.

Description

Satellite communication receiving apparatus and receiving method

The present invention relates to a satellite communication receiving apparatus and a receiving method.

A satellite communication system that transmits signals between earth stations via a communication satellite is known. In this system, when a certain earth station (transmitting station) transmits a signal to another earth station (receiving station), a frequency deviation caused by a transmitting station, a local transmitter of a communication satellite, etc. occurs. When the frequency deviation exceeds the allowable deviation, the receiving station cannot receive the received signal.

As a technique for enabling reception of a received signal that exceeds a frequency tolerance, Patent Document 1 detects a phase difference from a signal delayed by a certain time with respect to the received signal, and averages the phase difference. Is an automatic frequency control circuit that corrects a frequency deviation of a received signal based on the received signal, and determines a received signal detection area based on a synchronization word (UW) included in the received signal, and receives based on the determined detected area An automatic frequency control circuit that corrects a frequency deviation when a signal is not correctly captured is disclosed.

Japanese Patent No. 3327152

The technique according to Patent Document 1 is premised on a demodulation operation by a delay detection method, and there is a problem that an effect cannot be obtained by a synchronous detection method widely used in fixed satellite communication. Further, since the technique according to Patent Document 1 corrects the frequency deviation of the received signal based on the synchronization word included in the received signal, it is applied when the received signal is a burst wave having no synchronization word. In the case where the received signal is a continuous wave, there is a problem that it is difficult to shorten the time until the establishment of reception synchronization due to the time for controlling the correction amount of the frequency deviation.

The present invention has been made in view of the above circumstances, and is not limited to a specific detection method and reception wave, and can be used to expand a reception frequency range and shorten a time until establishment of reception synchronization and a satellite communication reception apparatus and reception. It aims to provide a method.

A satellite communication receiver according to the present invention includes a receiving unit that receives a signal transmitted via a communication satellite, and a plurality of frequency shift circuits that shift the frequency of the signal received by the receiving unit with different frequency shift amounts. Each of the signals output from the plurality of frequency shift circuits includes synchronization processing means for performing synchronization processing, and selection means for selecting, as a reception signal, an output signal of the frequency shift circuit for which synchronization has been established by the synchronization processing means.

According to the present invention, the reception frequency range can be expanded and the time until establishment of reception synchronization can be shortened without being limited to a specific detection method and reception wave.

1 is a block diagram of a satellite communication system according to an embodiment of the present invention. It is a block diagram which shows schematic structure of the earth station shown in FIG. FIG. 3 is a block diagram of a receiving circuit of the modem device shown in FIG. 2. FIG. 4 is a block diagram of the IF sampling circuit shown in FIG. 3. It is a figure for demonstrating operation | movement of a frequency shift circuit. It is a block diagram of the frequency shift circuit which comprises the frequency shift part shown in FIG. FIG. 4 is a block diagram of a carrier processing unit shown in FIG. 3.

A satellite communication system according to an embodiment of the present invention will be described with reference to the drawings.

The satellite communication system 1000 according to the present embodiment includes a communication satellite 100 that is a space station and a plurality of earth stations 200, as shown in FIG.

The earth station 200 includes a master station 210 and a plurality of slave stations (VSAT: Very Small Aperture Terminal) 221 to 22m (m is an integer of 2 or more). Each of the plurality of slave stations 221 to 22m and the master station 210 transmits and receives signals through the

lines

30 and 40. The

lines

30 and 40 connecting each of the plurality of slave stations 221 to 22m and the master station 210 are relayed via the communication satellite 100.

The master station 210 is also called a HUB station, and performs setting / cancellation, monitoring, and control of the lines of the slave stations 221 to 22m. Each of the plurality of slave stations 221 to 22m is configured as a fixed station, a portable station, an in-vehicle station, and the like, and a line frequency is assigned to each of them by the control of the master station 210.

A signal is transmitted from the master station 210 to each of the slave stations 221 to 22m by a TDM (Time Division Multiplexing) system via the line 30. A continuous wave is transmitted from the master station 210 to each of the slave stations 221 to 22m through the line 30. The line 30 is a communication line, a supervisory control line, a tracking line in the case where the slave station has an automatic acquisition function in the satellite direction, etc., and its application is not limited.

The signals from each of the slave stations 221 to 22m to the master station 210 are transmitted by the TDMA (Time Division Multiple Access) system via the line 40. A burst wave is transmitted from each of the slave stations 221 to 22m to the master station 210 via the line 40. The line 40 may be used for a communication line, a monitoring line, or the like.

That is, the satellite communication system 1000 according to the present embodiment is configured as a TDM / TDMA system.

In the satellite communication system 1000, the receiving circuit of the modem device included in the earth station 200 has a configuration unique to the present embodiment. This unique configuration can be applied to any earth station of the master station 210 and the plurality of slave stations 221 to 22m. Therefore, hereinafter, the configuration of a predetermined earth station among the master station 210 and the plurality of slave stations 221 to 22m will be described as the configuration of the earth station 200.

As shown in FIG. 2, the earth station 200 is configured as an earth station having a receiving circuit of a modem that can capture the direction of the communication satellite 100. The earth station 200 communicates with the master station 210 or the slave stations 221 to 22m via the communication satellite 100.

The earth station 200 includes a directional antenna 20, an antenna control / drive unit 21, a high frequency transmission / reception unit 22, a modem device 23, and a terminal device 24.

The antenna 20 tracks the communication satellite 100 and transmits / receives radio waves to / from the communication satellite 100 under the control of the antenna control / drive unit 21.

The antenna control / drive unit 21 drives the antenna 20 in order to adjust the direction, polarization plane, and the like of the antenna 20. The antenna control / drive unit 21 directs the antenna 20 in the satellite direction based on the reception level and the reception synchronization information acquired from the modem 23.

The high frequency transmission / reception unit 22 is a device that transmits and receives a high frequency (RF) signal, and is configured integrally with the antenna control / drive unit 21 or installed in the vicinity of the antenna control / drive unit 21.

The modem 23 is connected to the high frequency transmitter / receiver 22 and supplies the reception level and the reception synchronization information to the antenna control / drive unit 21. Also, the modem 23 exchanges predetermined communication data with the terminal device 24.

Next, the receiving circuit 230 provided in the modem device 23 will be described with reference to FIG. The transmission circuit of the modem device 23 is based on a known design.

As shown in FIG. 3, the receiving circuit 230 of the modem 23 includes a frequency conversion unit 1, an analog-digital conversion circuit (ADC) 2, an IF sampling circuit 3, a frequency shift unit 4, a carrier processing unit 5, and the like. A symbol memory unit 6, a demodulation unit 7, a synchronous shift channel determination unit 8, a channel selection unit 9, a control unit 10, a decoding unit 11, and a data processing unit 12. The frequency shift unit 4, the carrier processing unit 5, the symbol memory unit 6, and the demodulation unit 7 operate under the control of the control unit 10.

The frequency converter 1 converts the RF signal sent from the high-frequency transmitter / receiver 22 into an intermediate frequency (IF) signal, and includes a synthesizer 1a, a mixer 1b, and a low-pass filter 1c. The synthesizer 1a is for selecting a reception frequency band, and supplies a sine wave signal used for frequency conversion to the mixer 1b. The mixer 1b converts the RF signal from the high frequency transmitter / receiver 22 into an IF signal in the operating frequency band of the ADC 2 based on the sine wave signal from the synthesizer 1a. This IF signal is sent to the ADC 2.

Specifically, the synthesizer 1a is a sine wave signal having a local oscillation frequency fo corresponding to the difference between the frequency fr (t) of the signal in the high frequency band to be received and the operating frequency band (frequency in the sampling frequency band) fi of the ADC 2. (Local oscillation signal) So (t) is generated and supplied to the mixer 1b. The mixer 1b mixes the reception signal Sr (t) and the local oscillation signal So (t), and outputs signals having frequencies of (fr−fo) and (fr + fo). The low-pass filter 1c extracts an intermediate frequency (IF) band signal having a frequency of (fr-fo) and outputs an analog IF (intermediate frequency) signal Sr (t).

The ADC 2 samples the analog IF signal Sr (t) sent from the frequency converter 1 at a predetermined sampling rate, converts it to a digital signal DSr (t), and sends it to the IF sampling circuit 3.

The IF sampling circuit 3 frequency-converts the digital IF signal DSr (t) sent from the ADC 2 to generate a baseband signal. This baseband signal is sent to the frequency shift unit 4.

Specifically, the IF sampling circuit 3 includes, for example, a numerically controlled oscillator (NCO) 31, first and

second mixers

32 and 33, and low-

pass filters

34 and 35 as shown in FIG. Composed.

The NCO 31 generates orthogonal local oscillation signals sin (ωn) and cos (ωn).

The first mixer 32 multiplies the digital IF signal DSr (t) by the local oscillation signal sin (ωn) and converts it into an I component baseband signal. The second mixer 33 multiplies the digital IF signal DSr (t) by the local oscillation signal cos (ωn) and converts it into a Q component baseband signal.

The low-pass filter 34 removes the double frequency component contained in the I component baseband signal by limiting the high frequency band.

The low pass filter 35 removes the double frequency component contained in the baseband signal of the Q component by limiting the high frequency band.

Thus, a complex baseband signal composed of an I component baseband signal and a Q component baseband signal is output.

The frequency shift unit 4 is a device that shifts the frequency of the signal received by the receiving means from the high frequency transmitting / receiving unit 22 to the IF sampling circuit 3. The frequency shift unit 4 includes a plurality of frequency shift circuits 41 to 4n (n is an integer of 2 or more). Each of the frequency shift circuits 41 to 4n shifts the frequency of the signal received by the receiving unit by a frequency shift amount different from that of other frequency shift circuits. In the following description, for easy understanding, the frequency shift amounts of the frequency shift circuits 41 to 4n are expressed as f1 to fn, respectively.

The frequency shift amounts f1 to fn of the frequency shift circuits 41 to 4n are bands in which an assumed range of reception frequency deviation included in the baseband signal (a wider range than the pullable range determined by the modulation band of the received signal) is determined by the symbol rate. The frequency corresponds to each section when divided into n pieces for each width (withdrawable range). That is, in the frequency shift circuits 41 to 4n, the frequency shift amount is determined so that the shift interval becomes equal to the pullable range.

For example, assume that the assumed range of the reception frequency deviation is fa, and the bandwidth determined by the symbol rate (withdrawable range) is fa / 4. At this time, n = 4, and the frequency shift circuits 41 to 44 are arranged. In this case, as shown in FIG. 5, the frequency shift circuit 41 shifts the frequency of the baseband signal by the frequency shift amount f1 = fa / 8 and sends it to the carrier processing unit 5. Further, the frequency shift circuit 42 shifts the frequency of the baseband signal by the frequency shift amount f2 = −fa / 8 and sends it to the carrier processing unit 5. Further, the frequency shift circuit 43 shifts the frequency of the baseband signal by the frequency shift amount f3 = 3 × fa / 8 and sends it to the carrier processing unit 5. Further, the frequency shift circuit 44 shifts the frequency of the baseband signal by the frequency shift amount f4 = −3 × fa / 8 and sends it to the carrier processing unit 5. In this way, the frequency shift unit 4 can receive the same line in a plurality of frequency bands. The shift interval may be smaller than the pullable range.

Each of the frequency shift circuits 41 to 4n includes an NCO 401,

mixers

402 and 403, and low-

pass filters

404 and 405, as illustrated in FIG.

The NCO 401 of the frequency shift circuit 4i (i = 1 to n) generates a local oscillation signal having a frequency corresponding to the frequency shift amount fi (i = 1 to n). The mixer 402 multiplies the I component baseband signal and the local oscillation signal, and outputs an I component baseband signal shifted in frequency by fi. The mixer 403 multiplies the Q component baseband signal and the local oscillation signal, and outputs a Q component baseband signal whose frequency is shifted by fi. The low-pass filter 404 outputs only the low frequency side of the signal output from the mixer 402 to the carrier processing unit 5. The low-pass filter 405 outputs only the low frequency side of the signal output from the mixer 403 to the carrier processing unit 5.

The NCO 401 of the frequency shift circuit 4i (i = 1 to n) receives the frequency deviation fbi from the AFC unit 75 of the demodulator 7 described later, so that the frequency displacement fbi is set to 0, for example, the local signal The frequency fi is corrected to fi-fbi. This point will be described later.

According to the frequency shift unit 4, the baseband signal can be waited at n (plural) frequencies. For this reason, the allowable deviation of the reception frequency can be expanded. In addition, each frequency shift circuit 41 to 4n can perform processing in parallel, and the received signal of the received signal can be processed at a higher speed than the method of expanding the pullable frequency range by sweeping on the frequency axis by one frequency shift circuit. Pull-in is possible.

The carrier processing unit 5 oversamples a plurality of baseband signals from each of the frequency shift circuits 41 to 4n in accordance with the symbol rate, adjusts the waveform shaping processing for limiting the channel band, and the signal power level to be constant. AGC (Automatic-Gain-Control) processing, BTR (Bit-Timing-Recovery) processing for obtaining bit synchronization, and the like are executed, and after correcting the bit timing error, a time-multiplexed baseband signal is generated. The generated signal is stored in the symbol memory unit 6.

Specifically, the carrier processing unit 5 includes an input unit 51, an oversampling unit 52, a waveform shaping circuit 53, an AGC circuit 54, and a BTR unit 55, as shown in FIG.

The input unit 51 takes in and outputs the output signals of the frequency shift circuits 41 to 4n and supplies them to the subsequent stage in a time division manner.

The oversampling unit 52 oversamples the signal at a sampling frequency corresponding to the symbol rate of the transmission signal, in this example, the symbol rate of the transmission data of the center station and the symbol rate of the transmission wave of the satellite. .

The waveform shaping circuit 53 shapes the waveform of the output signal of the oversampling unit 52 so as to remove the frequency component of the unnecessary reception band based on the band limitation of the channel of the received signal.

The AGC circuit 54 adjusts the amplitude so that the power level of the signal becomes constant.

The BTR unit 55 generates a clock serving as a bit timing reference from a signal whose power level is adjusted to be constant.

The symbol memory unit 6 stores symbol data from the carrier processing unit 5 and is composed of n symbol memories 61 to 6n. The time-multiplexed baseband signal from the carrier processing unit 5 is stored in the symbol memories 61 to 6n for each channel whose frequency is shifted by each of the frequency shift circuits 41 to 4n constituting the frequency shift unit 4. Specifically, in the symbol memory 6i (i = 1 to n), the carrier processing unit 5 processes the output signal of the frequency shift circuit 4i and outputs the baseband signal and the clock timing generation signal (BTR). Remember.

The demodulator 7 acquires time-multiplexed data from the symbol memory unit 6 and demodulates the acquired data. The demodulator 7 includes a continuous wave (CW) detector 71, a synchronization word (UW) detector 72, and a phase estimator 73. And a soft decision unit 74 and an AFC (Automatic Frequency Control) unit 75.

A CW (Continuous Wave) detection unit 71 determines whether or not the received wave is a continuous wave from a series of baseband signals and BTR stored in each symbol memory 6 i (i = 1 to n) of the symbol memory unit 6. To detect. That is, the CW detection unit 71 determines whether the baseband signal stored in the symbol memory 6i is a signal that is continuously output or a signal that is temporarily output. Further, if the CW detection unit 71 determines that the wave is a continuous wave, the CW detection unit 71 performs demodulation processing within one frame based on the BTR. If not (that is, if the received wave is a burst wave), Based on this, demodulation processing within one burst is performed. The CW detection unit 71 sequentially performs this operation while switching the symbol memory 6i (i = 1 to n).

The UW detection unit 72 detects a unique word (UW) pattern arranged in a series of baseband signals stored in the symbol memory 6i (i = 1 to n) of the symbol memory unit 6.

The phase estimation unit 73 estimates the carrier phase based on the UW pattern detected by the UW detection unit 72, the baseband signal stored in the symbol memory 6i, and the BTR.

Soft decision unit 74 outputs a soft decision value of the demodulated data. That is, the soft decision unit 74 calculates a soft decision value for each bit of the baseband signal based on the carrier phase estimated by the phase estimation unit 73, the baseband signal stored in the symbol memory 6i, and the BTR. Ask.

The AFC unit 75 obtains a phase rotation amount per symbol from a phase difference over a plurality of symbols of the received signal, and detects a frequency deviation.

The demodulator 7 performs the above operation on the symbol memories 61 to 6n while switching i. The demodulator 7 performs demodulation operation in a time division manner and returns frequency deviation data indicating the frequency deviation detected by the AFC unit 75 to the frequency shift circuits 41 to 4n. Each frequency shift circuit 4i (i = 1 to n) of the frequency shift unit 4 adjusts the frequency of the local signal of the NCO 401 based on the frequency deviation data notified from the AFC unit 75 so that the frequency deviation becomes zero. (to correct. For example, when the frequency deviation is fb, the frequency of the local oscillation signal fi is -fb. However, the frequency deviation data here is limited within the pullable range delimited by the frequency shift circuits 41 to 4n. The demodulator 7 determines whether synchronization is established from the soft decision value generated by the soft decision unit 74, the demodulation result of the CW detection unit, etc., and the synchronization establishment information indicating the discrimination result and the soft decision unit 74 The generated soft decision value is output for each symbol memory 6i.

Thus, the carrier processing unit 5, the symbol memory 6, and the demodulation unit 7 perform synchronization processing on each of the output signals of the frequency shift circuits 41 to 4n.

The synchronization shift line determination unit 8 determines a shift line for which reception synchronization has been established based on the synchronization establishment information supplied from the demodulation unit 7 and notifies the line selection unit 9 of line selection information indicating the determination result. . For example, assume that it is determined that synchronization is established for the baseband signal stored in the symbol memory 6i. At this time, the synchronous shift line determination unit 8 determines that the shift line processed by the frequency shift circuit 4 i is a shift line for which synchronization has been established, and outputs line selection information indicating i to the line selection unit 9.

The line selection unit 9 extracts the received data of the shift line for which reception synchronization has been established from the time multiplexed data, transmits it to the decoding unit 11 as a soft decision signal, and notifies the control unit 10 of the number of the selected shift line. That is, the line selection unit 9 extracts only the received data of the normally received shift line based on the line selection information from the synchronous shift line determination unit 8 and sends only the received data to the decoding unit 11.

For example, it is assumed that the line selection information indicating the shift line number i is provided from the synchronous shift line determination unit 8 to the line selection unit 9. At this time, the line selection unit 9 outputs the soft signal generated based on the baseband signal stored in the symbol memory 6 i to the decoding unit 11. Then, the line selector 9 discards the soft signals generated from the other symbol memories 61 to 6 (i−1) and 6 (i + 1) to 6n. Further, the line selection unit 9 notifies the control unit 10 of the shift line number i.

As described above, the synchronization shift line determination unit 8 and the line selection unit 9 select the output signal of any frequency shift circuit in which synchronization is established by the carrier processing unit 5 to the synchronization shift line determination unit 8. And output to the decoding unit 11.

The control unit 10 is composed of a CPU (Central Processing Unit) ROM (Read Only Memory) or the like, and controls the operation of each unit by the CPU operating based on data and programs stored in the ROM or the like.

The control unit 10 instructs the frequency shift unit 4 to stop the function blocks related to the lines other than the shift line for which reception synchronization has been established, based on the shift line number notified from the line selection unit 9. Thereby, the operation of the circuit is unnecessarily suppressed and the power consumption of the circuit is suppressed. Specifically, when the shift line number notified from the line selection unit 9 is i, the control unit 10 causes the frequency shift unit 4 to operate only the frequency shift circuit 4i, so that other frequency shift circuits, that is, frequency The shift circuits 41 to 4 (i−1) and 4 (i + 1) to 4n are instructed to be stopped. In addition, the control unit 10 instructs the carrier processing unit 5 to process only the output of the frequency shift circuit 4i. Further, the control unit 10 causes the symbol memory unit 6 to store only the symbol memory 6i, and stops the storage operation of other symbol memories, that is, the symbol memories 61 to 6 (i-1) and 6 (i + 1) to 6n. Instruct them to do so. Further, the control unit 10 instructs the demodulation unit 7 to process only the data in the symbol memory 6i.

The frequency shift unit 4 operates the frequency shift circuit 4i in response to an instruction from the control unit 10, and pauses the other frequency shift circuits 41 to 4 (i-1) and 4 (i + 1) to 4n. Further, in response to an instruction from the control unit 10, the carrier processing unit 5 switches the internal state to a state where only the output of the frequency shift circuit 4i can be processed. In response to an instruction from the control unit 10, the symbol memory unit 6 stops the operation of symbol memories other than the symbol memory 6i. The symbol memory 6i stores a baseband signal generated from the output signal of the frequency shift circuit 4i by the carrier processing unit 5. Further, in response to an instruction from the control unit 10, the demodulation unit 7 processes only the data in the symbol memory 6i.

The decoding unit 11 is based on the soft decision value generated from the baseband signal obtained from the normally received shift line sent from the line selection unit 9 and the error correction method used for the

line

30 or 40. Decrypt. The signal decoded by the decoding unit 11 is sent to the data processing unit 12 as decoded data.

The data processing unit 12 transmits the received data to the terminal device 24 shown in FIG. 2 in a form corresponding to the conversion to the terminal data format and the communication protocol.

In the receiving circuit 230 of the modulation / demodulation device 23 configured as described above, the frequency shift unit 4 can wait for a baseband signal at a plurality of frequencies. For this reason, as a result, the allowable deviation of the reception frequency can be increased. Further, since the frequency shift unit 4 can perform processing in parallel by each of the frequency shift circuits 41 to 4n, the frequency shift unit 4 is a method of expanding the pullable frequency range by sweeping on the frequency axis by one frequency shift circuit. In comparison, it is possible to pull in the received signal at high speed.

The reception frequency deviation in the communication line is the sum of the transmission frequency deviation from the transmission earth station and the frequency deviation of the local oscillation circuit of the communication satellite. For example, in a satellite communication system, a voice band signal, a small amount of control signal When the communication line is a narrow-band line and the reception frequency deviation is larger than that, the receiving earth station 200 cannot pull in the signal. Even in such a case, according to the receiving circuit 230 according to the present embodiment, it is possible to widen the pullable frequency range, and thus it is possible to maintain good reception accuracy.

In addition, when the main factor of the reception frequency deviation is the transmission frequency deviation of the transmitting station, it is not necessary to keep the transmission deviation of the transmitting station with higher precision than necessary. There is no need to provide a highly accurate reference signal source in the earth station. Therefore, the price of the earth station can be reduced.

Further, according to the receiving circuit 230, since the time until the establishment of reception synchronization can be shortened, a high-speed acquisition is possible in a system that performs acquisition in the satellite direction with determination of establishment of reception synchronization. Therefore, as a result, the time required to start the satellite line and the time required for re-acquisition can be shortened, and the satellite line can be quickly connected.

Further, in the configuration of the receiving circuit 230 of the present embodiment, the portions other than the frequency shift circuits 41 to 4n constituting the frequency shift unit 4 are realized by the time-division operation of the same circuit, so that the FPGA (Field-Programmable) is mainly used. It is possible to minimize the amount of increase in circuit capacity of digital elements such as Gate Array.

In addition, this invention is not limited by said embodiment and drawing. Changes can be made as appropriate (including deletion of components).

For example, the circuit configuration itself of the modem device 23 illustrated in FIG. 3 can be changed as needed. Also, the circuit shown in FIG. 3 may be configured by a discrete circuit or a DSP (Digital Signal Processor) or the like. In addition, the line selection by the line selection unit 9 can be performed based on, for example, synchronization establishment information instead of the output of the synchronization shift line determination unit 8. That is, the soft decision value of the shift line determined to have established synchronization may be output to the decoding unit 11 and the control unit 10 may be notified of information about the shift line. In this case, the synchronous shift line determination unit 8 may be removed.

The earth station 200 is not provided with the antenna control / drive unit 21, and the earth station 200 may not have an automatic satellite capturing function. Moreover, the earth station 200 may not have a transmission function but may have only a reception function. In these cases, as in the above embodiment, the reception frequency deviation can be increased and the satellite line can be quickly connected.

Any of the above embodiments can be variously modified within the scope of the gist of the present invention. The above embodiments are for explaining the present invention, and are not intended to limit the scope of the present invention. The scope of the invention is indicated by the appended claims rather than the embodiments. Various modifications made within the scope of the claims and within the scope equivalent to the claims of the invention are included in the scope of the present invention.

This application claims priority based on Japanese Patent Application No. 2012-057479 filed on March 14, 2012, including the specification, claims, figures, and abstract. The disclosure of this original patent application is hereby incorporated by reference in its entirety.

1000 satellite communication system, 100 communication satellite, 200 earth station, 210 master station, 221-22m slave station, 30, 40 lines, 20 antennas, 21 antenna control / drive unit, 22 high frequency transmission / reception unit, 23 modulation / demodulation device, 24 terminal device , 230 receiver circuit, 1 frequency converter, 1a synthesizer, 1b mixer, 1c low pass filter, 2 ADC, 3 IF sampling circuit, 31 NCO, 32, 33 mixer, 34, 35 low pass filter, 4 frequency shift unit, 41 to 4n Frequency shift circuit, 401 NCO, 402, 403 mixer, 404, 405 low pass filter, 5 carrier processing unit, 51 input unit, 52 oversampling unit, 53 waveform shaping circuit, 54 AGC circuit, 55 BTR unit, 6 symbol Memory section, 61-6n symbol memory, 7 demodulator section, 71 CW detection section, 72 UW detection section, 73 phase estimation section, 74 soft decision section, 75 AFC section, 8 synchronous shift line determination section, 9 line selection section, 10 Control unit, 11 decoding unit, 12 data processing unit.

Claims

Receiving means for receiving a signal transmitted via a communication satellite;
A plurality of frequency shift circuits for frequency-shifting the signals received by the receiving means by different frequency shift amounts;
Synchronization processing means for performing synchronization processing for each of the signals output from the plurality of frequency shift circuits;
Selecting means for selecting, as a received signal, an output signal of the frequency shift circuit whose synchronization is established by the synchronization processing means,
Satellite communication receiver.
The selection means includes means for stopping the operation of a frequency shift circuit other than the frequency shift circuit that generated the output signal with which synchronization is established,
The satellite communication receiver according to claim 1.
The selection unit includes a unit that causes the synchronization processing unit to stop synchronization processing for an output signal of a frequency shift circuit other than the frequency shift circuit that generates the output signal with which synchronization is established.
The satellite communication receiver according to claim 1 or 2.
The synchronization processing means executes processing for generating a baseband signal from outputs of the plurality of frequency shift circuits and demodulation processing for demodulating the generated baseband signal in a time division manner, and synchronizes the outputs of the frequency shift circuits. Determine whether or not
The satellite communication receiving device according to any one of claims 1 to 3.
The synchronization processing means obtains a frequency deviation for the signal of each frequency shift circuit, and feeds back the obtained frequency deviation to the corresponding frequency shift circuit.
Each frequency shift circuit adjusts the amount of frequency shift based on the fed back frequency deviation.
The satellite communication receiver according to any one of claims 1 to 4.
The shift interval of the plurality of frequency shift circuits is less than or equal to the pullable range determined by the modulation band,
The satellite communication receiver according to any one of claims 1 to 5.
The receiving means includes means for generating a baseband signal of an intermediate frequency band from the received high-frequency signal.
The satellite communication receiver according to any one of claims 1 to 6.
Receive the signal,
The received signal is divided into a plurality of signals, and the plurality of signals are frequency shifted by different frequency shift amounts,
Performing synchronization processing for each of the plurality of signals shifted in frequency and determining whether reception synchronization has been established for each of the plurality of signals subjected to synchronization processing;
Selecting and outputting a signal determined to have established reception synchronization among the plurality of signals;
Receiving method.