JP4637661B2 - Modulation signal demodulator - Google Patents

Description

  The present invention relates to a demodulator for a modulated signal.

For example, Japanese Patent Laid-Open No. 2002-111863 discloses a demodulator for a PSK (Phase Shift Keying) modulation signal (orthogonal modulation signal). In order to perform synchronization processing at the time of demodulation of the received PSK modulated signal with high accuracy, the demodulator synchronizes with the timing synchronization signal indicating the synchronization timing of the transmission symbol of the PSK modulated signal, and uses the frequency of the timing synchronization signal. Sampling means for sampling the PSK modulated signal with a high frequency sampling signal, and power between two signal points at symmetrical phase positions centering on the intermediate timing of the adjacent synchronization timings from the sampled PSK modulated signal A level difference is obtained, the power level difference is averaged, and a phase error detecting means for detecting a phase error of the synchronization timing of the transmission symbol, and a frequency and a phase of the timing synchronization signal are controlled so that the phase error becomes zero. Control means.
JP 2002-111863 A

However, in the above prior art, the synchronization processing at the time of demodulation can be performed with high accuracy, but when the I signal and the Q signal are orthogonally demodulated from the PSK modulation signal, the I signal and the In order to perform signal processing of the Q signal, it is necessary to arrange components such as a multiplier, a low-pass filter, and an A / D converter in the two systems. Therefore, there are problems that the number of parts increases, the circuit scale increases, and the device cost increases.

 The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to simplify the circuit configuration of a demodulating device and reduce the device cost.

In order to achieve the above object, the following means were adopted.
Demodulator of the modulation signal according to the present invention, there is provided a demodulating apparatus for demodulating a modulated signal received, and a sampling unit for sampling with a sample frequency of power times 2 the modulated signal (excluding 0 power), the A predetermined first signal and a second signal having a phase different by π / 2 with respect to the first signal out of signals obtained by the sampling process in the sampling unit connected to the sampling unit ; A time-division processing unit that outputs the first signal and the second signal after time-division processing; and the first signal that is connected to the time-division processing unit and is time-division-processed by the time-division processing unit and output the second signal includes a multiplier for outputting by multiplying a predetermined frequency signal supplied from a predetermined oscillator, and a control unit for controlling the oscillator, the sampling unit, the time division processing section and The multiplier is connected in series and configured in one system, and the control unit detects an error in synchronization timing between the first signal and the second signal output from the time division processing unit, and the error The oscillator is controlled so that becomes zero .

The modulation signal is an analog signal, and the sampling unit includes an A / D converter that converts the analog signal into a digital signal, and the time division processing unit is a digital signal output from the A / D converter. The first signal and the second signal are extracted based on the signal, and the first signal and the second signal are time-division processed and output.

The oscillator supplies a frequency signal having the same value to the multiplier every two time division periods of the first signal and the second signal that are output from the time division processing unit. To do.

 According to the present invention, the modulation signal is sampled at a sampling frequency that is a power of 2 (excluding the 0th power), and among the signals obtained by the sampling process, a predetermined first signal and the first signal The second signal having a phase difference of π / 2 is extracted, and the first signal (that is, the I signal) and the second signal (that is, the Q signal) are output as time-division processed signals. Thus, it is not necessary to branch the I signal and the Q signal into different systems for signal processing. Therefore, the circuit configuration can be simplified and the device cost can be reduced.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a modulation signal demodulator according to an embodiment of the present invention. As shown in this figure, the demodulator R includes an antenna 1, an RF converter 2, an A / D converter 3, a time division processing unit 4, a multiplier 5, an LPF (Low Pass Filter) 6, a baseband processing unit 7, A Costas loop circuit 8, a first oscillator 9, and a second oscillator 10 are included. The demodulator R configured as described above receives an RF modulation signal (analog signal) transmitted from the transmitter S and demodulates the RF modulation signal.

 In the present demodulator R, the antenna 1 receives the RF modulation signal transmitted from the transmitter S and outputs the RF modulation signal to the RF converter 2. The RF converter 2 down-converts the RF modulation signal input from the antenna 1 into an intermediate frequency band, that is, converts it to an IF modulation signal and outputs the IF modulation signal to the A / D converter 3.

 The A / D converter 3 performs a sampling process on the IF modulation signal input from the RF converter 2 based on a sampling clock signal that defines a sampling frequency input from the second oscillator 10, and is obtained by the sampling process. The digital signal of the IF modulation signal is output to the time division processing unit 4. The sampling frequency is defined as a sampling frequency 8fc that is four times the sampling frequency 2fc that satisfies the sampling theorem at a minimum, where fc is the carrier frequency of the IF modulation signal.

 The time division processing unit 4 includes a first digital signal at a predetermined sampling point from the digital signal output from the A / D converter 3, and a second digital signal at a sampling point whose phase is different from the first digital signal by π / 2. And the first digital signal as an I signal and the second digital signal as a Q signal, time division processing of these signals is performed, and the time-divided digital signal (IQ digital signal) is output to the multiplier 5 To do. Details of the time division processing by the time division processing unit 4 will be described later.

 The multiplier 5 multiplies the IQ digital signal output from the time division processing unit 4 and the digital signal (IFLO signal) indicating the cosine wave signal (frequency signal) of the frequency fc input from the first oscillator 9. The I and Q signals included in the IQ digital signal are demodulated, and the demodulated IQ digital signal is output to the LPF 6. The LPF 6 removes a high frequency component from the demodulated IQ digital signal input from the multiplier 5 and outputs the IQ digital signal after the removal of the high frequency component to the baseband processing unit 7 and the Costas loop circuit 8.

 The baseband processing unit 7 is a baseband processor, for example, and performs various signal processing based on the I signal and the Q signal included in the IQ digital signal. The Costas loop circuit 8 detects a synchronization timing error between the I signal and the Q signal included in the IQ digital signal, generates a Costas loop control signal so that the error becomes 0, and generates the first oscillator 9 and the second oscillator 9. Output to the oscillator 10.

 The first oscillator 9 is, for example, a VCO (Voltage Controlled Oscillator), and outputs an IFLO signal (digital signal) whose oscillation frequency is voltage-controlled by a Costas loop control signal to the multiplier 5. Similarly, the second oscillator 10 is a VCO, for example, and outputs a sampling clock signal whose oscillation frequency is voltage-controlled by a Costas loop control signal to the A / D converter 3.

Next, the operation of the demodulator R configured as described above will be described.
First, the RF modulation signal received by the antenna 1 is down-converted to an IF modulation signal by the RF converter 2 and output to the A / D converter 3. In the A / D converter 3, the IF modulation signal is sampled at a sampling frequency 8fc defined by the sampling clock signal.

 Here, as shown in FIG. 2, a cosine wave signal having a carrier frequency fc (period Tc) of the IF modulation signal is assumed. Since the sampling frequency that satisfies the sampling theorem at a minimum is 2fc, the sampling frequency Ts = Tc / 8 when the sampling frequency is obtained by multiplying the 2fc by 4 times, and the sampling point becomes the cycle Tc. On the other hand, there are 9 points from P1 to P9. Therefore, the A / D converter 3 outputs the digital signals D1 to D9 at the sampling points P1 to P9 to the time division processing unit 4. Hereinafter, for simplification of description, description will be given using digital signals D1 to D9 related to one cycle Tc.

 By the way, the definition of the I signal and the Q signal is that a signal having a phase different by π / 2 from the I signal is a Q signal, and a signal having a phase different by π / 2 from the Q signal is an I signal. When the digital signal D1 of P1 is an I signal, the Q signal corresponding to the digital signal D1 is a sampling point whose phase is π / 2 different from the sampling point P1, that is, a sampling point whose phase is shifted by Tc / 4 from the sampling point P1. It is sufficient to extract the digital signal D3 of P3.

 Therefore, the time division processing unit 4 extracts the digital signal D1 at the sampling point P1 as the I signal (I1) and extracts the digital signal D3 at the sampling point P3 as the Q signal (Q1). Are set as a set of IQ digital signals (I1 = D1, Q1 = D3). Subsequently, the time division processing unit 4 extracts the digital signal D2 at the sampling point P2 as an I signal (I2), and extracts the digital signal D4 at the sampling point P4 as a Q signal (Q2). The signal is set as a set of IQ digital signals (I2, Q2). The time division processing unit 4 sets IQ digital signals in the same manner and performs time division processing on these IQ digital signals, thereby time-divided IQ digital signals (I1, Q1) (I2, Q2) (I3, Q3) (I4, Q4) to (I9, Q9) are generated and output to the multiplier 5.

  In the multiplier 5, the IQ digital signal time-divided as described above is multiplied by the IFLO signal input from the first oscillator 9. At this time, the IFLO signal is multiplied by the I signal and the Q signal of (I1, Q1) which are a set of IQ digital signals, respectively, but the IFLO signal of the same value is applied to the set of IQ digital signals. The next set of IQ digital signals is multiplied by an IFLO signal whose value has been updated. In this way, it is possible to synchronize the I signal and the Q signal.

  As described above, the IQ digital signal is demodulated by being multiplied by the IFLO signal, and the high-frequency component is removed from the IQ digital signal by the LPF 6, whereby the I signal and the Q signal that can be processed by the baseband processing unit 7 are obtained. Played.

 As described above, according to this embodiment, the A / D converter 3 that samples the IF modulated signal at a frequency four times the sampling frequency that satisfies the sampling theorem at the minimum is used. By extracting the digital signal at two sampling points having a phase difference of π / 2 from the digital signal obtained as described above as an I signal or Q signal and outputting it as a time-division IQ digital signal, There is no need to branch the Q signal into different systems for signal processing. Therefore, the circuit configuration can be simplified, and the device cost can be reduced by reducing the number of parts.

  In addition, this invention is not limited to the said embodiment, For example, the following modifications can be considered.

(1) In the above embodiment, the sampling frequency that satisfies the sampling theorem as a minimum is described with reference to 2fc, and a frequency that is 4 times the 2fc is described as the sampling frequency. A value larger than 2fc may be set. Thereby, highly accurate A / D conversion can be performed.

(2) In the above embodiment, the sampling frequency that satisfies the sampling theorem as a minimum is described with reference to 2fc, and 4 times the 2fc is described as the sampling frequency. The value to be multiplied may be a power of 2. However, the case of 0th power is excluded.

1 is a block diagram illustrating a configuration of a modulation signal demodulator according to an embodiment of the present invention. It is explanatory drawing which shows the sampling processing method in one Embodiment of this invention.

Explanation of symbols

 R ... demodulator, 1 ... antenna, 2 ... RF converter, 3 ... A / D converter, 4 ... time division processing unit, 5 ... multiplier, 6 ... LPF (Low Pass Filter), 7 ... baseband processing unit, 8 ... Costas loop circuit, 9 ... first oscillator, 10 ... second oscillator, S ... transmitter

Claims (3)

A demodulator that demodulates a received modulated signal,
A sampling unit that samples the modulated signal at a sample frequency that is a power of 2 (excluding the 0th power);
Of the signals connected to the sampling unit and obtained by the sampling process in the sampling unit, a predetermined first signal and a second signal having a phase different by π / 2 with respect to the first signal are extracted, A time division processing unit for time-division processing and outputting the first signal and the second signal;
Connected to the time division processing unit, the first signal and the second signal division processing has been outputted when by the time division processing unit, and outputs the multiplied by a predetermined frequency signal supplied from a predetermined oscillator A multiplier,
A control unit for controlling the oscillator,
The sampling unit, the time division processing unit and the multiplier are connected in series and configured in one system,
The controller is
Detecting an error in synchronization timing between the first signal and the second signal output from the time division processing unit, and controlling the oscillator so that the error becomes 0;
A modulation signal demodulating device. The modulation signal is an analog signal;
As the sampling unit , an A / D converter for converting an analog signal into a digital signal is provided,
The time division processing unit extracts the first signal and the second signal based on the digital signal output from the A / D converter, and outputs the first signal and the second signal after time division processing. The modulation signal demodulator according to claim 1. The oscillator supplies a frequency signal having the same value to the multiplier every two time division periods of the first signal and the second signal which are output from the time division processing unit. Item 3. An apparatus for demodulating a modulated signal according to Item 1 or 2.

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