KR100246619B1 - Demodulation apparatus for up-stream link in very high speed digital subscriber line - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a digital demodulation device for a high speed digital subscriber line uplink.

2. The technical problem to be solved by the invention

An object of the present invention is to provide a digital demodulation device that recovers symbol timing by adjusting only a phase of a symbol without tracking a symbol frequency error in an uplink of a high speed digital subscriber line.

3. Summary of Solution to Invention

The present invention provides an analog / digital conversion means for receiving a modulated signal from an external source and converting it into a digital signal, a down sampling means for lowering a sample rate, a resampling means for sampling a signal for determining a symbol value from data, and a carrier phase recovery means. And a symbol timing recovery means for performing symbol timing recovery.

4. Important uses of the invention

The present invention is used in a four-phase modulation (QPSK) demodulation device.

Description

Digital demodulation device for uplink of high speed digital subscriber line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulation and demodulation device for a communication system, and more particularly, to four-phase modulation (QPSK: Quadurature), which transmits data as a signal having a predetermined size by carrying data on phase information in an uplink of a very high rate subscriber line (VDSL). It relates to a demodulation device of the Phase Shift Keying) method.

A conventional four-phase modulation (QPSK) demodulation apparatus first extracts symbol frequency information to find a range of received symbol frequencies and recovers symbol timing through symbol phase information in order to recover symbol timing. This general scheme could be applied to high speed digital subscriber lines. However, in the above-described high speed digital subscriber line, the conventional method has a problem in that unnecessary computation is performed and the convergence speed of symbol recovery or carrier phase recovery is significantly lowered.

In order to solve the problems described above, the present invention is to recover the symbol timing by restoring only the exact symbol phase without finding the symbol frequency range when implementing the reception part of the four-phase modulation (QPSK) modulation system. An object of the present invention is to provide an uplink digital demodulation device for a high speed digital subscriber line that performs carrier phase recovery.

1 is a schematic diagram of a high speed digital subscriber line system to which the present invention is applied;

2 is a block diagram showing the configuration of a digital demodulation device of a four-phase modulation (QPSK) method according to an embodiment of the present invention.

3 is a block diagram showing an embodiment of a symbol timing recovery unit of the apparatus shown in FIG. 2;

* Explanation of symbols for the main parts of the drawings

20: analog / digital converter 21: multiplier

22: down sampling unit 23: low pass filter

24: symbol value determining section 25: four-phase modulation decoding section

26 resampler 27 control oscillator

28: symbol timing recovery unit 29: carrier phase recovery unit

30: in-phase signal transition detector 31: in-phase signal error predictor

32: quadrature signal transition detector 33: quadrature signal error predictor

34: multiplier 35: multiplier

36: adder 37: accumulator

38 threshold detector 39 sampling positioner

40: Current status register

The present invention for achieving the above object, Analog / digital conversion means for converting an analog signal received from the outside into a digital signal; First multiplication means for converting a pass band signal into a base band signal with respect to the output signal of the analog / digital conversion means; Down sampling means for lowering a sample rate of a signal passing through said first multiplication means by a predetermined multiple in accordance with an applied sampling positioning signal; Low pass filtering means for removing integer frequency components of the original signal spectrum with respect to the output signal of the down sampling means; Resampling means for performing sampling for symbol value determination from data passing through the low pass filtering means in accordance with an applied sampling positioning signal; Symbol timing recovery means for receiving the resampled data from the resampling means and performing symbol timing recovery and providing a sampling positioning signal to the down sampling means and the resampling means; Carrier phase recovery means for restoring a carrier phase by receiving the resampled data from the resampling means; Control oscillation means for generating an oscillation signal by correcting the signal recovered by the carrier phase restoration unit according to a carrier phase error signal which is an output signal of the symbol timing restoration means; Symbol value determining means for receiving data output from the resampling means and determining a symbol value; And four-phase modulation (QPSK) decoding means for generating a serial bit stream in accordance with the symbol value determined by the symbol value determining means.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 3.

1 is a schematic configuration diagram of a high-speed digital subscriber line system to which the present invention is applied and includes a downlink transmitter 10 and an uplink receiver 11 on a network side, a downlink receiver 12 and an uplink transmitter on a subscriber side. It consists of (13).

The downlink transmitter 10 on the network side transmits data to the downlink receiver 12 using a constant reference clock, and the downlink receiver 12 on the subscriber side recovers the transmission clock on the network side from the received data. . In addition, the uplink transmitter 13 at the subscriber side receives the recovered clock signal from the downlink receiver 12 at the subscriber side and transmits the data to the uplink receiver 11 using the received clock signal, and the uplink receiver at the network side ( In 11), the signal is recovered by demodulating the received signal.

In this case, the uplink receiver 11 needs to recover a clock signal to perform a predetermined procedure. The clock frequency of the restored signal has no frequency change factor such as a Doppler effect in an application field such as a high-speed digital subscriber line. Since the clock and frequency used at (10) are synchronized, the symbol timing to be restored by the uplink receiver 11 may have the same frequency as the clock used by the downlink receiver 10 and may have only a phase difference.

Thus, when converting the received signal from analog to digital, only the correct phase can be recovered to quickly restore the symbol timing.

2 is a block diagram showing a configuration of a digital demodulation device using a four-phase modulation (QPSK) method according to an embodiment of the present invention, and receives the sampling position determination signal from the symbol timing recovery unit 28 and receives an analog received from the outside. Analog-to-digital converter 20 for performing a digital conversion to the signal, and the in-phase and quadrature carriers of the received signal generated from the control oscillator 27 is multiplied by the output signal of the analog / digital converter 20 A multiplier 21 for converting a passband signal to a baseband signal, and a sampling timing signal received from the symbol timing recovery unit 28 to determine the sample rate of the digital signal passing through the multiplier 21; A down sampling section 22 for lowering, a low pass filtering section 23 for removing integer frequency components of the original signal spectrum with respect to the signal passing through the down sampling section 22, A resampling unit 26 for receiving a sampling position determination signal from the ball timing recovery unit 28 and sampling a signal for determining a symbol value from the data passing through the low pass filtering unit 23; A symbol timing recovery unit 28 for receiving symbol data from the data signal 26 and performing symbol recovery, a carrier phase recovery unit 29 for recovering the carrier phase by receiving the data signal from the resampling unit 26; A control oscillator 27 for generating an oscillation signal under the control of an output signal from the symbol timing recovery unit 28 and the carrier phase recovery unit 29 and a symbol receiving the output data from the resampling unit 26 And a four-phase modulation (QPSK) decoding section 25 for generating a serial bit stream in accordance with the determined symbol value.

Now, look at the operation of the four-phase modulation (QPSK) demodulation device according to the present invention.

As shown in the figure, the received analog signal is input to the analog / digital converter 20 and converted into a digital signal. The analog / digital converter 20 is designed so that the sampling frequency is an integer multiple of 4 of the symbol rate. The analog / digital converter 20 converts the received analog signal into a digital signal, and the higher the sampling frequency, the more accurate the clock signal is restored. Provide a digital signal that can be In this case, it is assumed that the frequency is N times higher than the symbol rate (where N is an integer).

The multiplier 21 multiplies the digital signal output from the analog / digital converter 20 by the in-phase carrier component and the quadrature carrier component of the received signal, thereby converting the passband signal to baseband. In this case, two digital data paths are generated according to the in-phase carrier component and the quadrature carrier component.

The down sampling unit (or decimation 22) performs N / 4: 1 down sampling (or decimation) on the signal output from the multiplier to lower the sample rate to four times the symbol rate to restore clock phase. This speed is a speed appropriately selected to prevent overlapping of the frequency spectrum while preventing the length of the low pass filter 23 from becoming too long.

The signal passing through the down sampling section 22 passes through the low pass filtering section 23, which has the same response as the waveform shaping filtering section used at the transmitting side, and serves as a matching filter section, while being an integer multiple of the original signal spectrum. The components are removed and input to the resampling unit 26.

The resampling unit 26 samples a signal for determining a symbol value from data corresponding to four times the symbol rate, thereby recovering the symbol timing recovery unit 28, the carrier phase recovery unit 29, and the symbol value. The determination unit 24 is provided.

The symbol value determining unit 24 receives a sampled signal from the resampling unit 26 and determines a correct symbol value, and transmits the determined symbol value to the four-phase modulation (QPSK) decoding unit 25. to provide. The four-phase modulation (QPSK) decoding unit 25 receives an output from the symbol value determining unit 24 and converts the input signal into a serial bit stream according to the in-phase symbol and the orthogonal symbol, respectively, and outputs the serial bit stream. The unit 28 generates a sampling decision signal according to the data input from the resampling unit 26 and provides it to the down sampling unit 22, the resampling unit 26, and the control oscillator 27. do. On the other hand, the carrier phase recovery unit 29 determines the value to be multiplied by the multiplier 21 by modifying the value of the control oscillator 27 according to the degree of error of the carrier phase.

FIG. 3 is a block diagram showing an exemplary configuration of a symbol timing recovery unit of the demodulation device shown in FIG. 2, and is a first in phase signal that is continuous in a symbol period among the output signals from the resampling unit 26 of FIG. The in-phase signal transition detector 30 which receives the signal and the second signal and finds the change in the value of the in-phase signal, and the in-phase at an intermediate point between the first signal and the second signal output from the resampling unit 26. Among the output signals from the in-phase signal error predictor 31 and the output signal from the resampling unit 26, which receive a third signal as a signal and calculate a difference from the average value at the time of transition of the fourth signal and the in-phase signal, which are average values of the in-phase signal, A quadrature signal transition detector 32 which receives a fifth signal and a sixth signal that are continuous quadrature signals in a symbol period, and finds a change in the quadrature signal value, and outputs from the resampling unit 26; Orthogonal phase which receives a seventh signal which is an orthogonal signal at an intermediate point in time between the fifth signal and the sixth signal and calculates a difference from an average value at the time of transition of the orthogonal signal and the eighth signal which is an average value of the orthogonal signal A first multiplier 34 for multiplying the signal error predictor 33 with the output from the in-phase signal transition detector 30 and the in-phase signal error predictor 31 to calculate the magnitude and direction of the error of the in-phase signal; A second multiplier 35 for multiplying the outputs of the quadrature signal transition detector 32 and the quadrature signal error predictor 33 and calculating the magnitude and direction of the error of the quadrature signal; and the first and second multipliers The adder 36 receives an initialization command from the threshold detector 38 by adding an output, and obtains a timing error for each symbol unit. The timing error, which is the output of the adder 36, is newly applied from the time when there is an instruction. A threshold detector 38 for generating a signal to the accumulator 37 and the sampling positioner 39 when the accumulator 37 and the output of the accumulator 37 are compared with a threshold which is already set. While storing the sampling positioner 39 for correcting the sampling position value in accordance with the output signal from the detector 38, and the time point for sampling in the down sampling section 22 and the re-sampling section 26 of FIG. If there is a control signal of the sampling positioner 39, it is provided with the present status register 40 which changes a register value according to the signal.

Now, look at the operation of the symbol timing recovery unit as follows.

For the in-phase signal, the in-phase signal transition detector 30 finds a change in the in-phase signal value, and the in-phase signal error predictor 31 calculates a difference from the average value at the time of transition of the in-phase signal. The first multiplier 34 calculates the magnitude and direction of the error of the in-phase signal. Similarly, for the quadrature signal, the quadrature signal transition detector 32 determines whether or not the quadrature signal is transitioned, and the quadrature signal error predictor 33 obtains the difference from the average value at the time of transition of the quadrature signal. The second multiplier 35 calculates the magnitude and direction of the error of the quadrature signal. Thus, the adder 36 adds the errors of the in-phase signal and the quadrature signal thus obtained to obtain a timing error for each symbol unit. The accumulator 37 and the threshold detector 38 serve as a lowpass filter and generate a signal to the sampling positioner 39 to correct a sampling position value whenever the threshold is exceeded. Therefore, the sensitivity of the symbol timing function may be adjusted according to the threshold of the threshold detector 38. The present state register 40 stores the time points for sampling by the down sampling unit 22 and the resampling unit 26 in FIG. 2 and changes the control signals for sampling positioning if there is a control signal.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the spirit of the present invention for those skilled in the art to which the present invention pertains, and the above-described embodiments and accompanying It is not limited to the drawing.

As described above, the present invention can facilitate symbol timing recovery in the uplink of a high-speed digital subscriber line, and can realize fast symbol recovery by exponentially tracking symbol phase, and much faster than symbol rate for symbol timing recovery. While using a symbol timing recovery method of selecting and writing data pre-sampled at a high frequency, symbol timing can be restored without performing unnecessary operations such as interploation. In addition, by dividing the sampling blocks into multiple stages, the complexity of the demodulator can be reduced exponentially than when they are gathered in one place, and the symbol timing recovery function for the full digitalization of the four-phase modulation (QPSK) demodulation function. It is effective to realize digitalization of the system economically and effectively.

Claims (3)

Analog / digital conversion means for converting an analog signal received from the outside into a digital signal; First multiplication means for converting a pass band signal into a base band signal with respect to the output signal of the analog / digital conversion means; Down sampling means for lowering a sample rate of a signal passing through said first multiplication means by a predetermined multiple in accordance with an applied sampling positioning signal; Low pass filtering means for removing integer frequency components of the original signal spectrum with respect to the output signal of the down sampling means; Resampling means for performing sampling for symbol value determination from data passing through the low pass filtering means in accordance with an applied sampling positioning signal; Symbol timing recovery means for receiving the resampled data from the resampling means and performing symbol timing recovery and providing a sampling positioning signal to the down sampling means and the resampling means; Carrier phase recovery means for restoring a carrier phase by receiving the resampled data from the resampling means; Control oscillation means for generating an oscillation signal by correcting the signal recovered by the carrier phase restoration unit according to a carrier phase error signal which is an output signal of the symbol timing restoration means; Symbol value determining means for receiving data output from the resampling means and determining a symbol value; And Decoding means for generating a serial bit stream in accordance with the symbol value determined by the symbol value determining means Digital demodulation device for the uplink of the high-speed digital subscriber line comprising a. The method of claim 1, The symbol timing recovery means, In-phase signal transition detection means for receiving a in-phase signal that is continuous in a symbol period among the output signals from the re-sampling means and finding a change in in-phase signal value; In-phase signal error predicting means for receiving an in-phase signal at an intermediate point of the in-phase signal that is continuous in a symbol period output from the re-sampling unit, and calculating a difference from an average value of the in-phase signal at the transition point of the in-phase signal; Orthogonal signal transition detection means for receiving a quadrature signal continuous in a symbol period among the output signals from the resampling means and finding a change in the quadrature signal value; Orthogonal signal error predicting means for receiving an orthogonal signal at an intermediate time point of the orthogonal signal which is continuous in a symbol period output from the resampling means, and calculating a difference from an average value of the orthogonal signal at the transition point of the orthogonal signal; Second multiplication means for multiplying the output from the in-phase signal transition detecting means and the in-phase signal error predicting means to calculate an error magnitude and a direction of the in-phase signal; Third multiplication means for multiplying the outputs of the quadrature signal transition detecting means and the quadrature signal error predicting means to calculate an error magnitude and a direction of the quadrature signal; Adding means for adding timings of the second and third multiplication means to obtain a timing error for each symbol unit instant; Accumulating means for accumulating timing errors which are outputs of the adding means from the time of initialization; Threshold detection means for comparing the output of the accumulation means with a preset threshold value; Sampling position determining means for correcting a sampling position value in accordance with an output signal from said threshold detection means; And A current state register means for storing the time point of sampling by the down sampling means and the resampling means, and changing a register value in accordance with the signal if there is a control signal from the sampling position determining means. Digital demodulation device for the uplink of the high-speed digital subscriber line comprising a. The method according to claim 1 or 2 The sampling frequency of the analog / digital converting means is set to be an integer multiple of 4 of the symbol rate, And the down sampling means lowers the sample rate to be four times the symbol rate. The uplink four-phase modulation (QPSK) demodulation device for a high-speed digital subscriber line.

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